"================================================================================================ #TITLE 'ZEUS C&C SLAVE PLD2' ; #ENGINEER 'Martin Postranecky / Dominic A Hayes'; #COMPANY 'University College London'; #COMMENT ''; "================================================================================================ "MODIFIED "12jan00 leb2 -> /leb2. "31jan00 mdb demux selected by daout (as originally specified) not da. "11feb00 clrtestbusy converted to pulse before reset of q1 (testbusy) in pld-2/4. "16feb00 error bit moved in reg04 and 06 in pld-2/2. "17feb00 a_abortout removed from RESET signal of q1 in pld2-2/4 " lasttrig_abort added to SLAVE state register (includes addition of PROC lastabort). "25feb00 q2 removed from lasttrig_abort circuit pld-2/5. "======================================================================================= FUNCTION sync "dual FF synchronization "Called by SLAVE PLD-2/1 (INPUT in, sclk_4, noa_rst); NODE nsclk_4, out; NODE q1 CLOCKED_BY sclk_4 RESET_BY noa_rst; NODE q2 CLOCKED_BY nsclk_4 RESET_BY noa_rst; nsclk_4 = /sclk_4; q1 = in; q2 = q1; out = q2; RETURN out; END sync; "======================================================================================= "----------------------------------------------------------------------- FUNCTION level_to_pulse "Converts input level into a single pulse approx 2tPD long. (INPUT level, reset); NODE pulse CLOCKED_BY level RESET_BY clr NO_REDUCE; NODE clr; RETURN pulse; clr = pulse + reset; "NB noa_rst is defined LOW_TRUE in this src. pulse = 1; END level_to_pulse; "----------------------------------------------------------------------- " " " "======================================================================================= PROCEDURE gflt_data "SLAVE PLD-2/1 (INPUT reg00, reg02, mdb[7..0], da[1..0], a_abort, a_accept, a_reset, sclk_4, noa_rst; OUTPUT r00[15..0], r02[15..0], mdbout[7..0], daout[1..0], a_abortout, a_acceptout, a_resetout); "------------------------------------------------------------------------------------ "Register00 (VME READ) NODE register00[15..0] CLOCKED_BY sclk_4 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; "------------------------------------------------------------------------------------ "------------------------------------------------------------------------------------ "Register02 NODE register02[15..0] "NB equivalent master register is [11..5] CLOCKED_BY sclk_4 " LSB [4] is set to 0 in master pld2. RESET_BY noa_rst DEFAULT_TO LAST_VALUE; "If fitting a problem remove empty FFs. "------------------------------------------------------------------------------------ " Calls Dual FF sync function for 13 i/ps "----------------------------------------- mdbout[0] = sync(mdb[0], sclk_4, noa_rst); mdbout[1] = sync(mdb[1], sclk_4, noa_rst); mdbout[2] = sync(mdb[2], sclk_4, noa_rst); mdbout[3] = sync(mdb[3], sclk_4, noa_rst); mdbout[4] = sync(mdb[4], sclk_4, noa_rst); mdbout[5] = sync(mdb[5], sclk_4, noa_rst); mdbout[6] = sync(mdb[6], sclk_4, noa_rst); mdbout[7] = sync(mdb[7], sclk_4, noa_rst); daout[0] = sync(da[0], sclk_4, noa_rst); daout[1] = sync(da[1], sclk_4, noa_rst); a_abortout = sync(a_abort, sclk_4, noa_rst); a_acceptout = sync(a_accept, sclk_4, noa_rst); a_resetout = sync(a_reset, sclk_4, noa_rst); " DMUX " Assigns the multiplexed input mdb to registers (A), (B) and (C) "----------------------------------------------------------------- IF (/daout[1] AND /daout[0]) THEN register02[11..4] = mdbout; "rosys, roamb, rousr. (A) ELSIF (daout[1] AND /daout[0]) THEN register00[7..0] = mdbout; "fltn. (B) ELSIF (/daout[1] AND daout[0]) THEN register00[15..8] = mdbout; "gbcn. (C) END IF; "------------------------------------------------------------------- " Assign other register bits "------------------------------------------------------------------- "Register00 " register00[15..8] = (C) " register00[7..0] = (B) "Register02 register02[15..12] = [ 0, 0, a_acceptout, a_abortout ] ; " register02[11..4] = (A) register02[3..0] = [ 0, 0, 0, 0 ] ; r00 = register00; "parameters passed out r02 = register02; " of procedure. END gflt_data; "======================================================================================= " " "======================================================================================= PROCEDURE state_and_com_regs "SLAVE PLD-2/2 (INPUT noa_rst, leb2, reg04, reg06, reg08, bwrite, busy, f_error, error, bplane_accept, bplane_abort, bplane_reset, bplane_error, bplane_f_error, bplane_busy, bplane_empty, a_clkon, a_resetout, testbusy, db[15..0], lasttrig_abort; OUTPUT vsoa_reset, vbusy, vf_error, verror, entestbusy, clrtestbusy, r04[15..0], r06[15..0], r08[15..0]); "------------------------------------------------------------------------------------ "Register04 (ADC WRITE / VME READ) NODE register04[15..0]; "------------------------------------------------------------------------------------ "------------------------------------------------------------------------------------ "Register06 (SLAVE WRITE / VME READ) NODE register06[15..0] CLOCKED_BY /leb2 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; "------------------------------------------------------------------------------------ "------------------------------------------------------------------------------------ "Register08 (VME READ/WRITE SLAVE READ) NODE register08[15..0]; "------------------------------------------------------------------------------------ " Assign register bits "------------------------------------------------------------------- "Register04 register04[15..0] = [ bplane_accept, bplane_abort, bplane_reset, bplane_error, bplane_f_error, bplane_busy, bplane_empty, 0, 0, error, 0, f_error, busy, 0, 0, 0 ] ; "Register06 IF (bwrite AND reg06) THEN register06[15..0] = db; END IF; clrtestbusy = register06[15]; entestbusy = register06[14]; verror = register06[6]; vf_error = register06[4]; vbusy = register06[3]; vsoa_reset = register06[1]; "Register08 register08[15..0] = [ testbusy, 0, 0, lasttrig_abort, a_resetout, 0, 0, 0, 0, 0, 0, a_clkon, 0, 0, 0, 0 ] ; r04 = register04; "procedure r06 = register06; " output r08 = register08; " parameters. END state_and_com_regs; "===================================================================================== " " "===================================================================================== PROCEDURE adc_signals "SLAVE PLD-2/3 (INPUT sclk_4, noa_rst, testbusy, vbusy, abusy, vf_error, af_error, verror, aerror; OUTPUT busy, f_error, error, nerror); NODE q1, q2, q3, q4, q5, q6 CLOCKED_BY sclk_4 RESET_BY noa_rst; q1 = testbusy OR vbusy OR abusy; q2 = q1; busy = q2; q3 = vf_error OR af_error; q4 = q3; f_error = q4; q5 = verror OR aerror; q6 = q5; error = q6; nerror = /q6; END adc_signals; "===================================================================================== " " "===================================================================================== PROCEDURE reset_and_test "SLAVE PLD-2/4 (INPUT sclk_4, noa_rst, entestbusy, clrtestbusy, a_acceptout, a_abortout, vsoa_reset, s_rst; OUTPUT testbusy, oa_reset, noa_reset); NODE q1 CLOCKED_BY a_acceptout RESET_BY /q1_reset; NODE q1_reset; NODE q2 CLOCKED_BY q2_clk RESET_BY /q_reset; NODE q3 CLOCKED_BY sclk_4 RESET_BY /q_reset; NODE q4 CLOCKED_BY sclk_4; NODE q2_clk, q_reset; NODE ClrTestBusyPulse; "used to reset q1. ClrTestBusyPulse = level_to_pulse(clrtestbusy, noa_rst); q1_reset = /noa_rst AND entestbusy AND /ClrTestBusyPulse; q1 = 1; testbusy = q1; q2_clk = (vsoa_reset OR s_rst); q_reset = /noa_rst AND noa_reset; q2 = 1; q3 = q2; q4 = q3; oa_reset = q4; noa_reset = /q4; END reset_and_test; "===================================================================================== " " "------------------------------------------------------------------------------------------------ "copied from MASTER PLD-4/14 PROCEDURE last_abort "SLAVE PLD-2/5 " "Called by Main body (INPUT a_acceptout, a_abortout, noa_rst; OUTPUT lasttrig_abort); NODE q1 CLOCKED_BY a_abortout RESET_BY /q_reset; NODE q3 CLOCKED_BY a_acceptout RESET_BY /q_reset; NODE q_reset; q_reset = /noa_rst AND /q3; q1 = a_acceptout; q3 = q1; lasttrig_abort = q1; END last_abort; "------------------------------------------------------------------------------------------------ "===================================================================================== " MAIN BODY "----------- LOW_TRUE INPUT reg00, reg02, reg04, reg06, reg08, bread, bwrite, leb2; LOW_TRUE INPUT noa_rst; INPUT sclk_4, mdb[7..0], da[1..0], a_abort, a_accept, a_reset, bplane_accept, bplane_abort, bplane_reset, bplane_error, bplane_f_error, bplane_busy, bplane_empty, a_clkon, abusy, af_error, aerror, s_rst; NODE register00[15..0], register02[15..0], register04[15..0], register06[15..0], register08[15..0], lasttrig_abort; NODE dboe; BIPUT db[15..0] ENABLED_BY dboe; INPUT s12[4]; "spare i/0 OUTPUT mdbout[7..0], daout[1..0], a_abortout, a_acceptout, a_resetout, vsoa_reset, vbusy, vf_error, verror, entestbusy, clrtestbusy, busy, f_error, error, nerror, testbusy, oa_reset, noa_reset; "------------------------------------------------------------------------------------- "Call prodcedure: gflt_data "------------------------------------------------------------------------------------- gflt_data "INPUT (reg00, reg02, mdb[7..0], da[1..0], a_abort, a_accept, a_reset, sclk_4, noa_rst, "OUTPUT register00[15..0], register02[15..0], mdbout[7..0], daout[1..0], a_abortout, a_acceptout, a_resetout); "------------------------------------------------------------------------------------- "------------------------------------------------------------------------------------- "Call prodcedure: state_and_com_regs "------------------------------------------------------------------------------------- state_and_com_regs "INPUT (noa_rst, leb2, reg04, reg06, reg08, bwrite, busy, f_error, error, bplane_accept, bplane_abort, bplane_reset, bplane_error, bplane_f_error, bplane_busy, bplane_empty, a_clkon, a_resetout, testbusy, db[15..0], lasttrig_abort, "OUTPUT vsoa_reset, vbusy, vf_error, verror, entestbusy, clrtestbusy, register04[15..0], register06[15..0], register08[15..0]); "------------------------------------------------------------------------------------- "------------------------------------------------------------------------------------- "Call prodcedure: adc_signals "------------------------------------------------------------------------------------- adc_signals "INPUT (sclk_4, noa_rst, testbusy, vbusy, abusy, vf_error, af_error, verror, aerror, "OUTPUT busy, f_error, error, nerror); "------------------------------------------------------------------------------------- "------------------------------------------------------------------------------------- "Call prodcedure: reset_and_test "------------------------------------------------------------------------------------- reset_and_test "INPUT (sclk_4, noa_rst, entestbusy, clrtestbusy, a_acceptout, a_abortout, vsoa_reset, s_rst, "OUTPUT testbusy, oa_reset, noa_reset); "------------------------------------------------------------------------------------- "------------------------------------------------------------------------------------- "Call prodcedure: reset_and_test "------------------------------------------------------------------------------------- last_abort "INPUT (a_acceptout, a_abortout, noa_rst, "OUTPUT lasttrig_abort); "------------------------------------------------------------------------------------- "----------------------------------------------- " Assign data to the vme databus biput db "----------------------------------------------- dboe = bread AND (reg00 OR reg02 OR reg04 OR reg06 OR reg08); "databus output enable. IF (bread) THEN " VME READ "---------- IF (reg00) THEN "VME READs register00. db = register00; ELSIF (reg02) THEN "VME READs register02. db = register02; ELSIF (reg04) THEN "VME READs register04. db = register04; ELSIF (reg06) THEN "VME READs register06. db = register06; ELSIF (reg08) THEN "VME READs register08. db = register08; END IF; END IF; "------------------------------------------------ "END MAIN BODY "=======================================================================================