DESCRIPTION OF BUSY's on TIM-0 & 1 & 2 ====================================== *** DRAFT -2- *** MP-UCL, 05 Feb. 2002 1) On PLD-2, there are internal busys, which get asserted while any of the internally-generated TTC(x) functions are being generated. Used to be called /BUSYA, /BUSYB, etc.... Now I think they are called "BUSYECR", "BUSYFER", etc. They should be as long as the SCT serial code for each 'fast command' : L1A : 3 clocks BCR, FER, ECR, spare : 7 clocks CAL : 27 + pipeline-delay-to-trigger + 3 clocks 2) "OA_BUSY" is an OR of all above BUSYs and of "TESTBUSYON" - ( "OA_BUSY" in the Status Register 6 bit 2 should NOT get asserted when "TIM-OK" goes LOW = ie. not OK ) 3) "TESTBUSYON" is a busy line which is enabled by Commands Register 1 bit 13 "EnTestBusy", and cleared by Commands Register 1 bit 14 "ClrTestBusy" and/or by "OA_RESET" "TESTBUSYON" is set by the next L1A after being enabled, and should prevent any internally-generated or externally-received fast commands after this L1A being acted upon "TESTBUSYON" is also output to the Status Register 6 bit 14 4) "INTBUSY" is the "OA_BUSY" shown in the Status Register 6 bit 2 - ( "INTBUSY" & "OA_BUSY" in the Status Register 6 bit 2 should NOT get asserted when "TIM-OK" goes LOW = ie. not OK ) 5) "VBUSY" is set in Commands Register 1 bit 7 6) "EXTBUSY" is the OR of externally-input "NIMEXTBUSY" and "ECLEXTBUSY" from the front panel It is also a bit 0 in Status Register 6 7) Front panel signal "NIMEXTBUSYIN" is enabled onto the "NIMEXTBUSY" line by selecting link LK2 pins 1+2 8) Front panel signal "NIMEXTBUSYIN" is enabled onto the "EXTRODBUSYIN" line by selecting link LK2 pins 2+3 In case of par. 8) the "EXTRODBUSYIN" should be grounded by selecting link LK2 pins 3+4 9) "BUSYOUT" is the OR of a) "OA_BUSY" ( same as "INTBUSY" ) enabled by "EnIntBUSY" in Enables Register 0 bit 7 b) "EXTBUSY" enabled by "EnExtBUSY" in Enables Register 0 bit 15 c) "VBUSY" from Commands Register 1 bit 7 d) "RODBUSY", enabled by "EnRODBUSY" in TTC Enable Register 12 bit 7 It is also a bit 3 in Status Register 6 10) "BUSYOUTB" is the buffered "BUSYOUT" sent to 'TIM BUSY' LED 11) "nBusyTrig2" is same as "BUSYOUT" above, but with the "OA_BUSY" ( same as "INTBUSY" ) being permanently enabled ( there is no "EnIntBUSY" ) 12) "NIMBUSYOUT" is a front panel output of the "BUSYOUTB" signal ( buffered version of "BUSYOUT" ), and can be selected by link LK4 to be either +ve or -ve going 13) "ECLBUSYOUT" is a front panel output, which is selected by link PL20 to be either "BUSYOUTB" signal as above ( PL20 pins 1+2 ), or the "MEXTBUSYOUT" signal ( PL20 pins 2+3 ) 14) "MEXTBUSYOUT" is the "EXTBUSY" signal enabled by "EnExtBUSY" in Enables Register 0 bit 15 It is also a bit 1 in Status Register 6 15) "VRODBUSY" is set in Commands Register 1 bit 8 16) "RODBUSYOUT" is a front panel output, which is selected by link LK1 to be either NIM-type signal "TIM_BUSY" ( LK1 pins 2+3 ) - which can be selected either +ve or -ve going by link LK7 - or TTL-type signal "FP_BUSY_OUT" ( LK1 pins 1+2 ) - ( "ROD_CRATE_BUSYOUT" ( ie. also "FP_BUSY_OUT", "FP_ROD_CRATE_BUSYOUT", "ROD_CRATE_BUSYOUT, "TIM_BUSY_OUT", "TIM-BUSY" and "RODBUSYout" ) should NOT get asserted when "TIM-OK" goes LOW = ie. not OK ) - ( it should BE asserted while the TIM is in "SAMODE" ) 17) "FP_BUSY_OUT" is the "FP_ROD_CRATE_BUSYOUT", which is the same as "ROD_CRATE_BUSYOUT 18) "ROD_CRATE_BUSYOUT" is the OR of a) masked OR of all the ROD-BUSY(x) signals received from TIM backplane ( see ROD Busy Register 16 and ROD Mask Register 15 ) b) "EXTRODBUSYIN" input from the front panel ( see par.8 ) and enabled by the "EnRODBUSY" bit 7 the TTC Enables Register 12 c) "VRODBUSY from Commands Register 1 bit 8 d) "SaMode" from Status register 6 bit 11 19) "RODBUSYout" is the "ROD_CRATE_BUSYOUT" set in bit 7 of Status Register 6 20) "TIM_BUSY_OUT" is the "ROD_CRATE_BUSYOUT" sent to TIM backplane J3 pin 21D 21) "TIM-BUSY" is the "ROD_CRATE_BUSYOUT" sent to the 'ROD BUSY' LED 22) BurstBUSY, SeqBUSY, SinkBUSY - see Status Register 6 This version : MP-UCL, 05 Feb. 2002 Previous versions : 05 Feb. 2002 28 Jan. 2002 26 Jan. 2002