TIM-1 PROTOTYPE MODULE SETTING-UP : =================================== MP-UCL, 26 May 2005 NOTE 1: Default setup is indicated by '#' ======= NOTE 2: IC numbers ( Uxx ) refer to the nearest IC receiving the ======= signal selected by the link/switch etc. NOTE 3: Diagram numbers refer to the circuit schematics page with ======= the relevant link/switch etc - see PC3162M dated 17-05-2001 1) Set VME Base Address switches : ------------------------------- ( Diag.07 ) SW3 : sets A16 - A19 # default : SW3 = 0 SW4 : sets A20 - A23 SW4 = F SW5 : sets A24 - A27 SW5 = D SW6 : sets A28 - A31 SW6 = 0 ( this default sets the A24-A28 = 13 ie. the ROD Crate TIM Slot Geographical Address GA(4-0)* = 10010 ) 2) Set various Delay Switches : ---------------------------- NOTE 4: Note that the LEAST SIGNIFICANT DELAY BIT "A0" is the top slide ======= ie. nearest the TOP edge of the TIM-1 PCB, with the bit "A5" ( MSB ) being the bottom slide. The "ON" position ( ie. signal An = 0 ) is with the relevant slide towards the FRONT PANEL of the TIM-1 PCB ( as marked WHITE ). The "OFF" position ( ie. signal An = 1 ) is with the relevant slide towards the BACKPLANE CONNECTORs of the TIM-1 PCB. Any other lever markings or numbers on actual switch bodies are irrelevant ( eg. switches are marked 6-1 instead of 0-5 ). ( Diag.08/U55 ) SW9: ROD Setup delay DL2 # all ON (ie.=0) ( Diag.08/U56 ) SW7: BCCLK1 Setup delay DL3 # all ON ( 0 ) ( Diag.08/U57 ) SW8: TIM Setup delay DL4 # all ON ( 0 ) ( Diag.09/U66 ) SW10: Trig. Window Delay Setup(*): # 011000 (18hex) ( Diag.09/U67 ) SW11: Trig. Window Size Comp.(*) : # 000010 ( 2 ) (*) NOTE that the "Trigger Window" has been calibrated with respect to the clock "PCLKB" on Test Point PL126. With the above default setting of ROD SETUP delay, this "PCLKB" clock is about 22 nsec earlier then the "NIMCLKOUT" clock output on the front panel socket SK11. ( See appendix for calibrating to different clocks ) /cont: - 2 - 3) 2-pin Links : ------------- ( Diag.07/U79 ) PL37 in # bypasses VME interrupt IACK daisy-chain out enables VME interrupt IACK daisy-chain ( Diag.07/U32 ) PL42 out # spare VME address link ( Diag.07/U32 ) PL84 in selects switch-set VME Base Address ( see par. 1 ) out # VME Base address set to VME GA(4-0)* = 10010 ( Diag.01/J2 ) PL190 in connects -5V2 bus to Jaux/9A,B,C out # isolates -5V2 bus from Jaux/9A,B,C PL191 out # -ditto- Jaux/10A,B,C PL192 out # -ditto- J2/4C PL193 out # -ditto- J2/7A PL194 out # -ditto- J2/13A PL195 out # -ditto- J2/19A PL196 out # -ditto- J2/19C ( Diag.14/U78 ) PL175 in disables -5V2 DC converter out # enables -5V2 DC converter ( Diag.14/U78 ) PL181 in # connects outputs from -5V2 DC converter onto -5V2 bus out isolates outputs from -5V2 bus PL182 in # - ditto - PL183 in # - ditto - NOTE 5: Three links PL181, 182, 183 to be used together ======= ( Diag.14/U75 ) PL173 in enables TIM_BUSY_OUT onto backplane out # disables TIM_BUSY_OUT ( Diag.14/U75 ) PL174 in overrides P3 b/plane drivers disable by ROD_SENSE out # P3 b/plane drivers only enabled by correct ROD_SENSE ( Diag.02/U39 ) PL121 in # sets stand-alone internal FER = ECR out sets FER independent from ECR ( Diag.13/U95 ) PL180 in # allows TTCB(n) outputs to be enabled by correct NTIMOUTEN out disables TTCB(n) outputs ( Diag.13/U98 ) SB19 in connects input clock onto the test point PL197/A out # isolates input clock from the test point PL197/A ( Diag.07/U12 ) SB1-SB10 VME Clocking Delay Line DL0 setup ==== THESE LINKS ARE ALREADY PROGRAMMED ON PCB ==== =================================================== /cont: - 3 - 4) 3-pin Links : ------------- ( Diag.15/U16 ) LK3 pins 1+2 # NIMTRIGINOUT = true 2+3 NIMTRIGINOUT = inverted LK4 pins 1+2 # NIMBUSYOUT = true 2+3 NIMBUSYOUT = inverted LK5 pins 1+2 # NIMTRIGOUT = true 2+3 NIMTRIGOUT = inverted LK6 pins 1+2 # NIMCLKOUT = true 2+3 NIMCLKOUT = inverted ( Diag.15/U24 ) LK7 pins 1+2 # RODBUSYOUT = true 2+3 RODBUSYOUT = inverted ( Diag.15/SK15) LK1 pins 2+3 # RODBUSYOUT = NIM standard 1+2 RODBUSYOUT = TTL standard ( Diag.16/U20 ) PL20 pins 2+3 # ECLBUSYOUT = BUSYOUTB 1+2 ECLBUSYOUT = MEXTBUSYOUT ( Diag.14/U75 ) PL172 pins 2+3 TIMOUTEN, which enables TIM backplane outputs, is always enabled 1+2 # NTIMOUTEN is enabled only in the correct TIM slot ( by VME GA(4-0)* = 10010 ) 5) 4-pin Links : ------------- ( Diag.15/U3 ) LK2 pins 2+3 NIMEXTBUSYIN -> EXTRODBUSYIN 1+2 # NIMEXTBUSYIN -> NIMEXTBUSY & 3+4 # plus EXTRODBUSYIN = 0 /cont: - 4 - 6) NOTE 6: The following links are DIAGNOSTIC TEST POINTS ONLY, ======= with EVERY PIN "B" CONNECTED TO GND ==== DO NOT PUT ANY LINKS BETWEEN PINS "A" and "B" ! ==== ========================================================== ( Diag.04/U54 ) PL141 - PL170 PLDs spare bus test points ( Diag.13/U98 ) PL188, PL189, PL197 Input Clock test points ( Diag.16/U19+U20 ) PL10-15 & PL47-50 TTC(x) output test points 7) NOTE 7: The following TEST POINTS can be used to set-up ======= correct timing relationships ( Diag.05/U59 ) PL132 SEQUBUSY ( SEQUENCER ) PL133 XSEQCLK1 PL134 XSEQTRIG ( Diag.12/U65 ) PL127 FIFO_L1ID_LOW(0) ( FIFO ) PL128 IDENB PL129 IDCLKB ( DIAG.13/U61 ) PL126 PCLKB ( BACKPLANE ) PL185 TTCCLKB PL186 NTTCOUT(7) 8) "TRIGGER WINDOW" CALIBRATION PROCEDURE : The "Trigger Window" allows you to select only those external triggers with selected timing relationship with respect to selected clock. This is useful for random triggers ( eg. from cosmics ). Please note that this feature operates on EXTERNAL TRIGGERs only. - To calibrate this feature for any particular clock, pre-select the Trigger Window and the NIM/ECL external trigger ( Register 0 Bits 6 and 9 'on' ). Decide to which clock and at which point of the clock chain you want to calibrate this feature - this could be outside the TIM module. Hook-up one scope probe to this point. - To observe the Trigger Window pulse, hook-up the second scope probe to U68 pin 5 on the TIM module ( see diag. 09 ). - Set WINDOW SIZE = 2 ( Register 4 Bit 1 'on' ). Set SW11 ( Trigger Window Size Compensation ) so there is only a sharp short +ve spike on U68 pin 5. This spike must disappear when Reg.4 = 0. - Set WINDOW SIZE = 10 ( Reg.4 Bit 4 'on' ) and set SW10 ( Trigger Window Delay Setup ) so that the +ve edge of the window pulse output is coincident with the +ve edge of the selected clock. The WINDOW SIZE is valid between 0 and ~2f in steps of 0.5 nsec. This window can then be scanned over the whole of the 25 nsec clock period by the WINDOW DELAY setting. This version : MP-UCL, 26 May 2005 Previous versions : 26 May 2005 24 Jun. 2002 10 Jun. 2002 21 Mar. 2002 30 Jan. 2002 22 Jan. 2002 07 Dec. 2001 18 Sep. 2001