HARDWARE CHANGES TO TIM-1 PC3162M MODULE TO PRODUCE NEW VERSION TIM-2 --------------------------------------------------------------------- ================================================================= *** PLEASE DO NOT RE-NUMBER THE COMPONENTS ON THE NEW VERSION *** ================================================================= MP, 11 Feb. 2002 ====|===========|========================================================= Diagram No: ACTION ====|===========|========================================================= A) LAYOUT : ---------------- 1b) 11 Move J21 & J22 connectors forward to align the new TTCrx PCB opto-connector with the previous SK1 position Note that SK1 will need to be moved upwards and towards the front panel to the position of the previous cutout for the opto-connector *** see enclosed drawings for dimensions *** PLEASE ENSURE THE NEW EXTRA-LONG "PRECI-DIP" CONNECTORS ( Part No: 714-91-125-41-001001 FOR single 25-pin row ) ARE USED FOR J21 AND J22 2) 01 Replace the existing pads for FUSES FS1, 2, 3, 4, 5 by new smd type for the SCHURTER OMF63 type fuses *** see RS 167-5194 for OHM63 smd fuseholders *** 3) 02 Add a third pin, connected to GND, next to existing pin 1 of PL121, as to allow this existing pin 1 = "INTINECR" to be shorted to GND by a link to the new third pin. 4) 08+09 Rotate DIL switches SW8, 9, 10, 11 by 180deg, so that pin 1 is connected to pin 23 = A0 of the adjacent Delay Line, pin 2 to A1, etc... ( pins 7-12 will then become shorted to GND ) 5) 13 Replace SB19 by a 2-pin header PLxx /cont: B) TOP SILK SCREEN : ------------------------- 1) 07 Add prominent labels to the four rotary switches ( ie. ENLARGE the existing "SWx" labels above each switch and add the "Axx-xx" legend to them ) : SW3 : A16-19 SW4 : A20-23 SW5 : A24-27 SW6 : A28-31 2) 02 Mark the new pin 1 of the 3-pin header PL121 by a marker 3) 14 Mark the pin 1 of the 3-pin header PL 172 by a marker C) BOTTOM SILK SCREEN : ---------------------------- 1) 07 Add prominent labels to the four rotary switch positions : SW3 : A16-19 SW4 : A20-23 SW5 : A24-27 SW6 : A28-31 2) - Rename this module "TIM-2" ( instead of "TIM-1" ) on the legend on the bottom silk D) FRONT PANEL : --------------------- 1) 11 Change the front panel cutout to fit the new TTCrx opto-connector ( see A-1b ) 2) - Add a third SCHROFF f/panel mounting block to the centre of the f/panel - above the "new" cutout ? 3) 17 Swap the legends on the f/panel for DS3 ( "OR" <-> "+12" ) 4) - Rename this module "ATLAS TIM-2" ( instead of "ATLAS TIM-0" ) on the front panel top /cont: E) CIRCUIT DIAGRAMS : -------------------------- 1) 01 Replace the existing pads for FUSES FS1, 2, 3, 4, 5 by new smd type for the SCHURTER OMF63 type fuses FS1, 2, 3 = 5A FS4, 5 = 10A *** see RS 167-5194 for OHM63 fuseholders *** 2) 01 Remove all connections from J2 and from JAUX to the "VEEIN" supply bus = ie. remove links PL190, 191, 192, 193, 194, 195, 196 *** Plus see also par. 31) below *** 3) 01 Add new signal "TIM-OK" to J3 pin A14 4) 02 Add a third pin, connected to GND, next to existing pin 1 of PL121, as to allow this existing pin 1, connected to PLD-2/U39 pin C23 = "INTINECR", to be shorted to GND by a link to the new grounded third pin of PL121 ---- 5) 02 Rename signal SGBD[1] from PLD-2/U39 pin C17 into a new signal line "TTC_READY_IN" 6) 02 Rename signal SGBD[0] from PLD-2/U39 pin D17 into a new signal line "TIM-OK_OUT" 7) 02 Add a new signal line "NSA_CLK_MODE" to PLD-2/U39 pin D16 8) 02 Add a new signal line "NTTC_CLK_MODE" to PLD-2/U39 pin B18 9) 02 Add a new signal line "TTCCLKIN" to PLD-2/U39 pin B19 10) 02 Rename signal SGBD[5] from PLD-2/U39 pin AE18 into a new signal line "ENEXTRODBUSY" ---- 11) 02 Rename signal S2_3[6] from PLD-2/U39 pin K2 into a new signal line "SACLKON_OUT" 12) 02 Rename signal S2_3[7] from PLD-2/U39 pin L2 into a new signal line "TTCCLKON_OUT" 13) 02 Rename signal s2_6[7] from PLD-2/U39 pin AD2 into a new signal line "ENTTCCLK" 14) 02 Rename signal s2_6[6] from PLD-2/U39 pin AC2 into a new signal line "ENEXTRODBUSY_IN" ---- /cont: 15) 04 Rename signal s2_6[7] from PLD-6/U77 pin 107 into a new signal line "ENTTCCLK" 16) 04 Rename signal "ENBCCLK" from PLD-6/U77 pin 68 into a new signal line "NENTTCCLK" 17) 04 Rename signal s2_6[6] from PLD-6/U77 pin 108 into a new signal line "ENEXTRODBUSY_IN" ---- 18) 05 Rename signal SGBD[5] from PLD-8/U76 pin 54 into a new signal line "ENEXTRODBUSY" 19) 06 Rename signal SGBD[1] from PLD-3/U38 pin 47 into a new signal line "TTC_READY_IN" 20) 06 Rename signal SGBD[0] from PLD-3/U38 pin 46 into a new signal line "TIM-OK_OUT" 21) 06 Rename signal S2_3[6] from PLD-3/U38 pin 147 into a new signal line "SACLKON_OUT" 22) 06 Rename signal S2_3[7] from PLD-3/U38 pin 148 into a new signal line "TTCCLKON_OUT" ---- 23) 06 Rename signal SGBD[1] from PLD-9/U43 pin 237 into a new signal line "TTC_READY_IN" 24) 06 Rename signal SGBD[0] from PLD-9/U43 pin 238 into a new signal line "TIM-OK_OUT" ---- 25) 02-06 Rename signal SGBD[0] to "TIM-OK_OUT", signal SGBD[1] to "TTC_READY_IN", and signal SGBD[5] to "ENEXTRODBUSY" on ALL OTHER PLD ICs U32, U38, U43, U71, U72, U54, U59, U76 ---- 26) 06 Change R101 & R102 to 1k Ohm ( from 22k ) 27) 07 Add a text legend to link PL37 on this schematics : INSERT LINK PL37 TO BY-PASS VME INTERRUPTS DAISY CHAIN 28) 07 Add a text legend to link PL42 on this schematics : LINK PL42 - SPARE VME ADDRESSING LINK /cont: 29) 08 Remove the GND connection from U58 pins 3 & 11 and re-connect to a new signal line "NSA_CLK_MODE", previously being connected to GND 30) 08 Remove Delay Line U56, DIL switch SW7, and associated components 31) 08+09 Rotate DIL switches SW8, 9, 10, 11 by 180deg, so that pin 1 is connected to pin 23 = A0 of the adjacent Delay Line, pin 2 to A1, etc... ( pins 7-12 will then become shorted to GND ) 32) 11 Add a 100pF chip capacitor onto U46 pin 11 33) 11 Remove R125 from J22 ---- 34) 13 Remove U51 pin 1 from "SAMODE" and re-connect to "NTTC_CLK_MODE" 35) 13 Rename signal "ENBCCLK" from U51 pin 19 into a new signal line "NENTTCCLK" 36) 13 Remove U51 pin 9 from "DL3OUT" 37) 13 Remove U51 pin 11 from "CLKINB4" ---- 38) 13 Remove U52 pin 1 from "RUNMODE" and re-connect to "NSA_CLK_MODE" 39) 13 Remove U52 pin 9 from "DL2OUTB" 40) 13 Remove U52 pin 11 from "CLKINB4" ---- 41) 13 Remove U50 pin 16 from "CLKINB3" and re-connect to "CLKINB4" ---- 42) 13 Remove U60 pin 3 from GND and re-connect to pin 2 ( ie. signal "BCCLK1B ) 43) 13 Add a new signal "TTCCLKIN" to U60 pin 17 ---- /cont: 44) 13 Remove PL180 and R112, connecting "NTIMOUTEN" and R111 directly to U95 pin 1 45) 13 Replace SB19 by a 2-pin header PLxx 46) 14 Add a new circuit consisting of two ICs as shown on diagram : SN74LVT244AD ( or equivalent 3V3 smd ) SN74ABT125D plus signals "TIM-OK_OUT", "TIM-OK" and "NTIMOUTEN", with a new 2-pin header link and text legend on this schematics : "REMOVE LINK PLxx TO DISABLE "TIM-OK" OUTPUT TO BACKPLANE" 47) 14 Add text legend to this schematics next to PL173 : REMOVE LINK PL173 TO DISABLE "TIM_BUSY_OUT" OUTPUT TO BACKPLANE 48) 14 Remove links PL181, 182, 183 49) 14 Connect U78 pin 6 etc. directly to "VEEIN" ( instead of "VEE", ie. keeping the fuse FS5 in the line ) *** This will require change to the top layer A and the VEE layer F *** *** Please move the whole circuit of U78 to diagram 1 *** ================================================================= *** PLEASE DO NOT RE-NUMBER THE COMPONENTS ON THE NEW VERSION *** ================================================================= This version : MP-UCL, 11 Feb. 2002 Previous versions : 11 Feb. 2002 08 Feb. 2002 06 Feb. 2002 30 Jan. 2002 23 Jan. 2002 22 Jan. 2002