{"text_format":"5","workbook":"xls","n_sheets":3,"sheets":["Sheet1","Sheet2","Sheet3"],"props":{"creator":"Matthew Warren","last_modified_by":"mp","company":"UCL"},"read":"whole","wrapped":"gz","date_system":"1900","formulas":"cached_only"}

{"sheet":"Sheet1","index":0,"n_rows":533,"n_cols":11,"rows_kept":533,"flags":["formulas_cached_only"]}
["TIM SIGNALS:",null,null,"Current",null,"New"]
["PLD","IO","NAME","Old Source/Dest","Old Source/Dest Discription","Internal or External","TIM or Manager or Other","Source or Dest.",null,"More Info"]
["new","INPUT","ab[15..1]","-","-","e","t","v","VME"]
["pld7","INPUT","ab[15..1]","v","VME","e","t","v","VME"]
["pld1","INPUT","ab[31..1]","v","VME","e","m","v","VME"]
["pld1","OUTPUT","Ack","v","VME","e","m","v","VME"]
["pld1","INPUT","amb[5..0]","v","VME","e","m","v","VME"]
["pld1","INPUT","B_select","j","Jumpers & DIPs","e","m","j","Jumpers & DIPs"]
["pld1","INPUT","base_addr[31..16]","ba","Base Addr. Switches","e","m","ba","Base Addr. Switches"]
["pld1","INPUT","BaseAddr_Select","j","Jumpers & DIPs","e","m","j","Jumpers & DIPs"]
["pld9","INPUT","BCclk1b","cc","Clock Control","e","c","cc","Clock Control","not used on pld9   "]
["pld9","INPUT","BCclk2b","cc","Clock Control","e","c","cc","Clock Control","not used on pld9   "]
["pld9","INPUT","BCnt[11..0]","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","BCntStr","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","BCRin","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","Brcst[7..2]","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","BrcstStr1","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","BrcstStr2","t","TTCrx","e","t","t","TTCrx"]
["pld1","OUTPUT","bRead","bf","Buffer/Fanout","e","t","m","Manager",null,"FF: C:dl1 R:/dl0 "]
["pld2","OUTPUT","BusyOut",3,"Intra-PLD","e","t","f","Front-Panel Signals"]
["pld1","OUTPUT","bWrite","bf","Buffer/Fanout","e","t","m","Manager",null,"FF: C:dl1 R:/dl0 "]
["pld2","OUTPUT","clkIn","cc","Clock Control","e","c","cc","Clock Control"]
["pld3","INPUT","clkInB1","cc","Clock Control","e","t","cc","Clock Control","probably not needed - but could keep it or a similar?   "]
["new","INPUT","Conf_TIM_cclk","-","-","e","t","cr","FPGA Config EEPROM"]
["new","INPUT","Conf_TIM_d","-","-","e","t","cr","FPGA Config EEPROM"]
["new","OUTPUT","ConfROM_ce","-","-","e","m","cr","FPGA Config EEPROM"]
["new","OUTPUT","ConfROM_clk","-","-","e","m","cr","FPGA Config EEPROM"]
["new","OUTPUT","ConfROM_d","-","-","e","m","cr","FPGA Config EEPROM"]
["new","OUTPUT","ConfROM_oe","-","-","e","m","cr","FPGA Config EEPROM"]
["pld2","OUTPUT","CT[5..0]","cc","Clock Control","e","t","cc","Clock Control",null,"FF: C:clk2b CE:Reg0A*/nLEb2 R:/nOA_rst"]
["new","BIPUT","db[15..0]","-","-","e","t","v","VME","not really needed as 'new' - but keeps things tidy"]
["new","BIPUT","db[15:0]","-","-","e","m","v","VME","for updating EEPROM, reading special status bits on Manager"]
["pld9","INPUT","DbErrStr","t","TTCrx","e","t","t","TTCrx"]
["new","BIPUT","DebugBus[15..0]","-","-","e","m","dh","DebugBus Header"]
["new","BIPUT","DebugBus[32..0]","-","-","e","t","dh","DebugBus Header"]
["new","INPUT","DebugMode[3..0]","-","-","e","m","dm","Debug Mode Select","Shared by TIM and Manager"]
["new","INPUT","DebugMode[3..0]","-","-","e","t","dm","Debug Mode Select","Shared by TIM and Manager"]
["pld1","OUTPUT","dl0","dv","VME Delay Unit","e","m","dv","VME Delay Unit"]
["pld1","INPUT","dl1","dv","VME Delay Unit","e","m","dv","VME Delay Unit"]
["pld1","INPUT","dl2","dv","VME Delay Unit","e","m","dv","VME Delay Unit"]
["pld1","INPUT","dl3","dv","VME Delay Unit","e","m","dv","VME Delay Unit"]
["pld9","INPUT","Dout[7..0]","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","DoutStr","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","DQ[3..0]","t","TTCrx","e","t","t","TTCrx"]
["pld6","OUTPUT","eclBCR","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld6","OUTPUT","eclCAL","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld6","OUTPUT","eclECR","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld2","INPUT","EclExt_Clk1","f","Front-Panel Signals","e","c","cc","Clock Control"]
["pld2","INPUT","EclExt_Clk2","f","Front-Panel Signals","e","c","cc","Clock Control"]
["pld2","INPUT","eclExtBusy","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld6","OUTPUT","eclFER","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld6","OUTPUT","eclID","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld6","OUTPUT","eclL1A","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld6","OUTPUT","eclSpare","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld6","OUTPUT","eclTT","f","Front-Panel Signals","e","t","f","Front-Panel Signals",null,"FF: C:clk6 R:/nOA_rst "]
["pld9","INPUT","ECRin","t","TTCrx","e","t","t","TTCrx"]
["pld2","OUTPUT","enIntFER","is","Internal Trig, FER, ECR","e","t","is","Internal Trig, FER, ECR"]
["pld2","OUTPUT","enIntTRIG","is","Internal Trig, FER, ECR","e","t","is","Internal Trig, FER, ECR",null,"FF: C:clk2b CE:Reg00*/nLEb2 R:/nOA_rst"]
["pld2","INPUT","enTTCClk",6,"Intra-PLD","e","t","cc","Clock Control"]
["pld6","OUTPUT","enTTCClk","cc","Clock Control","e","t","cc","Clock Control"]
["pld2","OUTPUT","enWindow","w","Trigger Window","e","t","w","Trigger Window",null,"FF: C:clk2b CE:Reg00*/nLEb2 R:/nOA_rst"]
["pld9","INPUT","EvCntHStr","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","EvCntLStr","t","TTCrx","e","t","t","TTCrx"]
["pld2","INPUT","extInBCREcl","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInBCRNim","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInCALEcl","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInCALNim","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInECREcl","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInECRNim","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInFEREcl","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInFERNim","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInSpareEcl","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInSpareNim","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInTRIGEcl","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","extInTRIGNim","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld8","INPUT","extRodBusyIn","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld8","OUTPUT","fp_rod_crate_busyout","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","INPUT","int_clk1","cc","Clock Control","e","c","cc","Clock Control"]
["pld2","INPUT","int_clk2","cc","Clock Control","e","c","cc","Clock Control"]
["pld2","INPUT","intInECR","is","Internal Trig, FER, ECR","e","t","is","Internal Trig, FER, ECR","Jumpered to intInFER   "]
["pld2","INPUT","intInFER","is","Internal Trig, FER, ECR","e","t","is","Internal Trig, FER, ECR"]
["pld2","INPUT","intInTRIG","is","Internal Trig, FER, ECR","e","t","is","Internal Trig, FER, ECR"]
["pld6","INPUT","L1Ain","t","TTCrx","e","t","t","TTCrx"]
["pld9","INPUT","L1Ain","t","TTCrx","e","t","t","TTCrx"]
["pld3","INPUT","laser_intlck_state","b","Back-Plane Signals","e","t","b","Back-Plane Signals"]
["pld1","INPUT","nASb","v","VME","e","m","v","VME"]
["pld1","INPUT","nBErrb","v","VME","e","m","v","VME"]
["pld1","INPUT","nDS0b","v","VME","e","m","v","VME"]
["pld1","INPUT","nDS1b","v","VME","e","m","v","VME"]
["pld6","OUTPUT","nenTTCClk","cc","Clock Control","e","t","t","TTCrx"]
["pld1","OUTPUT","nErrorLED","fl","Front-Panel LEDs","e","m","fl","Front-Panel LEDs"]
["pld1","INPUT","nGAb[4..0]","v","VME","e","m","v","VME"]
["pld1","INPUT","nGAbp","v","VME","e","m","v","VME"]
["pld1","OUTPUT","nGAoutEn","b","Back-Plane Signals","e","m","b","Back-Plane Signals"]
["pld1","INPUT","nIAckb","v","VME","e","m","v","VME"]
["pld1","INPUT","nIAckinb","v","VME","e","m","v","VME"]
["pld1","OUTPUT","nIAckoutb","v","VME","e","m","v","VME"]
["pld2","INPUT","NimExt_Clk","f","Front-Panel Signals","e","c","cc","Clock Control"]
["pld2","INPUT","nimExtBusy","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld3","INPUT","NimExtBusy","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld1","OUTPUT","nIrqb[7..1]","v","VME","e","m","v","VME"]
["pld1","OUTPUT","nLE1","v","VME","e","m","v","VME"]
["pld1","OUTPUT","nLE2","v","VME","e","m","v","VME"]
["pld1","INPUT","nLWordb","v","VME","e","m","v","VME"]
["pld2","OUTPUT","nOA_busy","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["new","OUTPUT","nOA_rst","-","-","e","t","m","Manager","inverse of OA_rst"]
["pld1","OUTPUT","nOEin","v","VME","e","m","v","VME"]
["pld1","OUTPUT","nOEout","v","VME","e","m","v","VME"]
["pld8","INPUT","nRodBusyb[21..5]","b","Back-Plane Signals","e","t","b","Back-Plane Signals"]
["pld2","OUTPUT","nSA_CLK_MODE","cc","Clock Control","e","t","cc","Clock Control",null,"FF: C:/clkIn R:/nOA_rst "]
["pld7","OUTPUT","nSeqCS","r","RAM","e","t","r","RAM"]
["pld7","OUTPUT","nSeqOE","r","RAM","e","t","r","RAM"]
["pld7","OUTPUT","nSeqWrEn","r","RAM","e","t","r","RAM"]
["pld7","OUTPUT","nSinkCS","r","RAM","e","t","r","RAM"]
["pld7","OUTPUT","nSinkOE","r","RAM","e","t","r","RAM"]
["pld7","OUTPUT","nSinkWrEn","r","RAM","e","t","r","RAM"]
["pld1","OUTPUT","nStop_Clk","cc","Clock Control","e","t","cc","Clock Control","inverse of Stop_Clk   "]
["pld2","OUTPUT","nTTC_CLK_MODE","cc","Clock Control","e","t","cc","Clock Control",null,"FF: C:/TTCClkIn PR:/TTCClkON2 "]
["pld6","OUTPUT","nTTCout[7..0]","b","Back-Plane Signals","e","t","b","Back-Plane Signals",".nsr reports [0..4] only. Don't know why …   "]
["pld1","INPUT","nWriteb","v","VME","e","m","v","VME"]
["pld2","OUTPUT","OA_reset","rst","Resets","e","t","m","Manager",null,"FF: C:OA_reset_set R:reset_count8 "]
["new","OUTPUT","OA_rst","-","-","e","t","m","Manager","inverse of nOA_rst"]
["pld2","OUTPUT","outTRIG","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld2","OUTPUT","outTRIG1","tp","Test Point","e","t","j","Jumpers & DIPs",null,"FF: C:clk2b R:/nOA_rst "]
["pld2","OUTPUT","outTRIGh","tp","Test Point","e","t","j","Jumpers & DIPs"]
["pld3","OUTPUT","r[5..1]","tp","Test Point","e","t","is","Internal Trig, FER, ECR",null,"FF: C:clk3 CE:Reg06*/nLEb2 R:/nOA_rst"]
["pld8","OUTPUT","RBM[15..0]","rsv","Reserved","e","t","rsv","Reserved"]
["pld9","OUTPUT","Resetb","t","TTCrx","e","t","t","TTCrx"]
["pld8","OUTPUT","rod_crate_busyout","fl","Front-Panel LEDs","e","t","fl","Front-Panel LEDs"]
["pld2","OUTPUT","RunMode","fl","Front-Panel LEDs","e","t","fl","Front-Panel LEDs",null,"FF: C:nLEb2 CE:Reg02*bWriteb R:/nOA_rst"]
["pld3","OUTPUT","s[5..1]","is","Internal Trig, FER, ECR","e","t","is","Internal Trig, FER, ECR",null,"FF: C:clk3 CE:Reg06*/nLEb2 R:/nOA_rst"]
["pld3","INPUT","SAClkOn","cc","Clock Control","e","t","cc","Clock Control"]
["pld2","OUTPUT","SAMode","fl","Front-Panel LEDs","e","t","fl","Front-Panel LEDs"]
["pld9","BIPUT","SCL","t","TTCrx","e","t","t","TTCrx",null,"ENABLED_BY /xSCL  "]
["pld9","BIPUT","SDA","t","TTCrx","e","t","t","TTCrx",null,"ENABLED_BY /xSDA  "]
["pld7","OUTPUT","SeqA[14..0]","r","RAM","e","t","r","RAM"]
["pld7","INPUT","SeqClk","r","RAM","e","t","r","RAM"]
["pld7","BIPUT","SeqD[7..0]","r","RAM","e","t","r","RAM",null,"ENABLED_BY SeqRamWrAccess  "]
["pld9","INPUT","SinErrStr","t","TTCrx","e","t","t","TTCrx"]
["pld7","OUTPUT","SinkA[14..0]","r","RAM","e","t","r","RAM"]
["pld7","INPUT","SinkClk","r","RAM","e","t","r","RAM"]
["pld7","BIPUT","SinkD[7..0]","r","RAM","e","t","r","RAM",null,"ENABLED_BY nSinkOE  "]
["new","BIPUT","SpareBus[32..0]","-","-","e","t","m","Manager"]
["pld2","INPUT","sReset","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["pld1","OUTPUT","Stop_Clk","cc","Clock Control","e","t","cc","Clock Control","inverse of nStopClk   "]
["pld9","INPUT","SubAddr[7..0]","t","TTCrx","e","t","t","TTCrx"]
["pld2","INPUT","test_sw","f","Front-Panel Signals","e","t","f","Front-Panel Signals"]
["new","INPUT","TIM_ID[7..0]","-","-","e","t","ti","TIM ID","Part shared TIM hardwired ID - used to be IC buffer direct to DB"]
["new","INPUT","TIM_ID[7..4]","-","-","e","m","ti","TIM ID","Part shared TIM hardwired ID - used to be IC buffer direct to DB"]
["pld2","OUTPUT","TIM_OK_out","b","Back-Plane Signals","e","t","b","Back-Plane Signals"]
["new","INPUT","TIMselect","-","-","e","t","m","Manager"]
["pld2","INPUT","TRIG_win","w","Trigger Window","e","t","w","Trigger Window"]
["pld2","INPUT","TTCClkIn","t","TTCrx","e","c","t","TTCrx"]
["pld3","INPUT","TTCClkOn","cc","Clock Control","e","t","cc","Clock Control"]
["pld9","INPUT","TTCReady","t","TTCrx","e","t","t","TTCrx"]
["pld3","OUTPUT","wd[5..0]","w","Trigger Window","e","t","w","Trigger Window",null,"FF: C:clk3 CE:Reg08*/nLEb2 R:/nOA_rst"]
["pld3","OUTPUT","ws[5..0]","w","Trigger Window","e","t","w","Trigger Window",null,"FF: C:clk3 CE:Reg08*/nLEb2 R:/nOA_rst"]
["pld4b","OUTPUT","BC_Strobe",5,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk4 R:/nOA_rst "]
["pld5","INPUT","BC_strobe","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","OUTPUT","BCID[11..0]","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:clk4 CE:ceBCID R:/nOA_rst"]
["pld4a","INPUT","BCntIn[11..0]","4b,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","BCntIn[11..0]","4a,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","BCntIn[11..0]","4a,4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 CE:strobe R:/nOA_rst"]
["pld4b","INPUT","BCntStrobe",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","BCntStrobe","4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld2","INPUT","bReadb","3,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","bReadb","2,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","bReadb","2,3,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","bReadb","2,3,4a,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","bReadb","2,3,4a,4b,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","bReadb","2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","bReadb","2,3,4a,4b,5,6,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","bReadb","2,3,4a,4b,5,6,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","bReadb","2,3,4a,4b,5,6,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","Burst_Ready",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","OUTPUT","Burst_Ready",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","BusyOut",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","bWriteb","3,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","bWriteb","2,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","bWriteb","2,3,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","bWriteb","2,3,4a,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","bWriteb","2,3,4a,4b,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","bWriteb","2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","bWriteb","2,3,4a,4b,5,6,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","bWriteb","2,3,4a,4b,5,6,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","bWriteb","2,3,4a,4b,5,6,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","CALin",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","CALin",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld2","INPUT","clk2","cc","Clock Control","i","i","i","TIM Internal"]
["pld2","INPUT","clk2b","cc","Clock Control","i","i","i","TIM Internal"]
["pld3","INPUT","clk3","cc","Clock Control","i","i","i","TIM Internal"]
["pld4a","INPUT","clk4","cc","Clock Control","i","i","i","TIM Internal"]
["pld4b","INPUT","clk4","cc","Clock Control","i","i","i","TIM Internal"]
["pld5","INPUT","clk5","cc","Clock Control","i","i","i","TIM Internal"]
["pld6","INPUT","clk6","cc","Clock Control","i","i","i","TIM Internal"]
["pld8","INPUT","clk8","cc","Clock Control","i","i","i","TIM Internal"]
["pld9","INPUT","clk9","cc","Clock Control","i","i","i","TIM Internal"]
["pld3","BIPUT","db[15..0]","2,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal",null,"ENABLED_BY dboe  "]
["pld4a","BIPUT","db[15..0]","2,3,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal",null,"ENABLED_BY dboe  "]
["pld4b","BIPUT","db[15..0]","2,3,4a,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal","ENABLED_BYdboe  "]
["pld6","BIPUT","db[15..0]","2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal",null,"ENABLED_BY dboe  "]
["pld7","BIPUT","db[15..0]","2,3,4a,4b,5,6,8,9","Intra-PLD","i","i","i","TIM Internal",null,"ENABLED_BY dboe  "]
["pld8","BIPUT","db[15..0]","2,3,4a,4b,5,6,7,9","Intra-PLD","i","i","i","TIM Internal",null,"ENABLED_BY dboe  "]
["pld9","BIPUT","db[15..0]","2,3,4a,4b,5,6,7,8","Intra-PLD","i","i","i","TIM Internal",null,"ENABLED_BY dboe  "]
["pld2","BIPUT","db[15..0]","3,4a,4b,5,6,7,8,9","Intra-PLD","i",null,null,"-",null,"ENABLED_BY dboe  "]
["pld2","INPUT","Disable_TRIG",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","OUTPUT","Disable_TRIG",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","enBCID",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enBCID","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","enCALBurst",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","OUTPUT","enCALBurst",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","INPUT","enExtRodBusy","2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","enExtRodBusy","1,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","enExtRodBusy","1,2,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","enExtRodBusy","1,2,3,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","enExtRodBusy","1,2,3,4a,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","enExtRodBusy","1,2,3,4a,4b,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","enExtRodBusy","1,2,3,4a,4b,5,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","enExtRODBusy","1,2,3,4a,4b,5,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","enExtRodBusy","1,2,3,4a,4b,5,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","enExtRodBusy_in",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enExtRodBusy_in",2,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 R:/nOA_rst "]
["pld4a","INPUT","enL1ID",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enL1ID","4a","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 R:/nOA_rst "]
["pld2","OUTPUT","enRandom",3,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b CE:Reg00*/nLEb2 R:/nOA_rst"]
["pld3","INPUT","enRandom",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","enRodBusy",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enRodBusy",2,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 R:/nOA_rst "]
["pld4b","INPUT","enSABCR2",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enSABCR2","4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 R:/nOA_rst "]
["pld4a","INPUT","enSAECR2",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enSAECR2","4a","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 R:/nOA_rst "]
["pld4b","INPUT","enTType",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","enTType","4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 R:/nOA_rst "]
["pld6","INPUT","FERin",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","FERin",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld5","INPUT","fifo_BCID[11..0]","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","fifo_L1ID_high[11..0]","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","fifo_L1ID_low[11..0]","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","fifo_TT[9..0]","ff","FIFO","i","i","i","TIM Internal"]
["pld5","OUTPUT","fs0","ff","FIFO","i","i","i","TIM Internal"]
["pld5","OUTPUT","fs1","ff","FIFO","i","i","i","TIM Internal"]
["pld4b","INPUT","idBCR",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","idBCR","4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk6 R:/nOA_rst "]
["pld5","OUTPUT","IDclkA","ff","FIFO","i","i","i","TIM Internal"]
["pld5","OUTPUT","IDclkB","ff","FIFO","i","i","i","TIM Internal"]
["pld4a","INPUT","idECR",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","idECR","4a","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk6 R:/nOA_rst "]
["pld5","OUTPUT","IDenA","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:IDclkA R:/nOA_rst "]
["pld5","OUTPUT","IDenB","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:IDclkB R:/nOA_rst "]
["pld5","OUTPUT","IDin",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","IDin",5,"Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","idTRIG","4b,6","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","idTRIG","4a,6","Intra-PLD","i","i","i","TIM Internal"]
["pld6","OUTPUT","idTRIG","4a,4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk6 R:/nOA_rst "]
["pld2","OUTPUT","intBusy",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","intBusy",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","intInBCR",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","OUTPUT","intInBCR",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","intInRan",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","OUTPUT","intInRan",2,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:  "]
["pld2","OUTPUT","intTRIG",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","intTRIG",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld4a","OUTPUT","L1_strobe",5,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk4 R:/nOA_rst "]
["pld5","INPUT","L1_strobe","4a","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","L1CntHighStrobe",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","L1CntHighStrobe","4a","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld4a","INPUT","L1CntLowStrobe",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","L1CntLowStrobe","4a","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld4a","OUTPUT","L1IDH[11..0]","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:clk4 R:/nOA_rst "]
["pld4a","OUTPUT","L1IDL[11..0]","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:clk4 R:/nOA_rst "]
["pld2","OUTPUT","MExtBusyOut",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","MExtBusyOut",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld5","OUTPUT","nFIFO_rst","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nIDae","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nIDaf","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nIDef","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nIDff","ff","FIFO","i","i","i","TIM Internal"]
["pld2","INPUT","nLEb2","3,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","nLEb2","2,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","nLEb2","2,3,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","nLEb2","2,3,4a,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","nLEb2","2,3,4a,4b,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","nLEb2","2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","nLEb2","2,3,4a,4b,5,6,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","nLEb2","2,3,4a,4b,5,6,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","nLEb2","2,3,4a,4b,5,6,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld1","INPUT","nOA_rst","2,3,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","nOA_rst","1,3,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","nOA_rst","1,2,4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","nOA_rst","1,2,3,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","nOA_rst","1,2,3,4a,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","nOA_rst","1,2,3,4a,4b,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","nOA_rst","1,2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","nOA_rst","1,2,3,4a,4b,5,6,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","nOA_rst","1,2,3,4a,4b,5,6,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","nOA_rst","1,2,3,4a,4b,5,6,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","nTTae","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nTTaf","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nTTef","ff","FIFO","i","i","i","TIM Internal"]
["pld5","INPUT","nTTff","ff","FIFO","i","i","i","TIM Internal"]
["pld1","OUTPUT","RAMselect",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","RAMselect",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg00",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","Reg00",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg02",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","Reg02",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg04",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","Reg04",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg06",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","Reg06",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg08",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","Reg08",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg0A",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","Reg0A",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg0C",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","Reg0C",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg0E",5,"Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","Reg0E",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg10","4a","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","Reg10",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg12","4a","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","Reg12",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg14","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","Reg14",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg16","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","Reg16",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg18",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","Reg18",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg1A",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","Reg1A",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg1C",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","Reg1C",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg1E",8,"Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","Reg1E",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg20",8,"Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","Reg20",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg22",8,"Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","Reg22",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg24",8,"Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","Reg24",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg26",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","Reg26",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg28",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","Reg28",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg2A","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","Reg2A",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg2C",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","Reg2C",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg2E",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","Reg2E",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg30",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","Reg30",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg32",5,"Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","Reg32",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","OUTPUT","Reg34",5,"Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","Reg34",1,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","rod_crate_BusyOut",3,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","rod_crate_BusyOut",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","RunMode","4a,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","RunMode","3,4b,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","RunMode","3,4a,5,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","RunMode","3,4a,4b,6,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","RunMode","3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","RunMode","3,4a,4b,5,6,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","RunMode","3,4a,4b,5,6,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","RunMode","3,4a,4b,5,6,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","SABCR1",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b R:/nOA_rst "]
["pld6","INPUT","SABCR1",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld4b","OUTPUT","SABCR2",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","SABCR2","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","SACAL",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b R:/nOA_rst "]
["pld6","INPUT","SACAL",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","SAECR1",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b R:/nOA_rst "]
["pld6","INPUT","SAECR1",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld4a","OUTPUT","SAECR2",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","SAECR2","4a","Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","SAFER",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b R:/nOA_rst "]
["pld6","INPUT","SAFER",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","SAMode",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","SASpare",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b R:/nOA_rst "]
["pld6","INPUT","SASpare",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","SATRIG","3,6","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk2b R:/nOA_rst "]
["pld3","INPUT","SATRIG","2,6","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","SATRIG","2,3","Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqBCR",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqBCR",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","SeqBusy",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","SeqBusy",3,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:SeqCountEnClk R:SeqCountEnReset "]
["pld6","INPUT","seqCAL",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqCAL",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqECR",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqECR",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqFER",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqFER",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqID",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqID",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqSpare",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqSpare",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqTRIG",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqTRIG",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","seqTT",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","seqTT",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","SinkBusy",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","OUTPUT","SinkBusy",3,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:SinkCountEnClk R:SinkCountEnReset "]
["pld6","INPUT","Sparein",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","Sparein",6,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld2","OUTPUT","StartSeq",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","StartSeq",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","StartSink",7,"Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","StartSink",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","TestBusyON",3,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:outTRIG1 R:TestBusyONreset "]
["pld3","INPUT","TestBusyON",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld1","INPUT","TIM_OK_OUT","3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","TIM_OK_OUT","1,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","TIM_OK_OUT","1,3,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","TIM_OK_OUT","1,3,4a,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","TIM_OK_OUT","1,3,4a,4b,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","TIM_OK_OUT","1,3,4a,4b,5,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","TIM_OK_OUT","1,3,4a,4b,5,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","INPUT","TIM_OK_OUT","1,3,4a,4b,5,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","OUTPUT","TT_Strobe",5,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk4 R:/nOA_rst "]
["pld5","INPUT","TT_Strobe","4b","Intra-PLD","i","i","i","TIM Internal"]
["pld1","INPUT","TTC_ready_in","2,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld2","INPUT","TTC_Ready_in","1,3,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld3","INPUT","TTC_ready_in","1,2,4a,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4a","INPUT","TTC_ready_in","1,2,3,4b,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","TTC_ready_in","1,2,3,4a,5,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld5","INPUT","TTC_ready_in","1,2,3,4a,4b,7,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld7","INPUT","TTC_ready_in","1,2,3,4a,4b,5,8,9","Intra-PLD","i","i","i","TIM Internal"]
["pld8","INPUT","TTC_ready_in","1,2,3,4a,4b,5,7,9","Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","TTC_ready_in","1,2,3,4a,4b,5,7,8","Intra-PLD","i","i","i","TIM Internal"]
["pld5","OUTPUT","TTclkA","ff","FIFO","i","i","i","TIM Internal"]
["pld5","OUTPUT","TTclkB","ff","FIFO","i","i","i","TIM Internal"]
["pld5","OUTPUT","TTenA","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:TTclkA R:/nOA_rst "]
["pld5","OUTPUT","TTenB","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:TTclkB R:/nOA_rst "]
["pld4b","OUTPUT","TTID[9..0]","ff","FIFO","i","i","i","TIM Internal",null,"FF: C:clk4 CE:ceTTID R:/nOA_rst"]
["pld4b","INPUT","TTIDin[9..0]",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","TTIDin[9..0]","4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 CE:ClkEnTType R:/nOA_rst"]
["pld5","OUTPUT","TTin",6,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","TTin",5,"Intra-PLD","i","i","i","TIM Internal"]
["pld4b","INPUT","TTypeStrobe",9,"Intra-PLD","i","i","i","TIM Internal"]
["pld9","OUTPUT","TTypeStrobe","4b","Intra-PLD","i","i","i","TIM Internal",null,"FF: C:clk9 R:/nOA_rst "]
["pld2","OUTPUT","vBurstGo",3,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 CE:Reg02*bWriteb R:/nOA_rst"]
["pld3","INPUT","vBurstGo",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","vBurstMode",3,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 CE:Reg02*bWriteb R:/nOA_rst"]
["pld3","INPUT","vBurstMode",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld2","OUTPUT","vRodBusy",8,"Intra-PLD","i","i","i","TIM Internal",null,"FF: C:nLEb2 CE:Reg02*bWriteb R:/nOA_rst"]
["pld8","INPUT","vRodBusy",2,"Intra-PLD","i","i","i","TIM Internal"]
["pld6","INPUT","BCRin","t","TTCrx","z","z","z","Deleted","not needed -- already got it (ex-pld9)"]
["pld5","BIPUT","db_h[15..8]","2,3,4a,4b,6,7,8,9","Intra-PLD","z","z","z","Deleted","Split db - same signals","ENABLED_BY dboe_h  "]
["pld5","BIPUT","db_l[7..0]","2,3,4a,4b,6,7,8.9","Intra-PLD","z","z","z","Deleted","Split db - same signals","ENABLED_BY dboe_l  "]
["pld7","INPUT","eclBCR",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld7","INPUT","eclCAL",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld7","INPUT","eclECR",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld3","INPUT","eclExtBusy","f","Front-Panel Signals","z","z","z","Deleted","not needed - already got (ex-pld 2)"]
["pld7","INPUT","eclFER",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld7","INPUT","eclID",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld7","INPUT","eclL1A",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld7","INPUT","eclSpare",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld7","INPUT","eclTT",6,"Intra-PLD","z","z","z","Deleted","not needed - already got (ex-pld6)"]
["pld6","INPUT","ECRin","t","TTCrx","z","z","z","Deleted","not needed -- already got it (ex-pld9)"]
["pld2","OUTPUT","nOA_reset","rst","Resets","z","z","z","Deleted"]
["pld1","OUTPUT","nReg32","v","VME","z","z","z","Deleted"]
["pld1","INPUT","s1_2[7..0]",2,"SpareSigs","z","z","z","Deleted"]
["pld2","INPUT","s1_2[7..0]",1,"SpareSigs","z","z","z","Deleted"]
["pld1","INPUT","s1_5[5..0]",5,"SpareSigs","z","z","z","Deleted"]
["pld5","INPUT","s1_5[5..0]",1,"SpareSigs","z","z","z","Deleted"]
["pld2","INPUT","s2_3[5..0]",3,"SpareSigs","z","z","z","Deleted"]
["pld3","INPUT","s2_3[5..0]",2,"SpareSigs","z","z","z","Deleted"]
["pld2","INPUT","s2_4a[7..0]","4a","SpareSigs","z","z","z","Deleted"]
["pld4a","INPUT","s2_4a[7..0]",2,"SpareSigs","z","z","z","Deleted"]
["pld2","INPUT","s2_6[5..0]",6,"SpareSigs","z","z","z","Deleted"]
["pld6","INPUT","s2_6[5..0]",2,"SpareSigs","z","z","z","Deleted"]
["pld3","INPUT","s3_9[7..0]",9,"SpareSigs","z","z","z","Deleted"]
["pld9","INPUT","s3_9[7..0]",3,"SpareSigs","z","z","z","Deleted"]
["pld4a","INPUT","s4a_4b[7..0]","4b","SpareSigs","z","z","z","Deleted"]
["pld4b","INPUT","s4a_4b[7..0]","4a","SpareSigs","z","z","z","Deleted"]
["pld4b","INPUT","s4b_5[7..0]",5,"SpareSigs","z","z","z","Deleted"]
["pld5","INPUT","s4b_5[7..0]","4b","SpareSigs","z","z","z","Deleted"]
["pld5","INPUT","s5_6[7..0]",6,"SpareSigs","z","z","z","Deleted"]
["pld6","INPUT","s5_6[7..0]",5,"SpareSigs","z","z","z","Deleted"]
["pld6","INPUT","s6_7[7..0]",7,"SpareSigs","z","z","z","Deleted"]
["pld7","INPUT","s6_7[7..0]",6,"SpareSigs","z","z","z","Deleted"]
["pld7","INPUT","s7_8[7..0]",8,"SpareSigs","z","z","z","Deleted"]
["pld8","INPUT","s7_8[7..0]",7,"SpareSigs","z","z","z","Deleted"]
["pld8","INPUT","s8_9[7..0]",9,"SpareSigs","z","z","z","Deleted"]
["pld9","INPUT","s8_9[7..0]",8,"SpareSigs","z","z","z","Deleted"]
["pld2","INPUT","SAClkON_out",3,"Intra-PLD","z","z","z","Deleted"]
["pld3","OUTPUT","SAClkON_out",2,"Intra-PLD","z","z","z","Deleted"]
["pld1","INPUT","sgbA[7..0]","2,3,4a,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld2","INPUT","sgbA[7..0]","1,3,4a,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld3","INPUT","sgbA[7..0]","1,2,4a,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4a","INPUT","sgbA[7..0]","1,2,3,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4b","INPUT","sgbA[7..0]","1,2,3,4a,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld5","INPUT","sgbA[7..0]","1,2,3,4a,4b,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld6","INPUT","sgbA[7..0]","1,2,3,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld7","INPUT","sgbA[7..0]","1,2,3,4a,4b,5,6,8,9","SpareBus","z","z","z","Deleted"]
["pld8","INPUT","sgbA[7..0]","1,2,3,4a,4b,5,6,7,9","SpareBus","z","z","z","Deleted"]
["pld9","INPUT","sgbA[7..0]","1,2,3,4a,4b,5,6,7,8","SpareBus","z","z","z","Deleted"]
["pld1","INPUT","sgbB[7..0]","2,3,4a,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld2","INPUT","sgbB[7..0]","1,3,4a,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld3","INPUT","sgbB[7..0]","1,2,4a,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4a","INPUT","sgbB[7..0]","1,2,3,4b,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4b","INPUT","sgbB[7..0]","1,2,3,4a,5,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld5","INPUT","sgbB[7..0]","1,2,3,4a,4b,6,7,8,9","SpareBus","z","z","z","Deleted"]
["pld6","INPUT","sgbB[7..0]","1,2,3,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld7","INPUT","sgbB[7..0]","1,2,3,4a,4b,5,6,8,9","SpareBus","z","z","z","Deleted"]
["pld8","INPUT","sgbB[7..0]","1,2,3,4a,4b,5,6,7,9","SpareBus","z","z","z","Deleted"]
["pld9","INPUT","sgbB[7..0]","1,2,3,4a,4b,5,6,7,8","SpareBus","z","z","z","Deleted"]
["pld1","INPUT","sgbC[7..0]","2,3,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld2","INPUT","sgbC[7..0]","1,3,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld3","INPUT","sgbC[7..0]","1,2,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4a","INPUT","sgbC[7..0]","1,2,3,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4b","INPUT","sgbC[7..0]","1,2,3,4a,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld5","INPUT","sgbC[7..0]","1,2,3,4a,4b,7,8,9","SpareBus","z","z","z","Deleted"]
["pld7","INPUT","sgbC[7..0]","1,2,3,4a,4b,5,8,9","SpareBus","z","z","z","Deleted"]
["pld8","INPUT","sgbC[7..0]","1,2,3,4a,4b,5,7,9","SpareBus","z","z","z","Deleted"]
["pld9","INPUT","sgbC[7..0]","1,2,3,4a,4b,5,7,8","SpareBus","z","z","z","Deleted"]
["pld1","INPUT","sgbD[4..2]","2,3,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld2","INPUT","sgbD[4..2]","1,3,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld3","INPUT","sgbD[4..2]","1,2,4a,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4a","INPUT","sgbD[4..2]","1,2,3,4b,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld4b","INPUT","sgbD[4..2]","1,2,3,4a,5,7,8,9","SpareBus","z","z","z","Deleted"]
["pld5","INPUT","sgbD[4..2]","1,2,3,4a,4b,7,8,9","SpareBus","z","z","z","Deleted"]
["pld7","INPUT","sgbD[4..2]","1,2,3,4a,4b,5,8,9","SpareBus","z","z","z","Deleted"]
["pld8","INPUT","sgbD[4..2]","1,2,3,4a,4b,5,7,9","SpareBus","z","z","z","Deleted"]
["pld9","INPUT","sgbD[4..2]","1,2,3,4a,4b,5,7,8","SpareBus","z","z","z","Deleted"]
["pld2","INPUT","TTCClkON_out",3,"Intra-PLD","z","z","z","Deleted"]
["pld3","OUTPUT","TTCClkON_out",2,"Intra-PLD","z","z","z","Deleted"]
["pld7","OUTPUT","XSeqClk1","tp","Test Point","z","z","z","Deleted"]
["pld7","OUTPUT","XSeqClk2","tp","Test Point","z","z","z","Deleted"]
["pld7","OUTPUT","XSeqTRIG","tp","Test Point","z","z","z","Deleted"]

{"sheet":"Sheet2","index":1,"n_rows":0,"n_cols":0,"rows_kept":0,"flags":["formulas_cached_only"]}

{"sheet":"Sheet3","index":2,"n_rows":0,"n_cols":0,"rows_kept":0,"flags":["formulas_cached_only"]}