{"text_format":"5","workbook":"xls","n_sheets":2,"sheets":["pld_io","Legend"],"props":{"creator":"Matthew Warren","last_modified_by":"mp","company":"HEP UCL"},"not_rendered":{"images":6,"macros":1,"external_links":1,"defined_names":2},"read":"whole","wrapped":"gz","date_system":"1900","formulas":"cached_only"}

{"sheet":"pld_io","index":0,"n_rows":577,"n_cols":22,"rows_kept":577,"merged":[[1,7,1,8]],"headers":{"header":["","","Page of"],"footer":["","Prepared by Matthew Warren","Page of"]},"flags":["formulas_cached_only"]}
["TIM SIGNALS:",null,null,"Old - TIM2",null,"New",{"$nulls":3},"I/O","FPGA2 (329)","FPGA1 (289)",{"$nulls":4},"FPGA Signals"]
["PLD","IO","NAME","Old Source/Destination",null,"Int or Ext","FPGA","New Source/ Destination",null,"No. I/O Pins","273 82%","178 60%","LVTTL Solution?",null,"Comment/ Part Suggestion","Last Modified","FPGA Name","Range","vhdl instantiation"]
["new",null,null,"-","-","e","f1","cp1","PROM1",1,null,1,3,"3.3v part",null,"2003-02-26","prom1_DI_i","-","prom1_DI_i : in  std_logic;",null,null,"sds"]
["new",null,null,"-","-","e","f1","cp2","PROM2",1,null,1,3,"3.3v part",null,"2003-02-26","xjtag_EN_o","-","xjtag_EN_o : out std_logic;"]
["new",null,null,"-","-","e","f1","cp2","PROM2",1,null,1,3,"3.3v part",null,"2003-02-26","xjtag_XCK_o","-","xjtag_XCK_o : out std_logic;"]
["new",null,null,"-","-","e","f1","cp2","PROM2",1,null,1,3,"3.3v part",null,"2003-02-26","xjtag_XDI_i","-","xjtag_XDI_i : in  std_logic;"]
["new",null,null,"-","-","e","f1","cp2","PROM2",1,null,1,3,"3.3v part",null,"2003-02-26","xjtag_XDO_o","-","xjtag_XDO_o : out std_logic;"]
["new",null,null,"-","-","e","f1","cp2","PROM2",1,null,1,3,"3.3v part",null,"2003-02-26","xjtag_XMS_o","-","xjtag_XMS_o : out std_logic;"]
["new",null,null,"-","-","e","f1","dh","Debug Bus Header",16,null,16,"n","Entirely New",null,"2003-02-26","debug_Bus_o","(15 downto 0)","debug_Bus_o : out std_logic_vector(15 downto 0);"]
["new",null,null,"-","-","e","f1","dms","Debug Mode Switch",4,null,4,"n","Entirely New",null,"2003-02-26","debug_Mode_i","(3 downto 0)","debug_Mode_i : in  std_logic_vector(3 downto 0);"]
["new",null,null,"-","-","e","f1","f2","FPGA2",1,1,1,"n","Entirely New",null,"2003-02-26","BaseAddrOK_o","-","BaseAddrOK_o : out std_logic;"]
["new",null,null,"-","-","e","f1","f2","FPGA2",16,16,16,"n","Entirely New",null,"2003-02-26","SpareBus_o","(15 downto 0)","SpareBus_o : out std_logic_vector(15 downto 0);"]
["new",null,null,"-","-","e","f1","por","Power-On Reset",1,null,1,"n","Entirely New",null,"2003-02-26","POreset_i","-","POreset_i : in  std_logic;"]
["new",null,null,"-","-","e","f1","sf","Special FPGA",1,null,1,3,"3.3v part",null,"2003-02-26","f1DI_i","-","f1DI_i : in  std_logic;"]
["new",null,null,"-","-","e","f1","sf","Special FPGA",1,null,1,3,"3.3v part",null,"2003-02-26","f1INIT_nio","-","f1INIT_nio : inout  std_logic;"]
["new",null,null,"-","-","e","f1","ti","TIM ID",8,null,8,3,"3.3v part",null,"2003-02-26","TIM_ID_i","(7 downto 0)","TIM_ID_i : in  std_logic_vector(7 downto 0);"]
["new",null,null,"-","-","e","f1","usf","Unused Special FPGA",0,null,0,3,"3.3v part",null,"2003-02-26","f1D_io","(7 downto 1)","f1D_io : inout  std_logic_vector(7 downto 1);"]
["new",null,null,"-","-","e","f1","usf","Unused Special FPGA",0,null,0,3,"3.3v part",null,"2003-02-26","f1DOUT_o","-","f1DOUT_o : out std_logic;"]
["new",null,null,"-","-","e","f1","usf","Unused Special FPGA",0,null,0,3,"3.3v part",null,"2003-02-26","f1WRITE_ni","-","f1WRITE_ni : in  std_logic;"]
["new",null,null,"-","-","e","f1","v","VME",31,null,31,"cb","Change Buffer",null,"2003-02-26","vme_ab_i","(31 downto 1)","vme_ab_i : in  std_logic_vector(31 downto 1);"]
["new",null,null,"-","-","e","f1","v","VME",32,null,32,"cb","Change Buffer",null,"2003-02-26","vme_db_io","(31 downto 0)","vme_db_io : inout  std_logic_vector(31 downto 0);"]
["new",null,null,"-","-","e","f2","cc","Clock Control",1,1,null,"t","Translator req'd",null,"2003-02-26","enIntClk_o","-","enIntClk_o : out std_logic;"]
["new",null,null,"-","-","e","f2","cc","Clock Control",1,1,null,"t","Translator req'd",null,"2003-02-26","enSAClk_o","-","enSAClk_o : out std_logic;"]
["new",null,null,"-","-","e","f2","cc","Clock Control",1,1,null,"t","Translator req'd",null,"2003-02-26","IntClkOff_i","-","IntClkOff_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","cc","Clock Control",1,1,null,"t","Translator req'd",null,"2003-02-26","SAClkOff_i","-","SAClkOff_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","cc","Clock Control",1,1,null,"t","Translator req'd",null,"2003-02-26","TTCClkOff_i","-","TTCClkOff_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","cp2","PROM2",1,1,null,3,"3.3v part",null,"2003-02-26","prom2_DI_i","-","prom2_DI_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","dh","Debug Bus Header",16,16,null,"n","Entirely New",null,"2003-02-26","debug_Bus_o","(15 downto 0)","debug_Bus_o : out std_logic_vector(15 downto 0);"]
["new",null,null,"-","-","e","f2","dms","Debug Mode Switch",4,4,null,"n","Entirely New",null,"2003-02-26","debug_Mode_i","(3 downto 0)","debug_Mode_i : in  std_logic_vector(3 downto 0);"]
["new",null,null,"-","-","e","f2","f2","FPGA2",1,1,null,"n","Entirely New",null,"2003-02-26","BaseAddrOK_i","-","BaseAddrOK_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","f2","FPGA2",16,16,null,"n","Entirely New",null,"2003-02-26","SpareBus_i","(15 downto 0)","SpareBus_i : in  std_logic_vector(15 downto 0);"]
["new",null,null,"-","-","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extClkOff_i","-","extClkOff_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","sf","Special FPGA",1,1,null,3,"3.3v part",null,"2003-02-26","f2DI_i","-","f2DI_i : in  std_logic;"]
["new",null,null,"-","-","e","f2","sf","Special FPGA",1,1,null,3,"3.3v part",null,"2003-02-26","f2INIT_nio","-","f2INIT_nio : inout  std_logic;"]
["new",null,null,"-","-","e","f2","ti","TIM ID",8,8,null,3,"3.3v part",null,"2003-02-26","TIM_ID_i","(7 downto 0)","TIM_ID_i : in  std_logic_vector(7 downto 0);"]
["new",null,null,"-","-","e","f2","usf","Unused Special FPGA",0,0,null,3,"3.3v part",null,"2003-02-26","f2D_io","(7 downto 1)","f2D_io : inout  std_logic_vector(7 downto 1);"]
["new",null,null,"-","-","e","f2","usf","Unused Special FPGA",0,0,null,3,"3.3v part",null,"2003-02-26","f2DOUT_o","-","f2DOUT_o : out std_logic;"]
["new",null,null,"-","-","e","f2","usf","Unused Special FPGA",0,0,null,3,"3.3v part",null,"2003-02-26","f2WRITE_ni","-","f2WRITE_ni : in  std_logic;"]
["pld1","OUTPUT","nGAoutEn","b","Back-Plane IO","e","f1","bp","BP Interfacing",1,null,1,"t","Translator req'd",null,"2003-02-26","GAoutEn_no","-","GAoutEn_no : out std_logic;"]
["pld1","OUTPUT","bRead","v","VME","e","f1","f2","FPGA2",1,1,1,"i","local - do nothing",null,"2003-02-26","vmeRD_o","-","vmeRD_o : out std_logic;"]
["pld1","OUTPUT","bWrite","v","VME","e","f1","f2","FPGA2",1,1,1,"i","local - do nothing",null,"2003-02-26","vmeWR_o","-","vmeWR_o : out std_logic;"]
["pld1","INPUT","B_select","j","Jumpers & DIPs","e","f1","j","Jumpers & DIPs",1,null,1,"p","Power change only",null,"2003-02-26","B_select_i","-","B_select_i : in  std_logic;"]
["pld1","INPUT","BaseAddr_Select","j","Jumpers & DIPs","e","f1","j","Jumpers & DIPs",1,null,1,"p","Power change only",null,"2003-02-26","BaseAddr_Select_i","-","BaseAddr_Select_i : in  std_logic;"]
["pld1","INPUT","base_addr[31..16]","ba","Base Addr. Switches","e","f1","v","VME",16,null,16,"p","Power change only",null,"2003-02-26","base_addr_i","(31 downto 16)","base_addr_i : in  std_logic_vector(31 downto 16);"]
["pld1","INPUT","dl1","dv","VME Delay Unit","e","f1","v","VME",1,null,1,"cp","Change Part","DS1110LE-100","2003-02-26","DL1_i","-","DL1_i : in  std_logic;"]
["pld1","INPUT","dl2","dv","VME Delay Unit","e","f1","v","VME",1,null,1,"cp","Change Part","DS1110LE-100","2003-02-26","DL2_i","-","DL2_i : in  std_logic;"]
["pld1","INPUT","dl3","dv","VME Delay Unit","e","f1","v","VME",1,null,1,"cp","Change Part","DS1110LE-100","2003-02-26","DL3_i","-","DL3_i : in  std_logic;"]
["pld1","INPUT","amb[5..0]","v","VME","e","f1","v","VME",6,null,6,"cb","Change Buffer",null,"2003-02-26","vme_AMb_i","(5 downto 0)","vme_AMb_i : in  std_logic_vector(5 downto 0);"]
["pld1","INPUT","nASb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_ASb_ni","-","vme_ASb_ni : in  std_logic;"]
["pld1","INPUT","nBErrb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_BErrb_ni","-","vme_BErrb_ni : in  std_logic;"]
["pld1","INPUT","nDS0b","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_DS0b_ni","-","vme_DS0b_ni : in  std_logic;"]
["pld1","INPUT","nDS1b","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_DS1b_ni","-","vme_DS1b_ni : in  std_logic;"]
["pld1","INPUT","nGAb[4..0]","v","VME","e","f1","v","VME",5,null,5,"cb","Change Buffer",null,"2003-02-26","vme_GAb_ni","(4 downto 0)","vme_GAb_ni : in  std_logic_vector(4 downto 0);"]
["pld1","INPUT","nGAbp","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_GAbp_ni","-","vme_GAbp_ni : in  std_logic;"]
["pld1","INPUT","nIAckb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_IAckb_ni","-","vme_IAckb_ni : in  std_logic;"]
["pld1","INPUT","nIAckinb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_IAckInb_ni","-","vme_IAckInb_ni : in  std_logic;"]
["pld1","INPUT","nLWordb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_LWordb_ni","-","vme_LWordb_ni : in  std_logic;"]
["pld1","INPUT","nWriteb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_Writeb_ni","-","vme_Writeb_ni : in  std_logic;"]
["pld1","OUTPUT","dl0","dv","VME Delay Unit","e","f1","v","VME",1,null,1,"cp","Change Part","DS1110LE-100","2003-02-26","DL0_o","-","DL0_o : out std_logic;"]
["pld1","OUTPUT","nErrorLED","fl","Front-Panel LEDs","e","f1","v","VME",1,null,1,"c3","Use 3.3v version",null,"2003-02-26","ErrorLED_no","-","ErrorLED_no : out std_logic;"]
["pld1","OUTPUT","Ack","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_Ack_o","-","vme_Ack_o : out std_logic;"]
["pld1","OUTPUT","nIAckoutb","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_IAckOutb_no","-","vme_IAckOutb_no : out std_logic;"]
["pld1","OUTPUT","nIrqb[7..1]","v","VME","e","f1","v","VME",7,null,7,"cb","Change Buffer",null,"2003-02-26","vme_IRQb_no","(7 downto 1)","vme_IRQb_no : out std_logic_vector(7 downto 1);"]
["pld1","OUTPUT","nLE1","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_LE1_no","-","vme_LE1_no : out std_logic;"]
["pld1","OUTPUT","nLE2","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_LE2_no","-","vme_LE2_no : out std_logic;"]
["pld1","OUTPUT","nOEin","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_OEin_no","-","vme_OEin_no : out std_logic;"]
["pld1","OUTPUT","nOEout","v","VME","e","f1","v","VME",1,null,1,"cb","Change Buffer",null,"2003-02-26","vme_OEout_no","-","vme_OEout_no : out std_logic;"]
["pld1","OUTPUT","bRead","v","VME","e","f2","f2","FPGA2",1,1,null,"i","local - do nothing",null,"2003-02-26","vmeRD_i","-","vmeRD_i : in  std_logic;"]
["pld1","OUTPUT","bWrite","v","VME","e","f2","f2","FPGA2",1,1,null,"i","local - do nothing",null,"2003-02-26","vmeWR_i","-","vmeWR_i : in  std_logic;"]
["pld1","OUTPUT","nStop_Clk","cc","Clock Control","e","f2","w","Trigger Window",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","trw_Stop_Clk_no","-","trw_Stop_Clk_no : out std_logic;"]
["pld1","OUTPUT","Stop_Clk","cc","Clock Control","e","f2","w","Trigger Window",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","trw_Stop_Clk_o","-","trw_Stop_Clk_o : out std_logic;"]
["pld2","INPUT","sReset","fi","Front Panel In","e","f1","fi","Front Panel In",1,null,1,"c3","Use 3.3v version",null,"2003-02-26","extReset_sw_i","-","extReset_sw_i : in  std_logic;"]
["pld2","OUTPUT","nOA_reset",2,"pld 2","e","f1","rst","Resets",1,null,1,"cb","Change Buffer",null,"2003-02-25","OA_reset_no","-","OA_reset_no : out std_logic;"]
["pld2","OUTPUT","TIM_OK_out","b","Back-Plane IO","e","f2","b","Back-Plane IO",1,1,null,"cb","Change Buffer",null,"2003-02-26","bp_TIM_OK_o","-","bp_TIM_OK_o : out std_logic;"]
["pld2","OUTPUT","CT[5..0]","cc","Clock Control","e","f2","cc","Clock Control",6,6,null,"nc","NO CHANGE!",null,"2003-02-26","CT_o","(5 downto 0)","CT_o : out std_logic_vector(5 downto 0);"]
["pld2","OUTPUT","nSA_CLK_MODE","cc","Clock Control","e","f2","cc","Clock Control",1,1,{"$nulls":4},"2003-02-25","nSA_CLK_MODE_o","-","nSA_CLK_MODE_o : out std_logic;"]
["pld2","INPUT","extInBCREcl","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extBCRin_ecl_i","-","extBCRin_ecl_i : in  std_logic;"]
["pld2","INPUT","extInBCRNim","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd","Use external OR?","2003-02-26","extBCRin_nim_i","-","extBCRin_nim_i : in  std_logic;"]
["pld2","INPUT","extInCALEcl","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extCALin_ecl_i","-","extCALin_ecl_i : in  std_logic;"]
["pld2","INPUT","extInCALNim","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd","Use external OR?","2003-02-26","extCALin_nim_i","-","extCALin_nim_i : in  std_logic;"]
["pld2","INPUT","extInECREcl","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extECRin_ecl_i","-","extECRin_ecl_i : in  std_logic;"]
["pld2","INPUT","extInECRNim","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd","Use external OR?","2003-02-26","extECRin_nim_i","-","extECRin_nim_i : in  std_logic;"]
["pld2","INPUT","extInFEREcl","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extFERin_ecl_i","-","extFERin_ecl_i : in  std_logic;"]
["pld2","INPUT","extInFERNim","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd","Use external OR?","2003-02-26","extFERin_nim_i","-","extFERin_nim_i : in  std_logic;"]
["pld2","INPUT","extInSpareEcl","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extSPRin_ecl_i","-","extSPRin_ecl_i : in  std_logic;"]
["pld2","INPUT","extInSpareNim","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd","Use external OR?","2003-02-26","extSPRin_nim_i","-","extSPRin_nim_i : in  std_logic;"]
["pld2","INPUT","test_sw","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","extTRIG_sw_i","-","extTRIG_sw_i : in  std_logic;"]
["pld2","INPUT","extInTRIGEcl","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extTRIGin_ecl_i","-","extTRIGin_ecl_i : in  std_logic;"]
["pld2","INPUT","extInTRIGNim","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd","Use external OR?","2003-02-26","extTRIGin_nim_i","-","extTRIGin_nim_i : in  std_logic;"]
["pld2","OUTPUT","SAMode","fl","Front-Panel LEDs","e","f2","fl","Front-Panel LEDs",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","led_SAMode_o","-","led_SAMode_o : out std_logic;"]
["pld2","OUTPUT","outTRIG","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extETRIGout_o","-","extETRIGout_o : out std_logic;"]
["pld2","OUTPUT","MExtBusyOut","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,{"$nulls":4},"2003-02-25","extMBUSYout_o","-","extMBUSYout_o : out std_logic;"]
["pld2","INPUT","intInECR","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",1,1,null,"t","Translator req'd",null,"2003-02-26","intECRin_i","-","intECRin_i : in  std_logic;"]
["pld2","INPUT","intInFER","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",1,1,null,"t","Translator req'd",null,"2003-02-26","intFERin_i","-","intFERin_i : in  std_logic;"]
["pld2","INPUT","intInTRIG","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",1,1,null,"t","Translator req'd",null,"2003-02-26","intTRIGin_i","-","intTRIGin_i : in  std_logic;"]
["pld2","OUTPUT","enIntFER","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",1,1,null,"t","Translator req'd",null,"2003-02-26","enIntFER_o","-","enIntFER_o : out std_logic;"]
["pld2","OUTPUT","enIntTRIG","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",1,1,null,"t","Translator req'd",null,"2003-02-26","enIntTRIG_o","-","enIntTRIG_o : out std_logic;"]
["pld2","INPUT","TRIG_win","w","Trigger Window","e","f2","w","Trigger Window",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","trw_TRIGin_i","-","trw_TRIGin_i : in  std_logic;"]
["pld2","OUTPUT","enWindow","w","Trigger Window","e","f2","w","Trigger Window",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","trw_enWindow_o","-","trw_enWindow_o : out std_logic;"]
["pld3","INPUT","laser_intlck_state","b","Back-Plane IO","e","f2","b","Back-Plane IO",1,1,null,"cb","Change Buffer",null,"2003-02-26","bp_laser_intlck_state_i","-","bp_laser_intlck_state_i : in  std_logic;"]
["pld3","INPUT","SAClkOn","cc","Clock Control","e","f2","cc","Clock Control",1,1,{"$nulls":4},"2003-02-25","SAClkOn_i","-","SAClkOn_i : in  std_logic;"]
["pld3","INPUT","TTCClkOn","cc","Clock Control","e","f2","cc","Clock Control",1,1,{"$nulls":4},"2003-02-25","TTCClkOn_i","-","TTCClkOn_i : in  std_logic;"]
["pld3","OUTPUT","r[5..1]","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",5,5,null,"t","Translator req'd",null,"2003-02-26","R_o","(5 downto 1)","R_o : out std_logic_vector(5 downto 1);"]
["pld3","OUTPUT","s[5..1]","is","Internal Trig, FER, ECR","e","f2","is","Internal Trig, FER, ECR",5,5,null,"t","Translator req'd",null,"2003-02-26","S_o","(5 downto 1)","S_o : out std_logic_vector(5 downto 1);"]
["pld3","OUTPUT","wd[5..0]","w","Trigger Window","e","f2","w","Trigger Window",6,6,null,"nc","NO CHANGE!",null,"2003-02-26","trw_WD_o","(5 downto 0)","trw_WD_o : out std_logic_vector(5 downto 0);"]
["pld3","OUTPUT","ws[5..0]","w","Trigger Window","e","f2","w","Trigger Window",6,6,null,"nc","NO CHANGE!",null,"2003-02-26","trw_WS_o","(5 downto 0)","trw_WS_o : out std_logic_vector(5 downto 0);"]
["pld6","OUTPUT","nTTCout[7..0]","b","Back-Plane IO","e","f2","b","Back-Plane IO",8,8,null,"t","Translator req'd",null,"2003-02-26","bp_TTCbus_no","(7 downto 0)","bp_TTCbus_no : out std_logic_vector(7 downto 0);"]
["pld8","INPUT","nRodBusyb[21..5]","b","Back-Plane IO","e","f2","b","Back-Plane IO",16,16,null,"nc","NO CHANGE!",null,"2003-02-26","bp_RodBusyb_ni","(21 downto 5)","bp_RodBusyb_ni : in  std_logic_vector(21 downto 5);"]
["pld8","INPUT","extRodBusyIn","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extRodBUSYin_i","-","extRodBUSYin_i : in  std_logic;"]
["pld9","OUTPUT","TTC_ready_in","fl","Front-Panel LEDs","e","f2","fl","Front-Panel LEDs",1,1,null,"p","Power change only",null,"2003-02-25","led_TTC_OK_o","-","led_TTC_OK_o : out std_logic;"]
["pld9","BIPUT","SCL","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_SCL_io","-","trx_SCL_io : inout  std_logic;"]
["pld9","BIPUT","SDA","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_SDA_io","-","trx_SDA_io : inout  std_logic;"]
["pld9","INPUT","BCnt[11..0]","t","TTCrx","e","f2","t","TTCrx",12,12,null,"p","Power change only",null,"2003-02-26","trx_BCnt_i","(11 downto 0)","trx_BCnt_i : in  std_logic_vector(11 downto 0);"]
["pld9","INPUT","BCntStr","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_BCntStr_i","-","trx_BCntStr_i : in  std_logic;"]
["pld9","INPUT","Brcst[7..2]","t","TTCrx","e","f2","t","TTCrx",6,6,null,"p","Power change only",null,"2003-02-26","trx_Brcst_i","(7 downto 2)","trx_Brcst_i : in  std_logic_vector(7 downto 2);"]
["pld9","INPUT","BrcstStr1","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_BrcstStr1_i","-","trx_BrcstStr1_i : in  std_logic;"]
["pld9","INPUT","BrcstStr2","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_BrcstStr2_i","-","trx_BrcstStr2_i : in  std_logic;"]
["pld9","INPUT","DbErrStr","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_DbErrStr_i","-","trx_DbErrStr_i : in  std_logic;"]
["pld9","INPUT","Dout[7..0]","t","TTCrx","e","f2","t","TTCrx",8,8,null,"p","Power change only",null,"2003-02-26","trx_Dout_i","(7 downto 0)","trx_Dout_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","DoutStr","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_DoutStr_i","-","trx_DoutStr_i : in  std_logic;"]
["pld9","INPUT","DQ[3..0]","t","TTCrx","e","f2","t","TTCrx",4,4,null,"p","Power change only",null,"2003-02-26","trx_DQ_i","(3 downto 0)","trx_DQ_i : in  std_logic_vector(3 downto 0);"]
["pld9","INPUT","EvCntHStr","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_EvCntHStr_i","-","trx_EvCntHStr_i : in  std_logic;"]
["pld9","INPUT","EvCntLStr","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_EvCntLStr_i","-","trx_EvCntLStr_i : in  std_logic;"]
["pld9","INPUT","SinErrStr","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_SinErrStr_i","-","trx_SinErrStr_i : in  std_logic;"]
["pld9","INPUT","SubAddr[7..0]","t","TTCrx","e","f2","t","TTCrx",8,8,null,"p","Power change only",null,"2003-02-26","trx_SubAddr_i","(7 downto 0)","trx_SubAddr_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","TTCReady","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_TTCReady_i","-","trx_TTCReady_i : in  std_logic;"]
["pld9","OUTPUT","Resetb","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-26","trx_Resetb_o","-","trx_Resetb_o : out std_logic;"]
["plds","INPUT","nOA_rst","rst","Resets","e","f2","f2","FPGA2",1,1,null,"cb","Change Buffer",null,"2003-02-25","OA_rst_ni","-","OA_rst_ni : in  std_logic;",null,null,"EvCntRes"]
["plds","INPUT","eclExtBusy","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extBUSYin_ecl_i","-","extBUSYin_ecl_i : in  std_logic;"]
["plds","INPUT","NimExtBusy","fi","Front Panel In","e","f2","fi","Front Panel In",1,1,null,"t","Translator req'd",null,"2003-02-26","extBUSYin_nim_i","-","extBUSYin_nim_i : in  std_logic;"]
["plds","OUTPUT","RunMode","fl","Front-Panel LEDs","e","f2","fl","Front-Panel LEDs",1,1,null,"c3","Use 3.3v version",null,"2003-02-26","led_RunMode_o","-","led_RunMode_o : out std_logic;"]
["plds","OUTPUT","eclBCR","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extBCRout_o","-","extBCRout_o : out std_logic;"]
["plds","OUTPUT","BusyOut","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extBUSYout_o","-","extBUSYout_o : out std_logic;"]
["plds","OUTPUT","eclCAL","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extCALout_o","-","extCALout_o : out std_logic;"]
["plds","OUTPUT","eclECR","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extECRout_o","-","extECRout_o : out std_logic;"]
["plds","OUTPUT","eclFER","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extFERout_o","-","extFERout_o : out std_logic;"]
["plds","OUTPUT","eclID","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extIDSout_o","-","extIDSout_o : out std_logic;"]
["plds","OUTPUT","eclL1A","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extL1Aout_o","-","extL1Aout_o : out std_logic;"]
["plds","OUTPUT","eclSpare","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extSPRout_o","-","extSPRout_o : out std_logic;"]
["plds","OUTPUT","eclTT","fo","Front Panel Out","e","f2","fo","Front Panel Out",1,1,null,"t","Translator req'd",null,"2003-02-26","extTTSout_o","-","extTTSout_o : out std_logic;"]
["plds","OUTPUT","rod_crate_BusyOut","fl","Front-Panel LEDs","e","f2","fo","Front Panel Out",1,1,null,"c3","Use 3.3v version",null,"2003-02-27","extRodCrateBUSYout_o","-","extRodCrateBUSYout_o : out std_logic;"]
["plds","INPUT","BCRin","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-25","trx_BCntRes_i","-","trx_BCntRes_i : in  std_logic;"]
["plds","INPUT","ECRin","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-25","trx_EvCntRes_i","-","trx_EvCntRes_i : in  std_logic;"]
["plds","INPUT","L1Ain","t","TTCrx","e","f2","t","TTCrx",1,1,null,"p","Power change only",null,"2003-02-25","trx_L1Accept_i","-","trx_L1Accept_i : in  std_logic;",null,null,"L1Accept"]
["plds","BIPUT","db[31..0]","v","VME","e","f2","v","VME",32,32,null,"cb","Change Buffer",null,"2003-02-26","vme_db_io","(31 downto 0)","vme_db_io : inout  std_logic_vector(31 downto 0);"]
["plds","INPUT","ab[15..1]","v","VME","e","f2","v","VME",15,15,null,"cb","Change Buffer",null,"2003-02-26","vme_ab_i","(15 downto 1)","vme_ab_i : in  std_logic_vector(15 downto 1);",null,null,"BCntRes"]
["pld1","INPUT","enExtRodBusy","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_i","-","enExtRodBusy_i : in  std_logic;"]
["pld1","OUTPUT","RAMselect",7,"pld 7","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","RAMselect_o","-","RAMselect_o : out std_logic;"]
["pld1","OUTPUT","Reg00",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg00_o","-","Reg00_o : out std_logic;"]
["pld1","OUTPUT","Reg02",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg02_o","-","Reg02_o : out std_logic;"]
["pld1","OUTPUT","Reg04",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg04_o","-","Reg04_o : out std_logic;"]
["pld1","OUTPUT","Reg06",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg06_o","-","Reg06_o : out std_logic;"]
["pld1","OUTPUT","Reg08",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg08_o","-","Reg08_o : out std_logic;"]
["pld1","OUTPUT","Reg0A",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg0A_o","-","Reg0A_o : out std_logic;"]
["pld1","OUTPUT","Reg0C",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg0C_o","-","Reg0C_o : out std_logic;"]
["pld1","OUTPUT","Reg0E",5,"pld 5","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg0E_o","-","Reg0E_o : out std_logic;"]
["pld1","OUTPUT","Reg10","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg10_o","-","Reg10_o : out std_logic;"]
["pld1","OUTPUT","Reg12","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg12_o","-","Reg12_o : out std_logic;"]
["pld1","OUTPUT","Reg14","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg14_o","-","Reg14_o : out std_logic;"]
["pld1","OUTPUT","Reg16","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg16_o","-","Reg16_o : out std_logic;"]
["pld1","OUTPUT","Reg18",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg18_o","-","Reg18_o : out std_logic;"]
["pld1","OUTPUT","Reg1A",7,"pld 7","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg1A_o","-","Reg1A_o : out std_logic;"]
["pld1","OUTPUT","Reg1C",7,"pld 7","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg1C_o","-","Reg1C_o : out std_logic;"]
["pld1","OUTPUT","Reg1E",8,"pld 8","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg1E_o","-","Reg1E_o : out std_logic;"]
["pld1","OUTPUT","Reg20",8,"pld 8","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg20_o","-","Reg20_o : out std_logic;"]
["pld1","OUTPUT","Reg22",8,"pld 8","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg22_o","-","Reg22_o : out std_logic;"]
["pld1","OUTPUT","Reg24",8,"pld 8","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg24_o","-","Reg24_o : out std_logic;"]
["pld1","OUTPUT","Reg26",9,"pld 9","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg26_o","-","Reg26_o : out std_logic;"]
["pld1","OUTPUT","Reg28",9,"pld 9","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg28_o","-","Reg28_o : out std_logic;"]
["pld1","OUTPUT","Reg2A","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg2A_o","-","Reg2A_o : out std_logic;"]
["pld1","OUTPUT","Reg2C",9,"pld 9","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg2C_o","-","Reg2C_o : out std_logic;"]
["pld1","OUTPUT","Reg2E",9,"pld 9","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg2E_o","-","Reg2E_o : out std_logic;"]
["pld1","OUTPUT","Reg30",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg30_o","-","Reg30_o : out std_logic;"]
["pld1","OUTPUT","Reg32",5,"pld 5","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg32_o","-","Reg32_o : out std_logic;"]
["pld1","OUTPUT","Reg34",5,"pld 5","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg34_o","-","Reg34_o : out std_logic;"]
["pld1","INPUT","ab[31..1]","v","VME","i","i","v","VME",{"$nulls":6},"2003-01-01","ab_i","(31 downto 1)","ab_i : in  std_logic_vector(31 downto 1);"]
["pld2","BIPUT","db[15..0]","All-1","pld All-1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","db_o","(15 downto 0)","db_o : out std_logic_vector(15 downto 0);"]
["pld2","INPUT","bReadb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bReadb_i","-","bReadb_i : in  std_logic;"]
["pld2","INPUT","Burst_Ready",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Burst_Ready_i","-","Burst_Ready_i : in  std_logic;"]
["pld2","INPUT","bWriteb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bWriteb_i","-","bWriteb_i : in  std_logic;"]
["pld2","INPUT","clk2","cc","Clock Control","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","clk2_i","-","clk2_i : in  std_logic;"]
["pld2","INPUT","clk2b","cc","Clock Control","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","clk2b_i","-","clk2b_i : in  std_logic;"]
["pld2","INPUT","Disable_TRIG",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Disable_TRIG_i","-","Disable_TRIG_i : in  std_logic;"]
["pld2","INPUT","enCALBurst",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enCALBurst_i","-","enCALBurst_i : in  std_logic;"]
["pld2","INPUT","enExtRodBusy_in",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_in_i","-","enExtRodBusy_in_i : in  std_logic;"]
["pld2","INPUT","enRodBusy",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enRodBusy_i","-","enRodBusy_i : in  std_logic;"]
["pld2","INPUT","intInBCR",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","intInBCR_i","-","intInBCR_i : in  std_logic;"]
["pld2","INPUT","intInRan",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","intInRan_i","-","intInRan_i : in  std_logic;"]
["pld2","INPUT","Reg00",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg00_i","-","Reg00_i : in  std_logic;"]
["pld2","INPUT","Reg02",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg02_i","-","Reg02_i : in  std_logic;"]
["pld2","INPUT","Reg0A",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg0A_i","-","Reg0A_i : in  std_logic;"]
["pld2","OUTPUT","enExtRodBusy","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_o","-","enExtRodBusy_o : out std_logic;"]
["pld2","OUTPUT","enRandom",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enRandom_o","-","enRandom_o : out std_logic;"]
["pld2","OUTPUT","intBusy",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","intBusy_o","-","intBusy_o : out std_logic;"]
["pld2","OUTPUT","intTRIG",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","intTRIG_o","-","intTRIG_o : out std_logic;"]
["pld2","OUTPUT","MExtBusyOut",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","MExtBusyOut_o","-","MExtBusyOut_o : out std_logic;"]
["pld2","OUTPUT","nOA_busy","tp","Test Point","I","I","I","TIM Internal",{"$nulls":6},"2003-01-01","nOA_busy_o","-","nOA_busy_o : out std_logic;"]
["pld2","OUTPUT","outTRIG1","tp","Test Point","i","i","I","TIM Internal",{"$nulls":6},"2003-01-01","outTRIG1_o","-","outTRIG1_o : out std_logic;"]
["pld2","OUTPUT","outTRIGh","tp","Test Point","i","i","I","TIM Internal",{"$nulls":6},"2003-01-01","outTRIGh_o","-","outTRIGh_o : out std_logic;"]
["pld2","OUTPUT","SABCR1",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SABCR1_o","-","SABCR1_o : out std_logic;"]
["pld2","OUTPUT","SACAL",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SACAL_o","-","SACAL_o : out std_logic;"]
["pld2","OUTPUT","SAECR1",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SAECR1_o","-","SAECR1_o : out std_logic;"]
["pld2","OUTPUT","SAFER",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SAFER_o","-","SAFER_o : out std_logic;"]
["pld2","OUTPUT","SASpare",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SASpare_o","-","SASpare_o : out std_logic;"]
["pld2","OUTPUT","StartSeq",7,"pld 7","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","StartSeq_o","-","StartSeq_o : out std_logic;"]
["pld2","OUTPUT","StartSink",7,"pld 7","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","StartSink_o","-","StartSink_o : out std_logic;"]
["pld2","OUTPUT","TestBusyON",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","TestBusyON_o","-","TestBusyON_o : out std_logic;"]
["pld2","OUTPUT","TTC_ready2_6",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","TTC_ready2_6_o","-","TTC_ready2_6_o : out std_logic;"]
["pld2","OUTPUT","vBurstGo",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","vBurstGo_o","-","vBurstGo_o : out std_logic;"]
["pld2","OUTPUT","vBurstMode",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","vBurstMode_o","-","vBurstMode_o : out std_logic;"]
["pld2","OUTPUT","vRodBusy",8,"pld 8","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","vRodBusy_o","-","vRodBusy_o : out std_logic;"]
["pld3","BIPUT","db[15..0]","All-1","pld All-1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","db_o","(15 downto 0)","db_o : out std_logic_vector(15 downto 0);"]
["pld3","INPUT","bReadb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bReadb_i","-","bReadb_i : in  std_logic;"]
["pld3","INPUT","bWriteb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bWriteb_i","-","bWriteb_i : in  std_logic;"]
["pld3","INPUT","clk3","cc","Clock Control","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","clk3_i","-","clk3_i : in  std_logic;"]
["pld3","INPUT","enExtRodBusy","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_i","-","enExtRodBusy_i : in  std_logic;"]
["pld3","INPUT","enRandom",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enRandom_i","-","enRandom_i : in  std_logic;"]
["pld3","INPUT","intBusy",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","intBusy_i","-","intBusy_i : in  std_logic;"]
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["pld6","OUTPUT","enBCID","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enBCID_o","-","enBCID_o : out std_logic;"]
["pld6","OUTPUT","enExtRodBusy_in",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_in_o","-","enExtRodBusy_in_o : out std_logic;"]
["pld6","OUTPUT","enL1ID","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enL1ID_o","-","enL1ID_o : out std_logic;"]
["pld6","OUTPUT","enRodBusy",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enRodBusy_o","-","enRodBusy_o : out std_logic;"]
["pld6","OUTPUT","enSABCR2","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enSABCR2_o","-","enSABCR2_o : out std_logic;"]
["pld6","OUTPUT","enSAECR2","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enSAECR2_o","-","enSAECR2_o : out std_logic;"]
["pld6","OUTPUT","enTType","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enTType_o","-","enTType_o : out std_logic;"]
["pld6","OUTPUT","idBCR","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","idBCR_o","-","idBCR_o : out std_logic;"]
["pld6","OUTPUT","idECR","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","idECR_o","-","idECR_o : out std_logic;"]
["pld6","OUTPUT","idTRIG","4a,4b","pld 4a,4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","idTRIG_o","-","idTRIG_o : out std_logic;"]
["pld7","BIPUT","db[15..0]","All-1","pld All-1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","db_o","(15 downto 0)","db_o : out std_logic_vector(15 downto 0);"]
["pld7","BIPUT","SeqD[7..0]","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SeqD_o","(7 downto 0)","SeqD_o : out std_logic_vector(7 downto 0);"]
["pld7","BIPUT","SinkD[7..0]","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SinkD_o","(7 downto 0)","SinkD_o : out std_logic_vector(7 downto 0);"]
["pld7","INPUT","ab[15..1]","v","VME","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","ab_i","(15 downto 1)","ab_i : in  std_logic_vector(15 downto 1);"]
["pld7","INPUT","bReadb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bReadb_i","-","bReadb_i : in  std_logic;"]
["pld7","INPUT","bWriteb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bWriteb_i","-","bWriteb_i : in  std_logic;"]
["pld7","INPUT","enExtRodBusy","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_i","-","enExtRodBusy_i : in  std_logic;"]
["pld7","INPUT","RAMselect",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","RAMselect_i","-","RAMselect_i : in  std_logic;"]
["pld7","INPUT","Reg1A",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg1A_i","-","Reg1A_i : in  std_logic;"]
["pld7","INPUT","Reg1C",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg1C_i","-","Reg1C_i : in  std_logic;"]
["pld7","INPUT","SeqClk","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SeqClk_i","-","SeqClk_i : in  std_logic;"]
["pld7","INPUT","SinkClk","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SinkClk_i","-","SinkClk_i : in  std_logic;"]
["pld7","INPUT","StartSeq",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","StartSeq_i","-","StartSeq_i : in  std_logic;"]
["pld7","INPUT","StartSink",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","StartSink_i","-","StartSink_i : in  std_logic;"]
["pld7","OUTPUT","nSeqCS","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nSeqCS_o","-","nSeqCS_o : out std_logic;"]
["pld7","OUTPUT","nSeqOE","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nSeqOE_o","-","nSeqOE_o : out std_logic;"]
["pld7","OUTPUT","nSeqWrEn","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nSeqWrEn_o","-","nSeqWrEn_o : out std_logic;"]
["pld7","OUTPUT","nSinkCS","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nSinkCS_o","-","nSinkCS_o : out std_logic;"]
["pld7","OUTPUT","nSinkOE","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nSinkOE_o","-","nSinkOE_o : out std_logic;"]
["pld7","OUTPUT","nSinkWrEn","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nSinkWrEn_o","-","nSinkWrEn_o : out std_logic;"]
["pld7","OUTPUT","SeqA[14..0]","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SeqA_o","(14 downto 0)","SeqA_o : out std_logic_vector(14 downto 0);"]
["pld7","OUTPUT","seqBCR",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqBCR_o","-","seqBCR_o : out std_logic;"]
["pld7","OUTPUT","SeqBusy",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SeqBusy_o","-","SeqBusy_o : out std_logic;"]
["pld7","OUTPUT","seqCAL",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqCAL_o","-","seqCAL_o : out std_logic;"]
["pld7","OUTPUT","seqECR",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqECR_o","-","seqECR_o : out std_logic;"]
["pld7","OUTPUT","seqFER",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqFER_o","-","seqFER_o : out std_logic;"]
["pld7","OUTPUT","seqID",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqID_o","-","seqID_o : out std_logic;"]
["pld7","OUTPUT","seqSpare",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqSpare_o","-","seqSpare_o : out std_logic;"]
["pld7","OUTPUT","seqTRIG",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqTRIG_o","-","seqTRIG_o : out std_logic;"]
["pld7","OUTPUT","seqTT",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","seqTT_o","-","seqTT_o : out std_logic;"]
["pld7","OUTPUT","SinkA[14..0]","r","RAM","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SinkA_o","(14 downto 0)","SinkA_o : out std_logic_vector(14 downto 0);"]
["pld7","OUTPUT","SinkBusy",3,"pld 3","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","SinkBusy_o","-","SinkBusy_o : out std_logic;"]
["pld8","BIPUT","db[15..0]","All-1","pld All-1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","db_o","(15 downto 0)","db_o : out std_logic_vector(15 downto 0);"]
["pld8","INPUT","bReadb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bReadb_i","-","bReadb_i : in  std_logic;"]
["pld8","INPUT","bWriteb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bWriteb_i","-","bWriteb_i : in  std_logic;"]
["pld8","INPUT","clk8","cc","Clock Control","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","clk8_i","-","clk8_i : in  std_logic;"]
["pld8","INPUT","enExtRODBusy","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRODBusy_i","-","enExtRODBusy_i : in  std_logic;"]
["pld8","INPUT","Reg1E",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg1E_i","-","Reg1E_i : in  std_logic;"]
["pld8","INPUT","Reg20",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg20_i","-","Reg20_i : in  std_logic;"]
["pld8","INPUT","Reg22",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg22_i","-","Reg22_i : in  std_logic;"]
["pld8","INPUT","Reg24",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg24_i","-","Reg24_i : in  std_logic;"]
["pld8","INPUT","vRodBusy",2,"pld 2","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","vRodBusy_i","-","vRodBusy_i : in  std_logic;"]
["pld9","BIPUT","db[15..0]","All-1","pld All-1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","db_o","(15 downto 0)","db_o : out std_logic_vector(15 downto 0);"]
["pld9","INPUT","bReadb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bReadb_i","-","bReadb_i : in  std_logic;"]
["pld9","INPUT","bWriteb","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","bWriteb_i","-","bWriteb_i : in  std_logic;"]
["pld9","INPUT","clk9","cc","Clock Control","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","clk9_i","-","clk9_i : in  std_logic;"]
["pld9","INPUT","enExtRodBusy","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","enExtRodBusy_i","-","enExtRodBusy_i : in  std_logic;"]
["pld9","INPUT","nLEb2","All","pld All","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld9","INPUT","Reg26",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg26_i","-","Reg26_i : in  std_logic;"]
["pld9","INPUT","Reg28",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg28_i","-","Reg28_i : in  std_logic;"]
["pld9","INPUT","Reg2C",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg2C_i","-","Reg2C_i : in  std_logic;"]
["pld9","INPUT","Reg2E",1,"pld 1","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Reg2E_i","-","Reg2E_i : in  std_logic;"]
["pld9","INPUT","TIM_OK_OUT","All-6","pld All-6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld9","OUTPUT","BCntIn[11..0]","4a,4b","pld 4a,4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","BCntIn_o","(11 downto 0)","BCntIn_o : out std_logic_vector(11 downto 0);"]
["pld9","OUTPUT","BCntStrobe","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","BCntStrobe_o","-","BCntStrobe_o : out std_logic;"]
["pld9","OUTPUT","CALin",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","CALin_o","-","CALin_o : out std_logic;"]
["pld9","OUTPUT","FERin",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","FERin_o","-","FERin_o : out std_logic;"]
["pld9","OUTPUT","L1CntHighStrobe","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","L1CntHighStrobe_o","-","L1CntHighStrobe_o : out std_logic;"]
["pld9","OUTPUT","L1CntLowStrobe","4a","pld 4a","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","L1CntLowStrobe_o","-","L1CntLowStrobe_o : out std_logic;"]
["pld9","OUTPUT","Sparein",6,"pld 6","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","Sparein_o","-","Sparein_o : out std_logic;"]
["pld9","OUTPUT","TTIDin[9..0]","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","TTIDin_o","(9 downto 0)","TTIDin_o : out std_logic_vector(9 downto 0);"]
["pld9","OUTPUT","TTypeStrobe","4b","pld 4b","i","i","i","TIM Internal",{"$nulls":6},"2003-01-01","TTypeStrobe_o","-","TTypeStrobe_o : out std_logic;"]
["pld9","INPUT","BCRin","t","TTCrx","i","t","t","TTCrx",{"$nulls":6},"2003-01-01","BCRin_i","-","BCRin_i : in  std_logic;"]
["pld1","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld1","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld2","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld2","INPUT","TTC_Ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_Ready_in_i","-","TTC_Ready_in_i : in  std_logic;"]
["pld2","OUTPUT","SATRIG","3, 6","pld 3, 6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","SATRIG_o","-","SATRIG_o : out std_logic;"]
["pld3","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld3","INPUT","SATRIG","2, 6","pld 2, 6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","SATRIG_i","-","SATRIG_i : in  std_logic;"]
["pld3","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld3","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld4a","INPUT","idTRIG","4b,6","pld 4b,6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","idTRIG_i","-","idTRIG_i : in  std_logic;"]
["pld4a","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld4a","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld4a","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld4b","INPUT","idTRIG","4a,6","pld 4a,6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","idTRIG_i","-","idTRIG_i : in  std_logic;"]
["pld4b","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld4b","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld4b","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld5","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld5","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld5","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld6","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld7","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld7","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld7","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld8","INPUT","nLEb2","All","pld All","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","nLEb2_i","-","nLEb2_i : in  std_logic;"]
["pld8","INPUT","TIM_OK_OUT","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TIM_OK_OUT_i","-","TIM_OK_OUT_i : in  std_logic;"]
["pld8","INPUT","TTC_ready_in","All-6","pld All-6","ii","ii","ii","Duplicated (Int)",{"$nulls":6},"2003-01-01","TTC_ready_in_i","-","TTC_ready_in_i : in  std_logic;"]
["pld1","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld2","INPUT","eclExtBusy","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclExtBusy_i","-","eclExtBusy_i : in  std_logic;"]
["pld2","INPUT","enTTCClk",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","enTTCClk_i","-","enTTCClk_i : in  std_logic;"]
["pld2","INPUT","NimExtBusy","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","NimExtBusy_i","-","NimExtBusy_i : in  std_logic;"]
["pld2","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld2","INPUT","rod_crate_BusyOut",3,"pld 3","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","rod_crate_BusyOut_i","-","rod_crate_BusyOut_i : in  std_logic;"]
["pld2","OUTPUT","BusyOut","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","BusyOut_o","-","BusyOut_o : out std_logic;"]
["pld2","OUTPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_o","-","RunMode_o : out std_logic;"]
["pld2","OUTPUT","SAMode","fl","Front-Panel LEDs","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","SAMode_o","-","SAMode_o : out std_logic;"]
["pld3","INPUT","BusyOut",2,"pld 2","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","BusyOut_i","-","BusyOut_i : in  std_logic;"]
["pld3","INPUT","eclExtBusy","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclExtBusy_i","-","eclExtBusy_i : in  std_logic;"]
["pld3","INPUT","NimExtBusy","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","NimExtBusy_i","-","NimExtBusy_i : in  std_logic;"]
["pld3","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld3","INPUT","rod_crate_BusyOut",2,"pld 2","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","rod_crate_BusyOut_i","-","rod_crate_BusyOut_i : in  std_logic;"]
["pld3","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld3","INPUT","SAMode",2,"pld 2","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","SAMode_i","-","SAMode_i : in  std_logic;"]
["pld4a","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld4a","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld4b","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld4b","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld5","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld5","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld6","INPUT","ECRin","t","TTCrx","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","ECRin_i","-","ECRin_i : in  std_logic;"]
["pld6","INPUT","L1Ain","t","TTCrx","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","L1Ain_i","-","L1Ain_i : in  std_logic;"]
["pld6","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld6","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld6","OUTPUT","eclBCR","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclBCR_o","-","eclBCR_o : out std_logic;"]
["pld6","OUTPUT","eclCAL","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclCAL_o","-","eclCAL_o : out std_logic;"]
["pld6","OUTPUT","eclECR","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclECR_o","-","eclECR_o : out std_logic;"]
["pld6","OUTPUT","eclFER","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclFER_o","-","eclFER_o : out std_logic;"]
["pld6","OUTPUT","eclID","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclID_o","-","eclID_o : out std_logic;"]
["pld6","OUTPUT","eclL1A","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclL1A_o","-","eclL1A_o : out std_logic;"]
["pld6","OUTPUT","eclSpare","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclSpare_o","-","eclSpare_o : out std_logic;"]
["pld6","OUTPUT","eclTT","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclTT_o","-","eclTT_o : out std_logic;"]
["pld6","OUTPUT","enTTCClk","cc","Clock Control","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","enTTCClk_o","-","enTTCClk_o : out std_logic;"]
["pld7","INPUT","eclBCR",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclBCR_i","-","eclBCR_i : in  std_logic;"]
["pld7","INPUT","eclCAL",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclCAL_i","-","eclCAL_i : in  std_logic;"]
["pld7","INPUT","eclECR",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclECR_i","-","eclECR_i : in  std_logic;"]
["pld7","INPUT","eclFER",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclFER_i","-","eclFER_i : in  std_logic;"]
["pld7","INPUT","eclID",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclID_i","-","eclID_i : in  std_logic;"]
["pld7","INPUT","eclL1A",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclL1A_i","-","eclL1A_i : in  std_logic;"]
["pld7","INPUT","eclSpare",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclSpare_i","-","eclSpare_i : in  std_logic;"]
["pld7","INPUT","eclTT",6,"pld 6","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","eclTT_i","-","eclTT_i : in  std_logic;"]
["pld7","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld7","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld8","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld8","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld8","OUTPUT","fp_rod_crate_busyout","f",{"$error":"#N/A"},"x","x","x","Duplicated (Ext)",{"$nulls":3},"t","Translator req'd","Duplicate with rod_crate_busyout?","2003-01-01","extRodCrateBUSY_o","-","extRodCrateBUSY_o : out std_logic;"]
["pld8","OUTPUT","rod_crate_BusyOut","fl","Front-Panel LEDs","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","rod_crate_BusyOut_o","-","rod_crate_BusyOut_o : out std_logic;"]
["pld9","INPUT","ECRin","t","TTCrx","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","ECRin_i","-","ECRin_i : in  std_logic;"]
["pld9","INPUT","L1Ain","t","TTCrx","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","L1Ain_i","-","L1Ain_i : in  std_logic;"]
["pld9","INPUT","nOA_rst","All","pld All","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","nOA_rst_i","-","nOA_rst_i : in  std_logic;"]
["pld9","INPUT","RunMode","All-1","pld All-1","x","x","x","Duplicated (Ext)",{"$nulls":6},"2003-01-01","RunMode_i","-","RunMode_i : in  std_logic;"]
["pld1","INPUT","s1_2[7..0]",2,"Spares pld 2","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s1_2_i","(7 downto 0)","s1_2_i : in  std_logic_vector(7 downto 0);"]
["pld1","INPUT","s1_5[5..0]",5,"Spares pld 5","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s1_5_i","(5 downto 0)","s1_5_i : in  std_logic_vector(5 downto 0);"]
["pld1","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld1","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld1","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld1","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld1","OUTPUT","nReg32","v","VME","z","z","z","Deleted",{"$nulls":6},"2003-01-01","nReg32_o","-","nReg32_o : out std_logic;"]
["pld2","INPUT","EclExt_Clk1","f",{"$error":"#N/A"},"z","z","z","Deleted",{"$nulls":6},"2003-01-01","EclExt_Clk1_i","-","EclExt_Clk1_i : in  std_logic;"]
["pld2","INPUT","EclExt_Clk2","f",{"$error":"#N/A"},"z","z","z","Deleted",{"$nulls":6},"2003-01-01","EclExt_Clk2_i","-","EclExt_Clk2_i : in  std_logic;"]
["pld2","INPUT","int_clk1","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","int_clk1_i","-","int_clk1_i : in  std_logic;"]
["pld2","INPUT","int_clk2","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","int_clk2_i","-","int_clk2_i : in  std_logic;"]
["pld2","INPUT","NimExt_Clk","f",{"$error":"#N/A"},"z","z","z","Deleted",{"$nulls":6},"2003-01-01","NimExt_Clk_i","-","NimExt_Clk_i : in  std_logic;"]
["pld2","INPUT","s1_2[7..0]",1,"Spares pld 1","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s1_2_i","(7 downto 0)","s1_2_i : in  std_logic_vector(7 downto 0);"]
["pld2","INPUT","s2_3[5..0]",3,"Spares pld 3","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s2_3_i","(5 downto 0)","s2_3_i : in  std_logic_vector(5 downto 0);"]
["pld2","INPUT","s2_4a[7..0]","4a","Spares pld 4a","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s2_4a_i","(7 downto 0)","s2_4a_i : in  std_logic_vector(7 downto 0);"]
["pld2","INPUT","s2_6[5..0]",6,"Spares pld 6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s2_6_i","(5 downto 0)","s2_6_i : in  std_logic_vector(5 downto 0);"]
["pld2","INPUT","SAClkON_out",3,"pld 3","z","z","z","Deleted",{"$nulls":6},"2003-01-01","SAClkON_out_i","-","SAClkON_out_i : in  std_logic;"]
["pld2","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld2","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld2","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld2","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld2","INPUT","TTCClkIn","t","TTCrx","z","z","z","Deleted",{"$nulls":6},"2003-01-01","TTCClkIn_i","-","TTCClkIn_i : in  std_logic;"]
["pld2","INPUT","TTCClkON_out",3,"pld 3","z","z","z","Deleted",{"$nulls":6},"2003-01-01","TTCClkON_out_i","-","TTCClkON_out_i : in  std_logic;"]
["pld2","OUTPUT","clkIn","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","clkIn_o","-","clkIn_o : out std_logic;"]
["pld2","OUTPUT","nOA_reset","rst","Resets","z","z","z","Deleted",{"$nulls":6},"2003-01-01","nOA_reset_o","-","nOA_reset_o : out std_logic;"]
["pld2","OUTPUT","nTTC_CLK_MODE","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","nTTC_CLK_MODE_o","-","nTTC_CLK_MODE_o : out std_logic;"]
["pld2","OUTPUT","OA_reset","rst","Resets","z","z","z","Deleted",{"$nulls":6},"2003-01-01","OA_reset_o","-","OA_reset_o : out std_logic;"]
["pld3","INPUT","clkInB1","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","clkInB1_i","-","clkInB1_i : in  std_logic;"]
["pld3","INPUT","s2_3[5..0]",2,"Spares pld 2","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s2_3_i","(5 downto 0)","s2_3_i : in  std_logic_vector(5 downto 0);"]
["pld3","INPUT","s3_9[7..0]",9,"Spares pld 9","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s3_9_i","(7 downto 0)","s3_9_i : in  std_logic_vector(7 downto 0);"]
["pld3","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld3","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld3","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld3","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld3","OUTPUT","SAClkON_out",2,"pld 2","z","z","z","Deleted",{"$nulls":6},"2003-01-01","SAClkON_out_o","-","SAClkON_out_o : out std_logic;"]
["pld3","OUTPUT","TTCClkON_out",2,"pld 2","z","z","z","Deleted",{"$nulls":6},"2003-01-01","TTCClkON_out_o","-","TTCClkON_out_o : out std_logic;"]
["pld4a","INPUT","s2_4a[7..0]",2,"Spares pld 2","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s2_4a_i","(7 downto 0)","s2_4a_i : in  std_logic_vector(7 downto 0);"]
["pld4a","INPUT","s4a_4b[7..0]","4b","Spares pld 4b","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s4a_4b_i","(7 downto 0)","s4a_4b_i : in  std_logic_vector(7 downto 0);"]
["pld4a","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld4a","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld4a","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld4a","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld4b","INPUT","s4a_4b[7..0]","4a","Spares pld 4a","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s4a_4b_i","(7 downto 0)","s4a_4b_i : in  std_logic_vector(7 downto 0);"]
["pld4b","INPUT","s4b_5[7..0]",5,"Spares pld 5","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s4b_5_i","(7 downto 0)","s4b_5_i : in  std_logic_vector(7 downto 0);"]
["pld4b","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld4b","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld4b","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld4b","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld5","BIPUT","db_h[15..8]","All-1","pld All-1","z","z","z","Deleted",{"$nulls":6},"2003-01-01","db_h_o","(15 downto 8)","db_h_o : out std_logic_vector(15 downto 8);"]
["pld5","BIPUT","db_l[7..0]","All-1","pld All-1","z","z","z","Deleted",{"$nulls":6},"2003-01-01","db_l_o","(7 downto 0)","db_l_o : out std_logic_vector(7 downto 0);"]
["pld5","INPUT","s1_5[5..0]",1,"Spares pld 1","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s1_5_i","(5 downto 0)","s1_5_i : in  std_logic_vector(5 downto 0);"]
["pld5","INPUT","s4b_5[7..0]","4b","Spares pld 4b","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s4b_5_i","(7 downto 0)","s4b_5_i : in  std_logic_vector(7 downto 0);"]
["pld5","INPUT","s5_6[7..0]",6,"Spares pld 6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s5_6_i","(7 downto 0)","s5_6_i : in  std_logic_vector(7 downto 0);"]
["pld5","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld5","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld5","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld5","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld6","INPUT","s2_6[5..0]",2,"Spares pld 2","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s2_6_i","(5 downto 0)","s2_6_i : in  std_logic_vector(5 downto 0);"]
["pld6","INPUT","s5_6[7..0]",5,"Spares pld 5","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s5_6_i","(7 downto 0)","s5_6_i : in  std_logic_vector(7 downto 0);"]
["pld6","INPUT","s6_7[7..0]",7,"Spares pld 7","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s6_7_i","(7 downto 0)","s6_7_i : in  std_logic_vector(7 downto 0);"]
["pld6","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld6","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld6","OUTPUT","nenTTCClk","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","nenTTCClk_o","-","nenTTCClk_o : out std_logic;"]
["pld7","INPUT","s6_7[7..0]",6,"Spares pld 6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s6_7_i","(7 downto 0)","s6_7_i : in  std_logic_vector(7 downto 0);"]
["pld7","INPUT","s7_8[7..0]",8,"Spares pld 8","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s7_8_i","(7 downto 0)","s7_8_i : in  std_logic_vector(7 downto 0);"]
["pld7","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld7","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld7","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld7","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld7","OUTPUT","XSeqClk1","tp","Test Point","z","z","z","Deleted",{"$nulls":6},"2003-01-01","XSeqClk1_o","-","XSeqClk1_o : out std_logic;"]
["pld7","OUTPUT","XSeqClk2","tp","Test Point","z","z","z","Deleted",{"$nulls":6},"2003-01-01","XSeqClk2_o","-","XSeqClk2_o : out std_logic;"]
["pld7","OUTPUT","XSeqTRIG","tp","Test Point","z","z","z","Deleted",{"$nulls":6},"2003-01-01","XSeqTRIG_o","-","XSeqTRIG_o : out std_logic;"]
["pld8","INPUT","s7_8[7..0]",7,"Spares pld 7","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s7_8_i","(7 downto 0)","s7_8_i : in  std_logic_vector(7 downto 0);"]
["pld8","INPUT","s8_9[7..0]",9,"Spares pld 9","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s8_9_i","(7 downto 0)","s8_9_i : in  std_logic_vector(7 downto 0);"]
["pld8","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld8","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld8","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld8","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]
["pld8","OUTPUT","RBM[15..0]","rsv","Reserved","z","z","z","Deleted","check",null,null,"cb","Change Buffer","Obsolete? John thinks so.","2003-01-01","RBM_o","(15 downto 0)","RBM_o : out std_logic_vector(15 downto 0);"]
["pld9","INPUT","BCclk1b","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","BCclk1b_i","-","BCclk1b_i : in  std_logic;"]
["pld9","INPUT","BCclk2b","cc","Clock Control","z","z","z","Deleted",{"$nulls":6},"2003-01-01","BCclk2b_i","-","BCclk2b_i : in  std_logic;"]
["pld9","INPUT","s3_9[7..0]",3,"Spares pld 3","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s3_9_i","(7 downto 0)","s3_9_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","s8_9[7..0]",8,"Spares pld 8","z","z","z","Deleted",{"$nulls":6},"2003-01-01","s8_9_i","(7 downto 0)","s8_9_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","sgbA[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbA_i","(7 downto 0)","sgbA_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","sgbB[7..0]","All","SpareBus All","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbB_i","(7 downto 0)","sgbB_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","sgbC[7..0]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbC_i","(7 downto 0)","sgbC_i : in  std_logic_vector(7 downto 0);"]
["pld9","INPUT","sgbD[4..2]","All-6","SpareBus All-6","z","z","z","Deleted",{"$nulls":6},"2003-01-01","sgbD_i","(4 downto 2)","sgbD_i : in  std_logic_vector(4 downto 2);"]

{"sheet":"Legend","index":1,"n_rows":43,"n_cols":6,"rows_kept":43,"flags":["formulas_cached_only"]}
[null,"Function Block Table",null,null,"LVTTL Problem/Fix legend"]
[null,"cc","Clock Control",null,"t","Translator req'd"]
[null,"j","Jumpers & DIPs",null,"cp","Change Part"]
[null,"rsv","Reserved",null,"p","Power change only"]
[null,"r","RAM",null,"cb","Change Buffer"]
[null,"t","TTCrx",null,3,"3.3v part"]
[null,"is","Internal Trig, FER, ECR",null,"5i","5V input"]
[null,"fl","Front-Panel LEDs"]
[null,"w","Trigger Window",null,"nc","NO CHANGE!"]
[{"$nulls":4},"n","Entirely New"]
[null,"b","Back-Plane IO",null,"I","local - do nothing"]
[{"$nulls":4},"c3","Use 3.3v version"]
[null,"cp2","PROM2"]
[null,"cp1","PROM1"]
[null,"dh","Debug Bus Header"]
[null,"dms","Debug Mode Switch"]
[null,"ti","TIM ID"]
[]
[null,"f1","FPGA1"]
[null,"ba","Base Addr. Switches"]
[null,"dv","VME Delay Unit"]
[null,"v","VME"]
[]
[null,"if","TIM Internal FIFO"]
[null,"I","TIM Internal"]
[null,"z","Deleted"]
[null,"clk","Clock Distribution"]
[null,"unclear","Still Thinking …"]
[null,"ff","FIFO"]
[null,"-","-"]
[null,"tp","Test Point"]
[null,"bf","Buffer/Fanout"]
[null,"rst","Resets"]
[null,"x","Duplicated (Ext)"]
[null,"ii","Duplicated (Int)"]
[null,"f2","FPGA2"]
[null,"trp","TIM Reset/Prog System"]
[null,"por","Power-On Reset"]
[null,"sf","Special FPGA"]
[null,"usf","Unused Special FPGA"]
[null,"bp","BP Interfacing"]
[null,"fo","Front Panel Out"]
[null,"fi","Front Panel In"]