DAVEUserGuide

Introduction

The DAVE card is able to generate stand alone triggers in a similar way to the CTP. It allows sub-detectors to generate triggers with the same randomness, bunch-group configuration and simple and complex deadtimes. It is designed to be placed in a TTC crate and provide triggers to the TTCvi (or is that LTP?).

The DAVE is also designed as a versatile FPGA utility board. It has NIM IO, a large SRAM etc etc etc.

See DAVEDevNotes for details on setups in FPGA reprog in SR1 etc.

See DAVEHardwareLog for lst of available hardware, location, mods etc.

Firmware

The firmware is in development. A pre-prototype version is available that provides the core functions originally requested by the SCT. The registrer map and control mechanisms are likely to change (hence the "pre-proto" label).

FIRMWARE_BLOCK-B (ppt) (pdf)

Some Pre-Proto Conventions

LED Block

There is a block of 3x4 LEDs on the front panel. They are organised in 3 columns (when in a VME crate) of 4 leds each. From left to right there are 4 green, 4 yellow and 4 red.

These are currently assigned as follows:

Green	Yellow	Red
Trig In	Trig Out	L1ID(3)
Orbit In	Orbit Out	L1ID(2)
ECR In	ECR Out	L1ID(1)
Busy In	Busy Out	L1ID(0)

LEMO I/O Assignments

To help de-confuse, input and output mapping are the same where possible

LEMO Inputs
C0 Clock0	C1 Clock1
0 Trigger	1 Orbit
2	3
4	5
6	7 Busy

*Active-Low input

LEMO Outputs
C0 Clock	C1 Clock80
0 Trigger	1 Orbit
2	3
4 Internal Trig	5 Internal Orbit
6	7 Busy

Pre-Proto Registers

Note: All accesses are 16bit so A0 is essentially ignored.

Overall Mapping
0x000000-0x00003E	Status Block (32 x 16b)
0x000100-0x00013E	Register Block (32 x 16b )
0x000200	Delay25 I2C control/IO register
0x000300	Commands register
0x000400-0x0005BC	Bunch-group Block (223 x 16b)
0x000600-0x000602	L1ID FIFO readout*
0x800000-0xFFFFFE	SRAM (4M x 16b)

* In version 0x0029 onwards

Status Block (0x000)

No.	Offset	Name	Short Name	Description
0	0x000	Sanity Check = 0xDAFE	SANITY	Fixed to 0xDAFE (almost 0xDAVE) for sanity checks
1	0x002	0x0000
2	0x004	Version ID	VERSION_ID	Firmware version id
3	0x006	Hardware ID	HARDWARE_ID	Board version number (8b) + hardware revisions (8b)
4	0x008	Board Status	BOARD_STAT	Status of power supplies and position of FP switch - BOARD_STAT
5	0x00a	Front Panel LEDs
6	0x00c	Lemo Inputs Status	LEMOIN_STAT
7	0x00e	Lemo Outputs Status	LEMOOUT_STAT
8	0x010	L1ID (Extended) Lo	L1ID_LO
9	0x012	L1ID (Extended) Hi	L1ID_HI
10	0x014	SeqSink Address Lo	SSAD_LO
11	0x016	SeqSink Address Hi	SSAD_HI
12	0x018	SeqSink Count Lo	SSCOUNT_LO
13	0x01a	SeqSink Count Hi	SSCOUNT_HI
14	0x01c	Sequencer Status	SEQ_STAT	SEQ_STAT
15*	0x01e	L1ID FIFO Status	LF_STAT	LF_STAT
16*	0x020	Lemo In Latch	LEMOIN_LCH	Stores if a signal has been asserted since last reset. Cleared using a COMMAND
17*	0x022	Lemo Out Latch	LEMOOUT_LCH	Stores if a signal has been asserted since last reset. Cleared using a COMMAND
18	0x024	0x2524
19	0x026	0x2726
20	0x028	0x2928
21	0x02a	0x2b2a
22	0x02c	0x2d2c
23	0x02e	0x2f2e
24	0x030	0x3130
25	0x032	0x3332
26	0x034	0x3534
27	0x036	0x3736
28	0x038	0x3938
29	0x03a	0x3b3a
30	0x03c	0x3d3c
31	0x03e	0x3f3e

* Implemented from v0029

BOARD_STAT

Board Status Word (4 - 0x008)

Bit	Description
15	0
14	mon_m5vok
13	mon_m2vok
12	mon_5vok
11	mon_3v3ok
10	mon_2v5ok
9	mon_1v8ok
8	mon_1v2ok
7:4	0x0
3:0	sw_opt

SEQ_STAT

Sequencer Status Word (14 - 0x01e)

Bit	Description
1	0x0
0	Sequencer Running

Register Block (0x100)

No.	Offset	Name	Short Name	Description
0	0x100	LEMO Input Enables	LEMOIN_ENA	LEMO inputs enable LEMOIN_ENA
1	0x102	LEMO Output Enables	LEMOOUT_ENA	LEMO outputs enable LEMOOUT_ENA
2	0x104	Internal Enables	INT_ENA	Overall enable for all signal sources INT_ENA
3	0x106	Random Seed Lo	RND_SEED_LO	16b random trig seed 15:0 - resets to 0x1971
4	0x108	Random Seed Hi	RND_SEED_HI	Random trig seed 31:16 - resets to 0x0112
5	0x10a	Random Rate	RND_RATE	5b random trig rate - range 0-0x1c only, decending
6	0x10c	Simple Dead-time Length	SDT_LENGTH	16b simple deadtime length
7	0x10e	Complex Dead-time Level	CDT_LEVEL	8b complex deadtime level
8	0x110	Complex Dead-time Rate	CDT_RATE	16b complex deadtime rate
9	0x112	BCID Offset	BCID_OFFSET	12b BCID offset used to align bunch-groups system
10	0x114	LEMO Inputs Invert	LEMOIN_INV	Bits corrospond to the inputs in LEMOIN_ENA (except clocks)
11	0x116	LEMO Outputs Invert	LEMOOUT_INV	Bits corrospond to the outputs in LEMOOUT_ENA
12	0x118	Sequencer End Address (lo)	SEQ_END_LO
13	0x11a	Sequencer End Address (hi)	SEQ_END_HI
14	0x11c	Sequencer Enables	SEQ_ENA	SEQ_ENA
15	0x11e	Debug Function	DEBUG	Allows setting of debug features DEBUG

LEMOIN_ENA

Lemo Input Enables Reg (0 - 0x100)

Bit	Name	Description
9
8	LEMOIN_CLK0
7	LEMOIN_BUSY
6	LEMOIN_6
5	LEMOIN_5
4	LEMOIN_4
3	LEMOIN_3
2	LEMOIN_ECR
1	LEMOIN_ORBIT
0	LEMOIN_TRIG

LEMOOUT_ENA

Lemo Output Enables Reg (1 - 0x102)

Bit	Name	Description
9	LEMOOUT_CLK1	80MHz clock
8	LEMOOUT_CLK0	Main clock output
7	LEMOOUT_BUSY
6	LEMOOUT_6
5	LEMOOUT_5
4	LEMOOUT_4
3	LEMOOUT_3
2	LEMOOUT_ECR
1	LEMOOUT_ORBIT
0	LEMOOUT_TRIG

INT_ENA

Internal Enables Reg (2 - 0x104)

Bit	Name	Description
15
14
13	BUSY_ECR_EN
12	CLK_80_SEL	Set 80 MHz clock (0 = 40MHz)
11	CTP_FUNC_EN	Enable CTP funcs SDT, CDT, BGrp
10	CDT_EN	Complex dead-time enable
9	SINK_ADDR_CLR	DEPRICATED - Use COMMAND - SRAM Sink mode address clear - set to offset 0
8	SINK_MODE	Enable SRAM recording trigger period mode (disables VME/USB access to SRAM)
7	INT_BUSY_EN*	Enables e.g. ECR or CDT busy output
6
5
4
3
2	INT_ECR_EN	Internal ECR generator enable
1	INT_ORBIT_EN	Internal Orbit enable
0	INT_TRIG_EN	Internal Trigger enable

* Not fully implemented.

SEQ_ENA

Sequencer Enables Reg (2 - 0x11c)

Is set to zero for recording

Bit	Name	Description
10 0x0400
9 0x0200	CYCLIC_EN*	Set sequencer to continually cycle
8 0x0100	SEQ_MODE	Enable the sequencer (stops VME/USB access to RAM
7 0x0080
6 0x0040
5 0x0020
4 0x0010
3 0x0008
2 0x0004	SEQ_ECR_EN	Internal ECR generator enable
1 0x0002	SEQ_ORBIT_EN	Internal Orbit enable
0 0x0001	SEQ_TRIG_EN	Internal Trigger enable

* Not implemented yet.

DEBUG

Debug Reg (15 - 0x11e)

Bit	Name	Description
2
1	SINK_TEST_MODE	SRAM period data replaced with 32b trigger counter
0	TRIG_CONST1	Sets trigger input to 1

Command Register (0x300)

The command address is used to send pulses. A write to this address will generate a 1 clock wide pulse on all the bits set to 1.

Bit	Name	Description
15 0x8000	LEMOOUT_LCH_CLR
14 0x4000	LEMOIN_LCH_CLR
13 0x2000	ECRID_RST	Set ECR-ID to 0
12 0x1000	L1ID_RST	Set L1ID to 0xffffff
11 0x0800	LF_RST	L1ID FIFO reset
10 0x0400
9 0x0200	SSAD_CLR	Reset the start address used by Seq/Sink to 0
8 0x0100	SEQ_GO	Start the sequencer running
7 0x0080
6 0x0040
5 0x0020
4 0x0010
3 0x0008
2 0x0004	CMD_ECR	Generate an ECR
1 0x0002	CMD_ORBIT	Genrate an Orbit
0 0x0001	CMD_TRIG	Generate a Trigger

Bunch Group RAM (0x400-0x5BC)

Each bit in this RAM corrosponds to a BCID.

L1ID FIFO (0x600-0x602) *

* Implemented from v0029 only Extended L1IDs (32b) are stored in a FIFO when a ECR is issued. This allows TTC2LAN (or similar) software to generate the correct number of ROS requests. Only a reads from 0x600 will advance the get the next value from the FIFO, So reads should always follow the sequence 0x600 then 0x602. The LF_STAT register has bits for full,empty and depth.

Addr	Data
0x602	ECRID(7:0) + L1ID(23:16)
0x600=	L1ID(15:0)

Sink Mode Operation

When in Sink-Mode, periods between signals are recorded to the SRAM. The SRAM is not accessable by VME/USB in this mode. The SINK_MODE bit must be set to 0 to read out the SRAM.

Status registers 10/11 (SSAD) contains the NEXT address to be used in the SRAM. Status registers 12/13 (SSCOUNT) contains the number of events recorded in the SRAM since the last clear/reset.

Periods (count of clocks) between signals are recorded in the range 0-0xffe. Periods longer than this are recorded as 0xfff. Periods between Trig, ECR, BCR and either rising or falling busy are recorded. The data are recorded as 16bit words ( 1 per address). The top 4 bits are used to encode which signal occurred.

SRAM Data Format

15	14	13	12	11:0
Busy*	ECR	BCR	Trig	Period count

* Busy shows the status of the busy, but the period is recorded each time busy rises or falls. This may be a flawed way of doing things - comments welcome.

More Documents and Information

Dave Robinson's ATLAS Presentation, CERN, 03 May 2011

Dave Robinson's Presentation - ATLAS - 03 May 2011 (ppt)
Dave Robinson's Presentation - ATLAS - 03 May 2011 (pdf)

From TWEPP-2011 POSTER Presentation

Design of a "Digital Atlas Vme Electronics" ( DAVE ) Module

Maurice Goodrick <goodrick@hep.phy.cam.ac.uk>
Dave Robinson <robinson@hep.phy.cam.ac.uk>
Rick Shaw <shaw@hep.phy.cam.ac.uk>
Cavendish Laboratory, Department of Physics, University of Cambridge

Martin Postranecky <mp@hep.ucl.ac.uk>
Matthew Warren <warren@hep.ucl.ac.uk>
Department of Physics and Astronomy, University College London

ABSTRACT

ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ( "DAVE" ). The unit was designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts.

DAVE aims to provide exact ATLAS CTP functionality, with random trigger, simple and complex deadtime, ECR, BCR etc. being generated to give exactly the same conditions in standalone running as experienced in combined runs.

DAVE provides additional hardware and a large amount of free firmware resource to allow users to add or change functionality.

SUMMARY

ATLAS-SCT uses NIM electronics in USA15 to provide the trigger and veto logic needed in stand-alone physics runs. This needs to be updated as some of the components drift uncontrollably and adjustments need to be made manually.

Initially a purpose specific 6U VME card was proposed as a replacement, but this design quickly grew to incorporate many more generic features.

One significant enhancement was to adopt all ATLAS CTP functions to exactly duplicate ATLAS running conditions, whilst incorporating much generic functionality. This evolved the DAVE card into a powerful and flexible logic module, potentially useful to all ATLAS subsystems as well as for other non-ATLAS users.

DAVE communication is by standard VME or by USB, allowing use inside VME-TTC crate or stand-alone on a bench-top. For this reason, +5V is the single power input ( from the VME backplane or a stand-alone power supply ), with all other power buses being generated on-board.

Firmware is developed in a modular fashion allowing code contributions from interested users. Initially the core SCT requirements ( vetoing trigger generation around a BCR ) will be implemented.

Further development will aim to provide other CTP functionality, with random trigger generator up to 100kHz, simple and complex deadtime, busy gating, ECR, BCR, etc. generation to give exact same conditions in standalone as experienced in combined runs.

Firmware for this purpose is being copied from the CTP code to ensure identical operation.

Some other useful capabilities include BC/ORBIT source with fine-delay ( with 0.5nsec resolution ) for timing scans, generic counter facility, etc.

In addition, a large 'trigger sequence record / playback' is incorporated on a 72Mbit SRAM. This provides up to 52 seconds history of trigger playback at 75 kHz L1 trigger rate ( e.g. on interrupt by system BUSY ).

The final design is a single 6U VME card with 2 clock inputs and outputs ( as NIM or ECL on LEMO connectors ) and 8 programmable data inputs and outputs ( as NIM or TTL on LEMOs ), containing a large Xilinx Spartan 3E 1600 ( XC3S1600E-FCG400C ) FPGA, 4Mbx18 SRAM ( GS8642Z18GB 1671 ), on-board 80.15733MHz clock X-tal generator, PLL ( ICS581-02 ) and CERN 'Delay25' delay lines, together with a 40-pin expansion header for possible daughter card(s).

Total of three prototype DAVE modules have been produced and tested by Cambridge and UCL. Further 17 production modules are being manufactured, with some modifications based on the test results, to be delivered to users in the autumn 2011. Additional firmware, suggested by various potential users, is also being developed.

TWEPP-2011 Poster

Poster (ppt) (pdf)

TWEPP-2011 Paper on arXiv

http://arxiv.org/abs/1111.4156

arXiv Paper (pdf) (doc)

Hardware Feature List

Front Panel and PCB Real Estate(pdf)

Hardware Block Diagrams

Annotated PCB Photos -A3-(ppt)

Annotaded PCB Photos (ppt)

Annotaded PCB Photos (pdf)

Hardware Components - Annotated Photos Descriptive Labels

Schematics and PCB

Circuit Schematics(pdf)

PCB Top Silk(pdf)

---

Major updates:
-- MattWarren - 01-Sep-2011
-- MartinP - 06-Sep-2011
-- MartinP - 14-Sep-2011
-- MartinP - 18-Nov-2011

Responsible: MattWarren
Last reviewed by: Never reviewed