This is a list of things to correct on the next version.

1.	No mounting holes for the front panel. Drilled on proto
	pcbs (x3) but need to add sleeve to hole to avoid shorting
	VCC to ground.

2.	SW20 ck_in 0,1 select is wired wrong way. 0 is to right!
	Rotate 180 degrees and leave label as is. FIX on proto
	will have to be - fudge label. Alternative is to drill
	out pins 1 & 3 then wire tack & solder to whats left of pads.

3.	Miniature pb switch has alignment pip on bottom,
	but no hole in pcb. Pip cut off on proto.
	STET. OneCall supplied wrong part.

4.	Needed to remove R13 (0R link), to get volt mon chip
	working OK. Changes from 5% to 10% TOL. 5% should be OK.
	Don't understand this, will come back to it. 150mV drop
	across fuse doesn't help.

5.	RED and BLUE volt OK LEDS are too bright. Increase resistors?
	Blue = 5mA, red = 7.5ma, how much lower can I go?

6.	Mark MSB/LSB on switches. Vme add, Mod, Serial No.

7.	Mark functions on Jtag SIL header.

8.	Increase ECL input buffer bais resistor, (R72, R64...)
	from 1K to ~4K7. (effctively in series with 75K pulldown)

9.	Mod record switches are 0 on right, 1 on left.
	would prefer this to be the other way round.

10.	IN [7..0] are not terminated when TTL is selected.
	Will they be driven by a 50 Ohm source?

11.	Silkscreen text is hard to read due to poor contrast with
	crosshatching. Solid plane would be better, none would be best.

12.	SW12 - SW19 also wired wrong way round. TTL / NIM selection reversed.

13.	U20 (BCT25244) sholud powered from vcc, not 3v3.
	(Add switch to terminate or not?)

14.	Termination issues. Clk_out terminations. Add switches to terminate TTL in.

15.	Route 40/80 clk selection switch into FPGA.