CALICE C+C PCB - CPLD ( U62 ) INPUTS & OUTPUTS ( NEW NUMBERS ) ============================================== MP-UCL, 12 January 2009 1) INPUTS to CPLD : ------------------- LFTRIGTOUTC U25/6 LF Trigger input 143 MCONT<1-4>T U29/3,6,8,1 LK12/1,3,5,7 4x Mixed Control in <77-80> LBUSY<1-8>T U6+U8/11,13,15,17 8x Busy inputs 1,2,<5-10> LSPARE<1-8>T U5+U7/11,13,15,17 8x Spare inputs 18,<21-28> MCLKTOUTC U27/8 CLK0 input 128 CLK1 127 CLK2 126 Delayed clk DL1/2 CLK3 = Delayed CLK 125 TCKL U16/14 J-TAG Clock input 89 TDIL U16/18 J-TAG Data input 4 TMSL U16/16 J-TAG Mode Select in 20 PORT_EN GND via 0R Enable 13 R1IN U52/12 RS232 R1 Line 83 R2IN U52/9 RS232 R2 Line 84 HEXSW<0-3> SW.1 Hex Switch Selector <53-56> A<0-5> DL1/<23-21>,<15-13> Delay Line Select <131-134>,136,137 MCLKTON U21/13 Ext.clock present & on 106 2) OUTPUTS from CPLD : ---------------------- CONTTINC LK12/11 Single Control out 74 BUSYTINC LK3/5 U13/4 Single Busy output 140 SPARETINC LK20/2 Single Spare output 141 LFTRIGTINC U24/3 LK17+18/7 Single LF Trigger out 142 TDOL U16/8 J-TAG Data output 104 T1OUT U52/11 RS232 T1 Line 81 T2OUT U52/10 RS232 T2 Line 82 3) PLUS spare/unused INPUTS/OUTPUTS : ------------------------------------- LH 8-pin SIL Header PL1 <11-16>,<29-31> Bottom 8-pin SIL Header PL3 <60-68> RH 8-pin SIL Header PL5 <91-98> Top 8-pin SIL Header PL2 <109-117> LCPLD-PC<0-7> inputs/outputs to PC CONNECTOR on PL4 <37-42>,44,45 /cont: - 2 - This version : MP-UCL, 12 Jan. 2009 Previous versions : 12 Jan. 2009 18 Aug. 2008 13 Aug. 2008 11 Aug 2008 06 Aug. 2008 04 Aug. 2008 20 Jul. 2008 09 Jul. 2008 02 Jul. 2008 01 Jul. 2008 30 Jun. 2008 22 May 2008 19 May 2008 21 Apr. 2008