CALICE C+C MODULE LINKS ( NEW NUMBERS )
		=======================

		MP - UCL, 08 APRIL 2009


NOTE : '#' indicates default setting
------ '*' indicates setting for stand-alone tests


LK22	Select NIM "NCLK<1-2>OUT" Output Polarity	Diag.02
LK23				
				1+2 = Inverted
			      # 2+3 = True ( NIM -ve standard )


LK5	Insert to Enable "LCLK<1-10>OUT" Drivers U12	Diag.02
LK19	Insert to Enable "LCLK<11-20>OUT" Drivers U35	Diag.02


LK17	Select "LFTRIG<1-10>OUT" Source			Diag.03
LK18			      
			      # 1 = Inputs
				2 = Expansion Header - LVDS
				3 = Expansion Header - LVT
			      * 4 = CPLD
				5 = ECL Inputs ( AC-coupled )


LK4	Insert to Enable "LFTRIG<1-10>OUT" Drivers U11	Diag.03


LK12	Select "MCONTTOUT" Source			Diag.04		

			        1,2,3,4 = Inputs
				5 Expansion Header
			      *	6 CPLD


LK6	Insert to Enable "LCONT<1-10>OUT" Drivers U36	Diag.04


LK27	Select NIM "NBUSYOUT" Output Polarity		Diag.05

			      # 1+2 = Inverted
				2+3 = True ( NIM -ve standard )


LK3	Select "MBUSYOUT" Source			Diag.05

			      #	1 = Inputs
				2 = Expansion Header
			      * 3 = CPLD


LK25	Select "NCLKIN" TTL/NIM	Input			Diag.01

			      # 1+2 = TTL
				1+3 & 2+4 = NIM


LK15	Select Clock Source				Diag.02
LK16				
			      # 1+2 = External via PLL
				2+3 = EXT

									/cont:

					- 2 -


LK29	Select "NCONT<1-4>IN" TTL/NIM Inputs		Diag.04
LK30
LK31			      # 1+2 = TTL
LK32				1+3 & 2+4 = NIM


LK13	Select "NCONT<1-4>IN" Polarity			Diag.04
LK14
LK21			      * 1+2 = Inverted				
LK20			      	2+3 = Non-inverted


LK24	SELECT o/c "OCBUSYOUT" Output Polarity		Diag.05

			      #	1+2 = Inverted 
				2+3 = True


LK7	SELECT "TSPAREOUT" Source			Diag.07

				1+2 = Expansion Header
			      #	3+4 = CPLD
	NOTE : The label of this LK7 is incorrect on the PCB
	------

Remove to isolate JTAG connection to CPLD U9
LK8			 	TDI			Diag.06
LK11				TCK			Diag.06
LK10				TMS			Diag.06
LK9				TDO			Diag.06


Switch SW1	Select CPLD U9 option	1-16 HEX rotary		Diag.06

       - Simple Firmware for CCC Post-Production Testing

	   0       All 'Zeros' on outputs
	   1       12.5MHz clock on all single outputs,
		   12.5MHz counter on all busses
	   2       Same as 1. above, but with a slow count on delay
		   ( 2s-ish/period )
	   3-14    All 'Zeros'
	   15      All 'Ones' on outputs


Switch SW2	Select Clock	Auto / Xtal Only	Diag.01

       - to force-select stand-alone clock, slide SW2/1 to A = XTAL
       - to select any one external clock input, slide SW2/1 to 1 = AUTO
         NOTE : In this position, the clock MPX/PLL U31 will automatically
         ------ revert to the internal stand-alone clock if no external
                clock is present for more than 3 pulses.
                If this happens, the output clock will drift slowly to
                the 50MHz stand-alone frequency. The transition will
                be smooth and glitch-free, and can last up to 200 usec
                depending on the frequency difference.
                When the external clock re-starts, the MPX/PLL will
                switch back to this external clock.

	 LED INDICATORS : - DS1 yellow LED indicates an external clock
	 ----------------   is present
			  - DS2 red LED indicates the internal stand-alone
			    clock is selected by SW2
									/cont:

					- 3 -










				This version : MP-UCL, 08 Apr. 2009


                                Previous versions :    08 Apr. 2009
                                                       29 Mar. 2009
						       23 Mar. 2009
						       23 Feb. 2009
						       12 Jan. 2009
						       09 Jul. 2008
						       02 Jul. 2008
						       22 May  2008
                                                       19 May  2008
                                                       21 Apr. 2008