CALICE C+C PCB - PC INTERFACE SIGNALS ( OLD NUMBERS ) ===================================== MP-UCL, 23 February 2009 PL4/xx pins ( 50-pin DIL HEADER ) : ----------------------------------- 1) INPUTS on PC CONNECTOR : Differential LVDS --------------------------------------------- 3 LFTRIGINP+ Diff.LVDS Fast Trigger U24/3 LK5/3 4 LFTRIGINP- U24/2 LK6/3 2) INPUTS on PC CONNECTOR : LVTTL --------------------------------- 11 LFTRIGTINP LVTTL Fast Trigger U23/2 LK5+LK6/5 15 CONTTINP LVTTL Control U34/4 LK8/9 17 BUSYTINP LVTTL Busy U47/2 LK11/3 19 SPARETINP LVTTL Spare U47/2 LK22/1 21 JTAGSEL J-TAG Source Select U61/19+U63/1 ( LOW to select External PC J-TAG inputs ) 3) OUTPUTS on PC CONNECTOR : Differential LVDS ----------------------------------------------- 7 LFTRIGOUTP+ Diff.LVDS Fast Trigger U21/6 8 LFTRIGOUTP- U21/7 4) OUTPUTS on PC CONNECTOR : LVTTL ----------------------------------- 49 MCLKTOUTP Mixed Clock U8/3 13 LFTRIGTOUTP LVTTL Fast Trigger U25/7 <12-18> MCONT<1-4>TOUTP 4x LVTTL Control U34/11-14 <20-34> LBUSY<1-8>TOUTP 8x LVTTL Busy U42+43/12,14,16,18 <36-50> LSPARE<1-8>TOUTP 8x LVTTL Spare U53+54/12,14,16,18 5) Direct INPUTS/OUTPUTS to CPLD on PC CONNECTOR : LVTTL -------------------------------------------------------- <23-37> LCPLD-PC<0-7> 8x LVTTL U62/<37-42>,44,45 5) J-TAG Interface / etc. ------------------------- 39 EXTCK External J-TAG Clock input U61/15 41 EXTDI External J-TAG Data input U61/12 45 EXTDO External J-TAG Data output U61/3 43 EXTMS External J-TAG Mode Select input U61/13 21 JTAGSEL J-TAG Source Select U61/19+U63/1 ( LOW to select External PC J-TAG inputs ) /cont: - 2 - This version : MP-UCL, 23 Feb. 2009 Previous versions : 23 Feb. 2009 12 Jan. 2009 13 Aug. 2008 11 Aug. 2008 06 Aug. 2008 20 Jul. 2008 18 Jul. 2008 09 Jul. 2008 02 Jul. 2008 01 Jul. 2008 30 Jun. 2008 22 May 2008 19 May 2008 21 Apr. 2008