CALICE C+C PCB - LINKS SETUP ============================ Martin Postranecky, UCL, 08 APRIL 2009 * see PCB LAYOUT and LINKS : http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_pc3405m1_Top-Silk.pdf * see CIRCUIT DIAGRAMS : http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_pc3405m-Schematics.pdf NOTES: - DEFAULT SETTINGS indicated by '#' ------ - SETTINGS for STAND-ALONE TESTING indicated by '*' - NIM : -ve standard, terminated 50R, DC-coupled, ( unless otherwise described ) LK25 : select NIM / TTL / LVTTL single-ended clock input ( Diag. 01 ) LK25/1+2 # = TTL input LK25/1+3 & 2+4 = NIM input LK15 & LK16 : select CLOCK outputs ( Diag. 02 ) LK15/1+2 # = enables any selected clock to clock output sockets LK15/2+3 = enables an external, non-PLL-ed clock from socket NIM-3 = SK34/1 to the clock output sockets LK16/1+2 # = enables any selected clock to CPLD clock and on Expansion Header PL4/49 LK16/2+3 = enables an external, non-PLL-ed clock from socket NIM-3 = SK34/1 to CPLD clock and on Expansion Header PL4/49 LK22 & LK23 : select polarity of CLOCK NIM outputs ( Diag. 02 ) LK23/1+2 = NCLK2OUT = inverted LK23/2+3 # = NCLK2OUT = true ( NIM -ve standard ) LK22/1+2 = NCLK1OUT = inverted LK22/2+3 # = NCLK1OUT = true ( NIM -ve standard ) LK17 & LK18 : select FAST Low Latency ( asynchronous ) pulse output ( Diag. 03 ) To select ONE ONLY of the inputs to pass to the output sockets, insert shorting link on the appropriate pins of links LK17(+) and LK18(-): LK17/1A+B & LK18/1A+1B # = LVDS input from SMA-2A+B sockets or from HDMI-9 LK17/2A+B & LK18/2A+1B = LVDS input from Expansion Header LK17/3A+B & LK18/3A+1B = LVTTL input from Expansion Header LK17/4A+B & LK18/4A+1B * = LVTTL input from the on-board CPLD U9 LK17/5A+B & LK18/5A+1B = ECL input from SK32 LK<29-32> : select NIM / TTL / LVTTL single-ended CONTROL/DATA inputs ( Diag. 04 ) LK<29-32>/1+2 # = TTL LK<29-32>/1+3 & 2+4 = NIM /cont: - 2 - LK<13-14> & LK<20-21> : select POLARITY of the CONT<1-4>IN signals ( Diag. 04 ) LK<13-14> & LK<20-21>/1+2 * = inverted LK<13-14> & LK<20-21>/2+3 = non-inverted LK12 : select CONTROL / DATA output ( Diag. 04 ) To select ONE ( or more ) of the inputs to pass to the output sockets, insert shorting links on the appropriate pins of link LK12 ( NOTE POLARITY of selected inputs ) : LK12/1A+1B = LVDS input from SMA-3A+B sockets, or TTL / NIM inputs from NIM-8 socket, or LVDS input from HDMI-9 LK12/2A+2B = LVDS input from SMA-4A+B sockets, or TTL / NIM inputs from NIM-9 socket LK12/3A+3B = LVDS input from SMA-5A+B sockets, or TTL / NIM inputs from NIM-10 socket LK12/4A+4B = LVDS input from SMA-6A+B sockets, or TTL / NIM inputs from NIM-11 socket LK12/5A+5B = LVTTL input from the Expansion Heade LK12/6A+6B * = LVTTL input from the on-board CPLD U9 LK3 : select GENERAL ( BUSY ) output ( Diag. 03 ) To select ONE of the three inputs to pass to the output sockets, insert shorting link on the appropriate pins of link LK3 : LK3/1A+1B # = Overall 'OR' of 8x LVDS inputs from HDMI<1-8> = SK<1-8> sockets LK3/2A+2B = LVTTL input from the Expansion Header LK3/3A+3B * = LVTTL input from the on-board CPLD U9 LK24 : select polarity of TTL o/c GENERAL ( BUSY ) output ( Diag. 05 ) LK24/1+2 # = inverted LK24/2+3 = non-inverted LK27 : select POLARITY of the NIM GENERAL ( BUSY ) output ( Diag. 05 ) LK27/1+2 = NBUSYOUT = inverted LK27/2+3 # = NBUSYOUT = true ( NIM -ve standard ) LK7 : select SPARE / DATA output ( Diag. 07 ) To select ONE of the two inputs to pass to the output sockets, insert shorting link on the appropriate pins of link LK7 : LK7/1A+2A = LVTTL input from the Expansion Header LK7/1B+2B # = LVTTL input from the on-board CPLD U9 NOTE : THE LABEL OF THIS LINK LK7 IS INCORRECT ON PCB ----------------------------------------------------- /cont: - 3 - LK5/1+2 # = insert to enable U12 outputs ( Diag. 02 ) LK19/1+2 # = insert to enable U35 outputs ( Diag. 02 ) LK4/1+2 # = insert to enable U11 outputs ( Diag. 03 ) LK6/1+2 # = insert to enable U18 outputs ( Diag. 04 ) To isolate the JTAG connections to CPLD U9, remove these four links : ( Diag. 06 ) LK8 = TDI LK9 = TDO LK10 = TMS LK11 = TCK Switch SW1 ( Diag. 06 ) ========== A) Simple Firmware for CCC Post-Production Testing -------------------------------------------------- This makes use of the rotary switch SW1 to configure IO on the board in different ways : 0 Ins (ORed) to Outs. Busy out <= OR( in<8:1> ) Control out <= OR ( in<4:1> ) Spare out <= OR( in <8:1> ) Fast Trig out <= in RS232 out <= in Clock Delay <= 0 EXIO<0> <= Clock0 EXIO<1> <= Clock1 EXIO<2> <= Clock2 EXIO<3> <= Delayed Clock EXIO<4> <= ClockOn? EXIO<7:5> <= 2b000 Debug Headers: right <= left, bottom <= top 1 12.5MHz clock on all single outputs, 12.5MHz counter on all busses 2 Same as 1. above, but with a slow count on delay (2s-ish/period) 3-e All 'Zeros' f All 'Ones' on outputs https://twiki.cern.ch/twiki/bin/view/CALICE/ClockControlCard B) Firmware for Running ----------------------- Firmware allowing interfacing to a PC is developing. It makes use of the the RS232 port for connection to the PC. Details of the Register list : https://twiki.cern.ch/twiki/bin/view/CALICE/CCCRegisterList This firmware also contains some debug modes, selected using of the hex switch SW1 Hex-switch settings ------------------- 8 cont, ftrig, spare & busy <= 0, delay <= "000000" 9 cont, ftrig, spare & busy <= 1, delay <= "111111" A cont, ftrig, spare & busy <= clk, delay <= "010101" others All 'Zeros' /cont: - 4 - Switch SW2 ( Diag. 01 ) ---------- - to force-select stand-alone clock, slide SW2/1 to A = XTAL - to select any external clock input, slide SW2/1 to 1 = AUTO NOTE : In this position, the clock MPX/PLL U31 will automatically ------ revert to the internal stand-alone clock if no external clock is present for more than 3 pulses. If this happens, the output clock will drift slowly to the 50MHz stand-alone frequency. The transition will be smooth and glitch-free, and can last up to 200 usec depending on the frequency difference. When an external clock re-starts, the MPX/PLL will switch back to this external clock. LED INDICATORS : - DS1 yellow LED indicates an external clock ---------------- is present - DS2 red LED indicates the internal stand-alone clock is selected by SW2 This version : MP-UCL, 08 Apr. 2009 Previous versions : 08 Apr. 2009 29 Mar. 2009 23 Mar. 2009 25 Feb. 2009 24 Feb. 2009 23 Feb. 2009 20 Feb. 2009 22 Jan. 2009