-- generated by newgenasym Sat Apr 26 11:21:38 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc2g86\ is
    port (    
	\1a\:      IN     STD_LOGIC;    
	\1b\:      IN     STD_LOGIC;    
	\1y\:      OUT    STD_LOGIC;    
	\2a\:      IN     STD_LOGIC;    
	\2b\:      IN     STD_LOGIC;    
	\2y\:      OUT    STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74lvc2g86\;
