-- generated by genview  Tue Feb 29 18:16:29 2000

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DS90LV048A is
    port (    
	EN:        IN     STD_LOGIC;    
	\en*\:     IN     STD_LOGIC;    
	GND:       INOUT  STD_LOGIC;    
	\rin+\:    IN     STD_LOGIC_VECTOR (4 DOWNTO 1);    
	\rin-\:    IN     STD_LOGIC_VECTOR (4 DOWNTO 1);    
	ROUT:      OUT    STD_LOGIC_VECTOR (4 DOWNTO 1);    
	VCC:       INOUT  STD_LOGIC);
end DS90LV048A;
