// generated by newgenasym  Thu Dec 09 12:01:53 2010


module \rj45-2x8port  (\1la , \1lb , \1lc , \1ld , \1le , \1lf , \1lg , \1lh , \1ua , \1ub , \1uc , \1ud , \1ue ,
        \1uf , \1ug , \1uh , \2la , \2lb , \2lc , \2ld , \2le , \2lf , \2lg , \2lh , \2ua , \2ub ,
        \2uc , \2ud , \2ue , \2uf , \2ug , \2uh , \3la , \3lb , \3lc , \3ld , \3le , \3lf , \3lg ,
        \3lh , \3ua , \3ub , \3uc , \3ud , \3ue , \3uf , \3ug , \3uh , \4la , \4lb , \4lc , \4ld ,
        \4le , \4lf , \4lg , \4lh , \4ua , \4ub , \4uc , \4ud , \4ue , \4uf , \4ug , \4uh , \5la ,
        \5lb , \5lc , \5ld , \5le , \5lf , \5lg , \5lh , \5ua , \5ub , \5uc , \5ud , \5ue , \5uf ,
        \5ug , \5uh , \6la , \6lb , \6lc , \6ld , \6le , \6lf , \6lg , \6lh , \6ua , \6ub , \6uc ,
        \6ud , \6ue , \6uf , \6ug , \6uh , \7la , \7lb , \7lc , \7ld , \7le , \7lf , \7lg , \7lh ,
        \7ua , \7ub , \7uc , \7ud , \7ue , \7uf , \7ug , \7uh , \8la , \8lb , \8lc , \8ld , \8le ,
        \8lf , \8lg , \8lh , \8ua , \8ub , \8uc , \8ud , \8ue , \8uf , \8ug , \8uh , fx1, fx2,
        fx3, fx4, fx5, fx6, fx7, gnd1, gnd2, gnd3, gnd4, llla_a, llla_k,
        lllb_a, lllb_k, lllc_a, lllc_k, llld_a, llld_k, llle_a,
        llle_k, lllf_a, lllf_k, lllg_a, lllg_k, lllh_a, lllh_k,
        lrla_a, lrla_k, lrlb_a, lrlb_k, lrlc_a, lrlc_k, lrld_a,
        lrld_k, lrle_a, lrle_k, lrlf_a, lrlf_k, lrlg_a, lrlg_k,
        lrlh_a, lrlh_k, ulla_a, ulla_k, ullb_a, ullb_k, ullc_a,
        ullc_k, ulld_a, ulld_k, ulle_a, ulle_k, ullf_a, ullf_k,
        ullg_a, ullg_k, ullh_a, ullh_k, urla_a, urla_k, urlb_a,
        urlb_k, urlc_a, urlc_k, urld_a, urld_k, urle_a, urle_k,
        urlf_a, urlf_k, urlg_a, urlg_k, urlh_a, urlh_k);
    inout \1la ;
    inout \1lb ;
    inout \1lc ;
    inout \1ld ;
    inout \1le ;
    inout \1lf ;
    inout \1lg ;
    inout \1lh ;
    inout \1ua ;
    inout \1ub ;
    inout \1uc ;
    inout \1ud ;
    inout \1ue ;
    inout \1uf ;
    inout \1ug ;
    inout \1uh ;
    inout \2la ;
    inout \2lb ;
    inout \2lc ;
    inout \2ld ;
    inout \2le ;
    inout \2lf ;
    inout \2lg ;
    inout \2lh ;
    inout \2ua ;
    inout \2ub ;
    inout \2uc ;
    inout \2ud ;
    inout \2ue ;
    inout \2uf ;
    inout \2ug ;
    inout \2uh ;
    inout \3la ;
    inout \3lb ;
    inout \3lc ;
    inout \3ld ;
    inout \3le ;
    inout \3lf ;
    inout \3lg ;
    inout \3lh ;
    inout \3ua ;
    inout \3ub ;
    inout \3uc ;
    inout \3ud ;
    inout \3ue ;
    inout \3uf ;
    inout \3ug ;
    inout \3uh ;
    inout \4la ;
    inout \4lb ;
    inout \4lc ;
    inout \4ld ;
    inout \4le ;
    inout \4lf ;
    inout \4lg ;
    inout \4lh ;
    inout \4ua ;
    inout \4ub ;
    inout \4uc ;
    inout \4ud ;
    inout \4ue ;
    inout \4uf ;
    inout \4ug ;
    inout \4uh ;
    inout \5la ;
    inout \5lb ;
    inout \5lc ;
    inout \5ld ;
    inout \5le ;
    inout \5lf ;
    inout \5lg ;
    inout \5lh ;
    inout \5ua ;
    inout \5ub ;
    inout \5uc ;
    inout \5ud ;
    inout \5ue ;
    inout \5uf ;
    inout \5ug ;
    inout \5uh ;
    inout \6la ;
    inout \6lb ;
    inout \6lc ;
    inout \6ld ;
    inout \6le ;
    inout \6lf ;
    inout \6lg ;
    inout \6lh ;
    inout \6ua ;
    inout \6ub ;
    inout \6uc ;
    inout \6ud ;
    inout \6ue ;
    inout \6uf ;
    inout \6ug ;
    inout \6uh ;
    inout \7la ;
    inout \7lb ;
    inout \7lc ;
    inout \7ld ;
    inout \7le ;
    inout \7lf ;
    inout \7lg ;
    inout \7lh ;
    inout \7ua ;
    inout \7ub ;
    inout \7uc ;
    inout \7ud ;
    inout \7ue ;
    inout \7uf ;
    inout \7ug ;
    inout \7uh ;
    inout \8la ;
    inout \8lb ;
    inout \8lc ;
    inout \8ld ;
    inout \8le ;
    inout \8lf ;
    inout \8lg ;
    inout \8lh ;
    inout \8ua ;
    inout \8ub ;
    inout \8uc ;
    inout \8ud ;
    inout \8ue ;
    inout \8uf ;
    inout \8ug ;
    inout \8uh ;
    inout fx1;
    inout fx2;
    inout fx3;
    inout fx4;
    inout fx5;
    inout fx6;
    inout fx7;
    inout gnd1;
    inout gnd2;
    inout gnd3;
    inout gnd4;
    input llla_a;
    input llla_k;
    input lllb_a;
    input lllb_k;
    input lllc_a;
    input lllc_k;
    input llld_a;
    input llld_k;
    input llle_a;
    input llle_k;
    input lllf_a;
    input lllf_k;
    input lllg_a;
    input lllg_k;
    input lllh_a;
    input lllh_k;
    input lrla_a;
    input lrla_k;
    input lrlb_a;
    input lrlb_k;
    input lrlc_a;
    input lrlc_k;
    input lrld_a;
    input lrld_k;
    input lrle_a;
    input lrle_k;
    input lrlf_a;
    input lrlf_k;
    input lrlg_a;
    input lrlg_k;
    input lrlh_a;
    input lrlh_k;
    input ulla_a;
    input ulla_k;
    input ullb_a;
    input ullb_k;
    input ullc_a;
    input ullc_k;
    input ulld_a;
    input ulld_k;
    input ulle_a;
    input ulle_k;
    input ullf_a;
    input ullf_k;
    input ullg_a;
    input ullg_k;
    input ullh_a;
    input ullh_k;
    input urla_a;
    input urla_k;
    input urlb_a;
    input urlb_k;
    input urlc_a;
    input urlc_k;
    input urld_a;
    input urld_k;
    input urle_a;
    input urle_k;
    input urlf_a;
    input urlf_k;
    input urlg_a;
    input urlg_k;
    input urlh_a;
    input urlh_k;


    initial
        begin
        end

endmodule
