-- generated by newgenasym Thu Dec 09 12:01:53 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \rj45-2x8port\ is
    port (    
	\1la\:     INOUT  STD_LOGIC;    
	\1lb\:     INOUT  STD_LOGIC;    
	\1lc\:     INOUT  STD_LOGIC;    
	\1ld\:     INOUT  STD_LOGIC;    
	\1le\:     INOUT  STD_LOGIC;    
	\1lf\:     INOUT  STD_LOGIC;    
	\1lg\:     INOUT  STD_LOGIC;    
	\1lh\:     INOUT  STD_LOGIC;    
	\1ua\:     INOUT  STD_LOGIC;    
	\1ub\:     INOUT  STD_LOGIC;    
	\1uc\:     INOUT  STD_LOGIC;    
	\1ud\:     INOUT  STD_LOGIC;    
	\1ue\:     INOUT  STD_LOGIC;    
	\1uf\:     INOUT  STD_LOGIC;    
	\1ug\:     INOUT  STD_LOGIC;    
	\1uh\:     INOUT  STD_LOGIC;    
	\2la\:     INOUT  STD_LOGIC;    
	\2lb\:     INOUT  STD_LOGIC;    
	\2lc\:     INOUT  STD_LOGIC;    
	\2ld\:     INOUT  STD_LOGIC;    
	\2le\:     INOUT  STD_LOGIC;    
	\2lf\:     INOUT  STD_LOGIC;    
	\2lg\:     INOUT  STD_LOGIC;    
	\2lh\:     INOUT  STD_LOGIC;    
	\2ua\:     INOUT  STD_LOGIC;    
	\2ub\:     INOUT  STD_LOGIC;    
	\2uc\:     INOUT  STD_LOGIC;    
	\2ud\:     INOUT  STD_LOGIC;    
	\2ue\:     INOUT  STD_LOGIC;    
	\2uf\:     INOUT  STD_LOGIC;    
	\2ug\:     INOUT  STD_LOGIC;    
	\2uh\:     INOUT  STD_LOGIC;    
	\3la\:     INOUT  STD_LOGIC;    
	\3lb\:     INOUT  STD_LOGIC;    
	\3lc\:     INOUT  STD_LOGIC;    
	\3ld\:     INOUT  STD_LOGIC;    
	\3le\:     INOUT  STD_LOGIC;    
	\3lf\:     INOUT  STD_LOGIC;    
	\3lg\:     INOUT  STD_LOGIC;    
	\3lh\:     INOUT  STD_LOGIC;    
	\3ua\:     INOUT  STD_LOGIC;    
	\3ub\:     INOUT  STD_LOGIC;    
	\3uc\:     INOUT  STD_LOGIC;    
	\3ud\:     INOUT  STD_LOGIC;    
	\3ue\:     INOUT  STD_LOGIC;    
	\3uf\:     INOUT  STD_LOGIC;    
	\3ug\:     INOUT  STD_LOGIC;    
	\3uh\:     INOUT  STD_LOGIC;    
	\4la\:     INOUT  STD_LOGIC;    
	\4lb\:     INOUT  STD_LOGIC;    
	\4lc\:     INOUT  STD_LOGIC;    
	\4ld\:     INOUT  STD_LOGIC;    
	\4le\:     INOUT  STD_LOGIC;    
	\4lf\:     INOUT  STD_LOGIC;    
	\4lg\:     INOUT  STD_LOGIC;    
	\4lh\:     INOUT  STD_LOGIC;    
	\4ua\:     INOUT  STD_LOGIC;    
	\4ub\:     INOUT  STD_LOGIC;    
	\4uc\:     INOUT  STD_LOGIC;    
	\4ud\:     INOUT  STD_LOGIC;    
	\4ue\:     INOUT  STD_LOGIC;    
	\4uf\:     INOUT  STD_LOGIC;    
	\4ug\:     INOUT  STD_LOGIC;    
	\4uh\:     INOUT  STD_LOGIC;    
	\5la\:     INOUT  STD_LOGIC;    
	\5lb\:     INOUT  STD_LOGIC;    
	\5lc\:     INOUT  STD_LOGIC;    
	\5ld\:     INOUT  STD_LOGIC;    
	\5le\:     INOUT  STD_LOGIC;    
	\5lf\:     INOUT  STD_LOGIC;    
	\5lg\:     INOUT  STD_LOGIC;    
	\5lh\:     INOUT  STD_LOGIC;    
	\5ua\:     INOUT  STD_LOGIC;    
	\5ub\:     INOUT  STD_LOGIC;    
	\5uc\:     INOUT  STD_LOGIC;    
	\5ud\:     INOUT  STD_LOGIC;    
	\5ue\:     INOUT  STD_LOGIC;    
	\5uf\:     INOUT  STD_LOGIC;    
	\5ug\:     INOUT  STD_LOGIC;    
	\5uh\:     INOUT  STD_LOGIC;    
	\6la\:     INOUT  STD_LOGIC;    
	\6lb\:     INOUT  STD_LOGIC;    
	\6lc\:     INOUT  STD_LOGIC;    
	\6ld\:     INOUT  STD_LOGIC;    
	\6le\:     INOUT  STD_LOGIC;    
	\6lf\:     INOUT  STD_LOGIC;    
	\6lg\:     INOUT  STD_LOGIC;    
	\6lh\:     INOUT  STD_LOGIC;    
	\6ua\:     INOUT  STD_LOGIC;    
	\6ub\:     INOUT  STD_LOGIC;    
	\6uc\:     INOUT  STD_LOGIC;    
	\6ud\:     INOUT  STD_LOGIC;    
	\6ue\:     INOUT  STD_LOGIC;    
	\6uf\:     INOUT  STD_LOGIC;    
	\6ug\:     INOUT  STD_LOGIC;    
	\6uh\:     INOUT  STD_LOGIC;    
	\7la\:     INOUT  STD_LOGIC;    
	\7lb\:     INOUT  STD_LOGIC;    
	\7lc\:     INOUT  STD_LOGIC;    
	\7ld\:     INOUT  STD_LOGIC;    
	\7le\:     INOUT  STD_LOGIC;    
	\7lf\:     INOUT  STD_LOGIC;    
	\7lg\:     INOUT  STD_LOGIC;    
	\7lh\:     INOUT  STD_LOGIC;    
	\7ua\:     INOUT  STD_LOGIC;    
	\7ub\:     INOUT  STD_LOGIC;    
	\7uc\:     INOUT  STD_LOGIC;    
	\7ud\:     INOUT  STD_LOGIC;    
	\7ue\:     INOUT  STD_LOGIC;    
	\7uf\:     INOUT  STD_LOGIC;    
	\7ug\:     INOUT  STD_LOGIC;    
	\7uh\:     INOUT  STD_LOGIC;    
	\8la\:     INOUT  STD_LOGIC;    
	\8lb\:     INOUT  STD_LOGIC;    
	\8lc\:     INOUT  STD_LOGIC;    
	\8ld\:     INOUT  STD_LOGIC;    
	\8le\:     INOUT  STD_LOGIC;    
	\8lf\:     INOUT  STD_LOGIC;    
	\8lg\:     INOUT  STD_LOGIC;    
	\8lh\:     INOUT  STD_LOGIC;    
	\8ua\:     INOUT  STD_LOGIC;    
	\8ub\:     INOUT  STD_LOGIC;    
	\8uc\:     INOUT  STD_LOGIC;    
	\8ud\:     INOUT  STD_LOGIC;    
	\8ue\:     INOUT  STD_LOGIC;    
	\8uf\:     INOUT  STD_LOGIC;    
	\8ug\:     INOUT  STD_LOGIC;    
	\8uh\:     INOUT  STD_LOGIC;    
	FX1:       INOUT  STD_LOGIC;    
	FX2:       INOUT  STD_LOGIC;    
	FX3:       INOUT  STD_LOGIC;    
	FX4:       INOUT  STD_LOGIC;    
	FX5:       INOUT  STD_LOGIC;    
	FX6:       INOUT  STD_LOGIC;    
	FX7:       INOUT  STD_LOGIC;    
	GND1:      INOUT  STD_LOGIC;    
	GND2:      INOUT  STD_LOGIC;    
	GND3:      INOUT  STD_LOGIC;    
	GND4:      INOUT  STD_LOGIC;    
	LLLA_A:    IN     STD_LOGIC;    
	LLLA_K:    IN     STD_LOGIC;    
	LLLB_A:    IN     STD_LOGIC;    
	LLLB_K:    IN     STD_LOGIC;    
	LLLC_A:    IN     STD_LOGIC;    
	LLLC_K:    IN     STD_LOGIC;    
	LLLD_A:    IN     STD_LOGIC;    
	LLLD_K:    IN     STD_LOGIC;    
	LLLE_A:    IN     STD_LOGIC;    
	LLLE_K:    IN     STD_LOGIC;    
	LLLF_A:    IN     STD_LOGIC;    
	LLLF_K:    IN     STD_LOGIC;    
	LLLG_A:    IN     STD_LOGIC;    
	LLLG_K:    IN     STD_LOGIC;    
	LLLH_A:    IN     STD_LOGIC;    
	LLLH_K:    IN     STD_LOGIC;    
	LRLA_A:    IN     STD_LOGIC;    
	LRLA_K:    IN     STD_LOGIC;    
	LRLB_A:    IN     STD_LOGIC;    
	LRLB_K:    IN     STD_LOGIC;    
	LRLC_A:    IN     STD_LOGIC;    
	LRLC_K:    IN     STD_LOGIC;    
	LRLD_A:    IN     STD_LOGIC;    
	LRLD_K:    IN     STD_LOGIC;    
	LRLE_A:    IN     STD_LOGIC;    
	LRLE_K:    IN     STD_LOGIC;    
	LRLF_A:    IN     STD_LOGIC;    
	LRLF_K:    IN     STD_LOGIC;    
	LRLG_A:    IN     STD_LOGIC;    
	LRLG_K:    IN     STD_LOGIC;    
	LRLH_A:    IN     STD_LOGIC;    
	LRLH_K:    IN     STD_LOGIC;    
	ULLA_A:    IN     STD_LOGIC;    
	ULLA_K:    IN     STD_LOGIC;    
	ULLB_A:    IN     STD_LOGIC;    
	ULLB_K:    IN     STD_LOGIC;    
	ULLC_A:    IN     STD_LOGIC;    
	ULLC_K:    IN     STD_LOGIC;    
	ULLD_A:    IN     STD_LOGIC;    
	ULLD_K:    IN     STD_LOGIC;    
	ULLE_A:    IN     STD_LOGIC;    
	ULLE_K:    IN     STD_LOGIC;    
	ULLF_A:    IN     STD_LOGIC;    
	ULLF_K:    IN     STD_LOGIC;    
	ULLG_A:    IN     STD_LOGIC;    
	ULLG_K:    IN     STD_LOGIC;    
	ULLH_A:    IN     STD_LOGIC;    
	ULLH_K:    IN     STD_LOGIC;    
	URLA_A:    IN     STD_LOGIC;    
	URLA_K:    IN     STD_LOGIC;    
	URLB_A:    IN     STD_LOGIC;    
	URLB_K:    IN     STD_LOGIC;    
	URLC_A:    IN     STD_LOGIC;    
	URLC_K:    IN     STD_LOGIC;    
	URLD_A:    IN     STD_LOGIC;    
	URLD_K:    IN     STD_LOGIC;    
	URLE_A:    IN     STD_LOGIC;    
	URLE_K:    IN     STD_LOGIC;    
	URLF_A:    IN     STD_LOGIC;    
	URLF_K:    IN     STD_LOGIC;    
	URLG_A:    IN     STD_LOGIC;    
	URLG_K:    IN     STD_LOGIC;    
	URLH_A:    IN     STD_LOGIC;    
	URLH_K:    IN     STD_LOGIC);
end \rj45-2x8port\;
