-- generated by newgenasym Fri Feb 02 12:41:44 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc74a\ is
    generic (
        size:positive:= 1
            );
    port (    
	\cl*\:     IN     STD_LOGIC;    
	CLOCK:     IN     STD_LOGIC;    
	D:         IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	\pr*\:     IN     STD_LOGIC;    
	Q:         OUT    STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	\q*\:      OUT    STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end \74lvc74a\;
