`timescale 1 ns/1 ps

module \3v3  (g );
// generated by Concept HDL Direct Version 05.20-s025 (Special) 06-Apr-2000
// on Wed Sep 20 08:24:01 2000
// from cds_standard/3V3/sch_1

  parameter size = 1;

  inout [size-1:0] g;
  // global signal glbl.\3v3 ;

  wire [0:0] unnamed_1_replicate_3p_input;


  `ifdef VAN

  wire  \3v3 ;
  wire  page1_3v3;
  wire [size-1:0] page1_g;

  assign \3v3  = glbl.\3v3 ;
  assign page1_3v3 = \3v3 ;
  assign page1_g = g;

  `endif


  `ifdef VAN

  assign unnamed_1_replicate_3p_input [0:0] = glbl.\3v3 ;
  assign g [0:0] = unnamed_1_replicate_3p_input[0:0];

  `else
  alias_bit alias_inst1 (unnamed_1_replicate_3p_input[0:0], glbl.\3v3 );
  alias_bit alias_inst2 (g[0:0], unnamed_1_replicate_3p_input[0:0]);

  `endif

// begin instances 

endmodule // \3v3 (sch_1) 
