-- generated by newgenasym Thu Mar  4 14:20:54 2004

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \ics581-02\ is
    port (    
	CLK1:      OUT    STD_LOGIC;    
	CLK2:      OUT    STD_LOGIC;    
	CLK3:      IN     STD_LOGIC;    
	CLK4:      IN     STD_LOGIC;    
	DIV:       IN     STD_LOGIC;    
	FBIN:      OUT    STD_LOGIC;    
	GND1:      IN     STD_LOGIC;    
	GND2:      IN     STD_LOGIC;    
	INA:       IN     STD_LOGIC;    
	INB:       IN     STD_LOGIC;    
	OE0:       IN     STD_LOGIC;    
	OE1:       IN     STD_LOGIC;    
	S0:        IN     STD_LOGIC;    
	S1:        IN     STD_LOGIC;    
	VDD1:      IN     STD_LOGIC;    
	VDD2:      IN     STD_LOGIC);
end \ics581-02\;
