-- generated by newgenasym Thu Apr 10 14:16:16 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \rj45-ver2\ is
    port (    
	\1\:       INOUT  STD_LOGIC;    
	\2\:       INOUT  STD_LOGIC;    
	\3\:       INOUT  STD_LOGIC;    
	\4\:       INOUT  STD_LOGIC;    
	\5\:       INOUT  STD_LOGIC;    
	\6\:       INOUT  STD_LOGIC;    
	\7\:       INOUT  STD_LOGIC;    
	\8\:       INOUT  STD_LOGIC;    
	SHIELD1:   INOUT  STD_LOGIC;    
	SHIELD2:   INOUT  STD_LOGIC);
end \rj45-ver2\;
