-- generated by newgenasym Sat Jun 07 13:24:28 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DS90LV027A is
    port (    
	DIN1:      IN     STD_LOGIC;    
	DIN2:      IN     STD_LOGIC;    
	DOUT1:     OUT    STD_LOGIC;    
	\dout1*\:  OUT    STD_LOGIC;    
	DOUT2:     OUT    STD_LOGIC;    
	\dout2*\:  OUT    STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end DS90LV027A;
