-- generated by newgenasym Mon May 22 14:25:03 2000

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity resistor is
    generic (
        size:positive:= 1
            );
    port (    
	A:         IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	B:         IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end resistor;
