-- generated by newgenasym Wed Oct  2 10:46:13 2002

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DS90LV001 is
    port (    
	EN:        OUT    STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	\in+\:     IN     STD_LOGIC;    
	\in-\:     IN     STD_LOGIC;    
	NC:        IN     STD_LOGIC;    
	\out+\:    OUT    STD_LOGIC;    
	\out-\:    OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end DS90LV001;
