-- generated by newgenasym Wed Dec 08 14:41:46 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \ics527-01\ is
    port (    
	\2xdrive\: IN     STD_LOGIC;    
	CLK1:      OUT    STD_LOGIC;    
	CLK2:      OUT    STD_LOGIC;    
	DIV2:      IN     STD_LOGIC;    
	F0:        IN     STD_LOGIC;    
	F1:        IN     STD_LOGIC;    
	F2:        IN     STD_LOGIC;    
	F3:        IN     STD_LOGIC;    
	F4:        IN     STD_LOGIC;    
	F5:        IN     STD_LOGIC;    
	F6:        IN     STD_LOGIC;    
	FBIN:      IN     STD_LOGIC;    
	GND1:      IN     STD_LOGIC;    
	GND2:      IN     STD_LOGIC;    
	ICLK:      IN     STD_LOGIC;    
	OECLK2:    IN     STD_LOGIC;    
	\pdts*\:   IN     STD_LOGIC;    
	R0:        IN     STD_LOGIC;    
	R1:        IN     STD_LOGIC;    
	R2:        IN     STD_LOGIC;    
	R3:        IN     STD_LOGIC;    
	R4:        IN     STD_LOGIC;    
	R5:        IN     STD_LOGIC;    
	R6:        IN     STD_LOGIC;    
	S0:        IN     STD_LOGIC;    
	S1:        IN     STD_LOGIC;    
	VDD1:      IN     STD_LOGIC;    
	VDD2:      IN     STD_LOGIC);
end \ics527-01\;
