"==============================================================================================
#TITLE    'HELIX DRIVER PLD2: CONTROL LOGIC';
#ENGINEER 'Gil Nixon / John Lane / Dominic A Hayes / Matt Warren';
#COMPANY  'University College London';
#COMMENT  'Mach5 192/120-7YC';
"==============================================================================================
" MODS
"------
"08sep00 channel now decoded from register_data[23..20] instead of ab[19..16].
"17oct00 delay_write replaced by write_delay_unit.
"        writeb input to replace wr.
"30nov00 changed clocking on data_reg from /db_clk to db_clk - oaky? - MRMW
"        added hsd_mode to the statreg (bit3) - MRMW
"4dec00	added soft_trig input. added 'trigger' (= soft_trig OR trig) output to pld1. MRMW
"				This makes use of 2 spare bus lines ...
"			Trig_Sent stat bit now = (trigger AND /hsd_mode AND trig_sd) MRMW
"			Added channel 15 for broadcasting to all units - JBL/MRMW
"8dec00  added code for soft_test MRMW



"==============================================================================================






"==============================================================================================
"                                  PLD INPUT/OUTPUT DECLARATIONS
"==============================================================================================


"----------------------------------------------------------------------------------------------
" PLD-WIDE CLOCKS/RESETS etc.
"----------------------------
			INPUT	db_clk;
															
			INPUT	reset;                 "reset: (reset_cmd OR onres).    
														

		" FROM MASTER BOX
		"-----------------

         INPUT	pld_ck,
					trig,
					test;

					
	

		OUTPUT 	test_pulse[14..0];
      test_pulse = [pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck];


		OUTPUT trig_sd;
      trig_sd = pld_ck;


      OUTPUT   ser_load[14..0];
      ser_load[14..0] = [pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck,pld_ck];


		OUTPUT   nreset;
      nreset = pld_ck;






		" VME DATABUS
		"-------------

LOW_TRUE INPUT writeb;

			BIPUT	db[23..0]            "bi-directional i/o pins.
						ENABLED_BY dboe;
			NODE  dboe;                "db output enable.


"----------------------------------------------------------------------------------------------
" SPARES
"--------
			INPUT		read_feedback;		" for VME reads of the feedback reg IF it was on this pld.
			

         INPUT		spare[20..0]; " *** used 3 spare lines:
   
         INPUT    soft_test;
         NODE     test_sig;

         

         INPUT		soft_trig;

         OUTPUT	trigger; " *** this is the new 'trig' op to pld1
         trigger = pld_ck;

	
		INPUT		output_data_set;   "*** added _set   "Set board to Output Data to the Helix.  (pld_ck sync'd signal)
		OUTPUT	output_busy			 " high when busy sending
						DEFAULT_TO 0;
		

		

		

		INPUT	 hsd_mode;						"for setting mode to Serial Download



			
	
		INPUT	access_data;						"VME access to the sequence Data Register
 	

		
		INPUT	access_sl_sent;
		

		LOW_TRUE INPUT	nres;


				
		INPUT		access_tp_mask;				"VME access to the Test Pulse Mask Register

	   INPUT		tp_ck;				" From TEST pulse delay unit
													"  for clocking the test pulse ff

					
		INPUT		access_status;             "VME access to the Status Register

	
	   									
   	

"==============================================================================================