===================================================================== Specification of MVD ADC crates version 2.0 18-June-1999 Katsuo Tokushuku ===================================================================== 1. Crate size: -------------- Front: 9U - 340mm deep. 21 slots (The 21st slot is for power control module (wiener)) Bus: J1-J2 : ZEUS special backplane (as used in CAL,HES,GFLT...; detail will be discussed in section 4. J3 : We use standard J2 backplane. But no digital signals are sent through the J3. Back: J2-J3 : 6U NIKHEF boards 16 cm long, "in-line" with front boards. 2. Modules in the crate: ------------------------ Front : ------- Slot 1-4: (note that J2 pins for slot3-20 is special) 1 CPU 2 Interrupt cards 1 Latency conter : DESY/Italy Slot 5 : Free! Slot 6-17 max 12 ADC modules : Japan (typically 10 ADCMs) Slot 18-20 1 Slave C-C cards : UK + Spare slot. (In one of the crates, slot 16-17 are used for the C-C MASTER module ( 9U, 340mm long, double-width front panel ) ) Backside: --------- Slot 1: (J1) Bus arbitor (DESY or Tokyo) Slot 3: (J2) ZEUS bus terminator (Tokyo) Slot 6,8,...16 (J2,J3) Analogue receivers. (NIKHEF) (or 7,9,11...17, i.e. every other slot) Slot 20: (J2) ZEUS bus terminator (Tokyo) 3. Powers : ----------- +5 V 200A VME standard Digital (ADC + CPU + C&C) +-12V 6A VME standard Digital (CPU etc.) -5.2V 30A ECL (C+C, (ADC)) + 5V 30A Analogue (ADC,NIKHEF) - 5V 30A Analogue (ADC,NIKHEF) :N.B. I will check if power supplies fits in the space 4. Bus: ------- J1: Standard VME J2: row-b Standard VME J2: row-a,c slot 1,2 : user defined: i.e. open J2: row-a,c slot 3-20: See below J3: See below Front panel connection: Individual Clock signal from C+C to ADCM. ----------------------- a) on each C-C SLAVE, there is 16 connectors for ECL CLOCK 2-pin LEMO, 0B size, self-latching : ( LEMO EPG.0B.302.HLN for r/angle pcb socket ) where pin 1 = true ECL line pin 2 = complementary ( inverted ) ECL line on each ADCM, there is 1 connector for receving the ECL CLOCK. b) on the C-C MASTER module, there is a single connector for output of mixed & masked "RESET REQUEST*" line ( to be used as INTERRUPT if required ) : 1-pole LEMO coax, 00 size, self-latching ( TTL output, totem-pole output, negative logic ) c) on the C-C MASTER module, there is a single connector for input of "T-ERROR" from external source ( if required ) : 1-pole LEMO coax, 00 size, self-latching ( TTL input, negative logic ) =============== J2/P2 Connector Slots 3 to 20 =============== A B C 1 -5.2 VME -5.2 2 -5.2 VME -5.2 3 -5.2 VME -5.2 4 unused power line VME unused power line 5 -5.0(analog) VME -5.0(analog) 6 GND(-5) VME GND(-5) 7 +5.0(analog) VME +5.0(analog) 8 GND(+5) VME GND(+5) 9 User defined VME User defined 10 User defined VME User defined 11 User defined VME User defined 12 User defined VME Z0 EMPTY* (ADCM internal) 13 GND VME GND 14 GND VME GND 15 GND VME GND 16 User defined VME Z1 10.41 MHz clock 17 User defined VME Z2 BUSY* (negative) 18 User defined VME Z3 FATAL ERROR* (negative) 19 User defined VME Z4 Reset Request*(negative) 20 User defined VME Z5 Reset* (negative) 21 User defined VME Z6 Abort 22 User defined VME Z7 Accept 23 User defined VME Z8 A1 24 User defined VME Z9 A0 25 User defined VME Z10 D7 26 User defined VME Z11 D6 27 User defined VME Z12 D5 28 User defined VME Z13 D4 29 User defined VME Z14 D3 30 User defined VME Z15 D2 31 User defined VME Z16 D1 32 User defined VME Z17 D0 Z0 - Z17 is a private bus. It will be terminated at the cards and not at the backplane. (--> backside at slot 3 and 20) Z0-Z17 : TTL bus. ADC internal: ------------- Z0: EMPTY* (netagive) : (The signal can be used for DAQ-interrupt board as the source of SLT interrupt) ADCM-->C&C : ------------- Z2: Busy (negative logic) Z3: Fatal Error (negative logic) This signal can be connected to the toGFLT Fatal error line. Z4: Reset Request (negative logic) This signal is used for error recovery scheme C&C -->ADCM : ------------- Z1: TTL Clock: to indicate the timing to latch Z6-Z17 (Totenpole output) Z5: Reset (negative logic) : Open corrector output. Note that ADCM can also drive this line (via VME command) Z6: Abort flag (Totenpole output) Z7: Accept flag (Totenpole output) Z8-Z9: Address for D0-D7 (A0-A1) (Totenpole output) Z10-Z17: Trigger data: (D0-D7) (Totenpole output) The first clock cycle with Accept flag (A0,1=00): Readout Type The second clock cycle with Accept flag (A0,1=01): FLTN The third clock cycle with Accept flag (A0,1=10): GBCN =============== J3/P3 Connector Slots 1 to 20 =============== A B C 1 Digital GND +5V Analog Digital GND 2 DSTR ch1 Analog GND DSTR ch1* 3 DSTR ch2 N.D. DSTR ch2* 4 Digital GND bus00 Digital GND 5 DSTR ch3 bus01 DSTR ch3* 6 DSTR ch4 bus02 DSTR ch4* 7 Digital GND bus03 Digital GND 8 DSTR ch5 bus04 DSTR ch5* 9 DSTR ch6 bus05 DSTR ch6* 10 Digital GND bus06 Digital GND 11 DSTR ch7 bus07 DSTR ch7* 12 DSTR ch8 Analog GND DSTR ch8* 13 Digital GND +5V Analog Digital GND 14 Digital GND bus08 Digital GND 15 Analog GND bus09 Analog GND 16 A.OUT ch1 bus10 Analog GND 17 A.GROUND ch1 bus11 Analog GND 18 A.OUT ch2 bus12 Analog GND 19 A.GROUND ch2 bus13 Analog GND 20 A.OUT ch3 bus14 Analog GND 21 A.GROUND ch3 bus15 Analog GND 22 A.OUT ch4 Analog GND Analog GND 23 A.GROUND ch4 bus16 Analog GND 24 A.OUT ch5 bus17 Analog GND 25 A.GROUND ch5 bus18 Analog GND 26 A.OUT ch6 bus19 Analog GND 27 A.GROUND ch6 bus20 Analog GND 28 A.OUT ch7 bus21 Analog GND 29 A.GROUND ch7 bus22 Analog GND 30 A.OUT ch8 bus23 Analog GND 31 A.GROUND ch8 Analog GND Analog GND 32 Analog GND +5V Analog Analog GND Analog out is single ended signal, 0-+2V into 50 Ohms. DSTR and DSTR*_ is a differential signal pair of +/- 300mV into 100 Ohms. bus 00-23 are not used.