FIN_CLK_v01 Project Status (07/21/2010 - 18:16:31)
Project File: FIN_CLK_v01.ise Implementation State: Programming File Not Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc3s400-4pq208
  • Warnings:
70 Warnings
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 75 7,168 1%  
Number of 4 input LUTs 131 7,168 1%  
Number of occupied Slices 98 3,584 2%  
    Number of Slices containing only related logic 98 98 100%  
    Number of Slices containing unrelated logic 0 98 0%  
Total Number of 4 input LUTs 175 7,168 2%  
    Number used as logic 131      
    Number used as a route-thru 44      
Number of bonded IOBs 50 141 35%  
    IOB Master Pads 9      
    IOB Slave Pads 9      
Number of BUFGMUXs 2 8 25%  
Number of RPM macros 2      
Average Fanout of Non-Clock Nets 2.80      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jul 21 18:15:23 2010057 Warnings2 Infos
Translation ReportCurrentWed Jul 21 18:15:37 2010000
Map ReportCurrentWed Jul 21 18:15:51 2010010 Warnings2 Infos
Place and Route ReportCurrentWed Jul 21 18:16:11 201003 Warnings4 Infos
Power Report     
Post-PAR Static Timing ReportCurrentWed Jul 21 18:16:18 2010003 Infos
Bitgen ReportCurrentWed Jul 21 18:16:29 2010001 Info
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 07/21/2010 - 18:50:29