MCP_MAINv02 Project Status
Project File:	MCP_MAINv02.ise	Current State:	Programming File Generated
Module Name:	TOP	Errors:	No Errors
Target Device:	xc2vp2-5fg256	Warnings:	279 Warnings
Product Version:	ISE 10.1.03 - Foundation Simulator	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

MCP_MAINv02 Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	653	2,816	23%
Number of 4 input LUTs	778	2,816	27%
Logic Distribution
Number of occupied Slices	702	1,408	49%
Number of Slices containing only related logic	702	702	100%
Number of Slices containing unrelated logic	0	702	0%
Total Number of 4 input LUTs	961	2,816	34%
Number used as logic	778
Number used as a route-thru	183
Number of bonded IOBs
Number of bonded	102	140	72%
IOB Master Pads	11
IOB Slave Pads	11
Number of BUFGMUXs	7	16	43%
Number of DCMs	1	4	25%
Number of GTs	1	4	25%
Number of RPM macros	2

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Jan 4 17:15:47 2011	0	249 Warnings	37 Infos
Translation Report	Current	Tue Jan 4 17:16:00 2011	0	1 Warning	0
Map Report	Current	Tue Jan 4 17:16:19 2011	0	26 Warnings	6 Infos
Place and Route Report	Current	Tue Jan 4 17:16:51 2011	0	3 Warnings	1 Info
Static Timing Report	Current	Tue Jan 4 17:16:57 2011	0	1 Warning	2 Infos
Bitgen Report	Current	Tue Jan 4 17:17:05 2011	0	2 Warnings	1 Info

Date Generated: 01/06/2011 - 15:01:36