MCP_TARGETv03 Project Status (05/04/2010 - 13:18:35)
Project File: MCP_TARGETv03.ise Current State: Programming File Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc3s400-4pq208
  • Warnings:
284 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
MCP_TARGETv03 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,457 7,168 20%  
Number of 4 input LUTs 1,511 7,168 21%  
Logic Distribution     
Number of occupied Slices 1,459 3,584 40%  
    Number of Slices containing only related logic 1,459 1,459 100%  
    Number of Slices containing unrelated logic 0 1,459 0%  
Total Number of 4 input LUTs 2,563 7,168 35%  
    Number used as logic 1,511      
    Number used as a route-thru 1,052      
Number of bonded IOBs
Number of bonded 111 141 78%  
    IOB Master Pads 4      
    IOB Slave Pads 4      
Number of RAMB16s 9 16 56%  
Number of BUFGMUXs 5 8 62%  
Number of RPM macros 3      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue May 4 13:17:35 20100268 Warnings38 Infos
Translation ReportCurrentTue May 4 13:17:45 2010000
Map ReportCurrentTue May 4 13:17:56 201009 Warnings2 Infos
Place and Route ReportCurrentTue May 4 13:18:18 201007 Warnings0
Static Timing ReportCurrentTue May 4 13:18:24 2010002 Infos
Bitgen ReportCurrentTue May 4 13:18:35 201001 Warning1 Info

Date Generated: 05/04/2010 - 13:18:35