<a large amount of info needs to be added here soon>
The communication between the CCC with the LDA (or ODR or DIF) is preferably via the HDMI outputs.
The CCC pinouts match those of the LDA and the board is designed to be used as a pseudo-LDA for stand-alone DIF testing (using USB for readout).
A subset of the standard LDA link (detailed in <zzz ref:Marc>) is used by the CCC (see table zzz)
|
HDMI Pair |
CCC Name |
CCC Function |
Pins(+,-) |
Coupling |
|---|---|---|---|---|
|
CLOCK_L2D |
CLOCK_OUT |
Clock |
1,3 |
AC |
|
ASYNC_L2D |
ASYNC_OUT |
Asynchronous signal |
4,6 |
AC |
|
DATA_L2D |
CMD_OUT |
Subset of commands. No data |
15,16 |
AC |
|
DATA_D2L |
n/a (CMD_RET zzz) |
Unused |
7,9 |
AC |
|
GEN_D2L |
GEN_IN |
General purpose, hardware OR available |
10,12 |
zzz |
|
Shields |
|
Terminated zzz |
|
|
Table zzz. CCC HDMI connector signals
For clock and control we only foresee this link being used for a limited number of commands, mainly the 'trainsync' SYNCCMD. This command sets-up the the synchronisation of all the front-ends.
|
Type/Command |
Description |
|---|---|
|
SYNCCMD/TRAINSYNC |
Synchronise all frontends to the coming train phase |
|
SYNCCMD/RUNSTART |
All start taking data at the same time. |
|
COMMAND/zzz |
zzz can't actually think of anything to go here |
Table zzz. CCC commands
To allow the CCC to be plugged directly into a DIF without an LDA present, and to allow the CCC to send synchronous commands to a DIF, the CMD_OUT signals must be compatible with LDA DATA_L2D signaling (8b/10b + CLINK zzz protocol). To avoid implementing an entire LDA link encoder block in the CPLD, a simplified 8b/10b encoder is used with hardwired sequences as needed.