S3ESK_TOP Project Status
Project File: s3esk_top.ise Current State: Programming File Generated
Module Name: s3esk_top
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
16 Warnings
Product Version: ISE 9.2.04i
  • Updated:
Thu Oct 16 12:47:32 2008
 
S3ESK_TOP Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 2,252 9,312 24%  
    Number used as Flip Flops 2,251      
    Number used as Latches 1      
Number of 4 input LUTs 3,559 9,312 38%  
Logic Distribution     
Number of occupied Slices 2,564 4,656 55%  
    Number of Slices containing only related logic 2,564 2,564 100%  
    Number of Slices containing unrelated logic 0 2,564 0%  
Total Number of 4 input LUTs 3,784 9,312 40%  
Number used as logic 3,559      
Number used as a route-thru 221      
Number used as Shift registers 4      
Number of bonded IOBs 29 232 12%  
    IOB Flip Flops 8      
    IOB Master Pads 6      
    IOB Slave Pads 6      
Number of Block RAMs 9 20 45%  
Number of GCLKs 2 24 8%  
Total equivalent gate count for design 632,655      
Additional JTAG gate count for IOBs 1,392      
 
Performance Summary
Final Timing Score: 87180 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: 1 Failing Constraint    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation ReportCurrentThu Oct 16 10:46:31 2008000
Map ReportCurrentThu Oct 16 10:46:57 200806 Warnings4 Infos
Place and Route ReportCurrentThu Oct 16 10:49:43 200807 Warnings0
Static Timing ReportCurrentThu Oct 16 10:49:54 2008002 Infos
Bitgen ReportCurrentThu Oct 16 10:50:10 200803 Warnings0