Xilinx Design Summary

SINGLE3E Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	2,082	9,312	22%
Number used as Flip Flops	2,081
Number used as Latches	1
Number of 4 input LUTs	3,585	9,312	38%
Logic Distribution
Number of occupied Slices	2,502	4,656	53%
Number of Slices containing only related logic	2,502	2,502	100%
Number of Slices containing unrelated logic	0	2,502	0%
Total Number of 4 input LUTs	3,631	9,312	38%
Number used as logic	3,585
Number used as a route-thru	43
Number used as Shift registers	3
Number of bonded IOBs	173	232	74%
IOB Flip Flops	34
Number of Block RAMs	9	20	45%
Number of GCLKs	2	24	8%
Total equivalent gate count for design	630,581
Additional JTAG gate count for IOBs	8,304

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met