#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
#install: /unix/local/synopsys/synplicity/fpga_c200906
#OS: Linux 
#Hostname: pc140.hep.ucl.ac.uk

#Implementation: rev_1

#Tue Mar 16 10:30:26 2010

$ Start of Compile
#Tue Mar 16 10:30:26 2010

$ Running Xilinx xtclsh. See log file:
@N: : xflow.log | 
#Tue Mar 16 10:30:26 2010

Synopsys HDL Compiler, version comp400rc, Build 019R, built May 19 2009
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved

/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.ngc
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9_0.ngc
/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Encode.edn
/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Decode.edn
/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Decode_decode_8b10b_xst_1.ndf
/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf
@N: : gig_eth_mac_v8_3.ngc | Reading NGC/NGO file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.ngc" for timing estimation.
Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Reading design
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.n
gc ...
WARNING:NetListWriters:298 - No output is written to gig_eth_mac_v8_3.xncf,
   ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus U0/MANIFGEN.MANAGEN/CONF/RX1_OUT(31 : 0)
   on block gig_eth_mac_v8_3_gmac_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/TXGEN/TX_SM_FD/Madd_IFG_COUNT_addsub0000_cy(5 : 2) on block
   gig_eth_mac_v8_3_gmac_gen_1 is not reconstructed, because there are some
   missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/TXGEN/TX_SM_FD/Msub_IFG_COUNT_addsub0001_cy(6 : 3) on block
   gig_eth_mac_v8_3_gmac_gen_1 is not reconstructed, because there are some
   missing bus signals.
  finished :Prep
Writing EDIF netlist file
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.n
df ...
ngc2edif: Total memory usage is 71108 kilobytes

@N: : gig_eth_mac_v8_3.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.ndf"
EDIF to SRS Translation Completed
###########################################################]
@N: : gig_eth_mac_v8_3.ngc | Reading NGC/NGO file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.ngc" for timing estimation.
Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Reading design
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.n
gc ...
WARNING:NetListWriters:298 - No output is written to gig_eth_mac_v8_3.xncf,
   ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus U0/MANIFGEN.MANAGEN/CONF/RX1_OUT(31 : 0)
   on block gig_eth_mac_v8_3_gmac_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/TXGEN/TX_SM_FD/Madd_IFG_COUNT_addsub0000_cy(5 : 2) on block
   gig_eth_mac_v8_3_gmac_gen_1 is not reconstructed, because there are some
   missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/TXGEN/TX_SM_FD/Msub_IFG_COUNT_addsub0001_cy(6 : 3) on block
   gig_eth_mac_v8_3_gmac_gen_1 is not reconstructed, because there are some
   missing bus signals.
  finished :Prep
Writing EDIF netlist file
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.n
df ...
ngc2edif: Total memory usage is 71104 kilobytes

@N: : gig_eth_mac_v8_3.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_mac_v8_3.ndf"
EDIF to SRS Translation Completed
###########################################################]
@N: : gig_eth_pcs_pma_v9_0.ngc | Reading NGC/NGO file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9_0.ngc" for timing estimation.
Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Reading design
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9
_0.ngc ...
WARNING:NetListWriters:298 - No output is written to gig_eth_pcs_pma_v9_0.xncf,
   ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus
   U0/HAS_AUTO_NEG.AUTO_NEGOTIATION/RX_CONFIG_SNAPSHOT(15 : 0) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/HAS_AUTO_NEG.AUTO_NEGOTIATION/MR_LP_ADV_ABILITY_INT(16 : 6) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/TRANSMITTER/CODE_GRP_mux0007(7 : 3)
   on block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because
   there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/TRANSMITTER/TXDATA_mux0003(7 : 0) on
   block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there
   are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/HAS_MANAGEMENT.MDIO/AN_ADV_REG(15 :
   5) on block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because
   there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/HAS_MANAGEMENT.MDIO/AN_NP_TX_REG(15 :
   0) on block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because
   there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/USE_TBI.PCS_OUTPUT/BASEX.RECLOCK_RX_DATA/NEXT_WR_ADDR(3 : 0) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/USE_TBI.PCS_OUTPUT/ENCODER/ENCODER_OUTPUT(12 : 0) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
  finished :Prep
Writing EDIF netlist file
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9
_0.ndf ...
ngc2edif: Total memory usage is 69120 kilobytes

@N: : gig_eth_pcs_pma_v9_0.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9_0.ndf"
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxnotintable of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port userclk2 of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port userclk of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port txbuferr of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port dcm_locked of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port basex_or_sgmii of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxrundisp of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxcharisk of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxdisperr of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxchariscomma of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
EDIF to SRS Translation Completed
###########################################################]
@N: : gig_eth_pcs_pma_v9_0.ngc | Reading NGC/NGO file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9_0.ngc" for timing estimation.
Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Release 11.4 - ngc2edif L.68 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Reading design
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9
_0.ngc ...
WARNING:NetListWriters:298 - No output is written to gig_eth_pcs_pma_v9_0.xncf,
   ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus
   U0/HAS_AUTO_NEG.AUTO_NEGOTIATION/RX_CONFIG_SNAPSHOT(15 : 0) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/HAS_AUTO_NEG.AUTO_NEGOTIATION/MR_LP_ADV_ABILITY_INT(16 : 6) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/TRANSMITTER/CODE_GRP_mux0007(7 : 3)
   on block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because
   there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/TRANSMITTER/TXDATA_mux0003(7 : 0) on
   block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there
   are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/HAS_MANAGEMENT.MDIO/AN_ADV_REG(15 :
   5) on block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because
   there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/HAS_MANAGEMENT.MDIO/AN_NP_TX_REG(15 :
   0) on block gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because
   there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/USE_TBI.PCS_OUTPUT/BASEX.RECLOCK_RX_DATA/NEXT_WR_ADDR(3 : 0) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
   U0/USE_TBI.PCS_OUTPUT/ENCODER/ENCODER_OUTPUT(12 : 0) on block
   gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1 is not reconstructed, because there are
   some missing bus signals.
  finished :Prep
Writing EDIF netlist file
/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9
_0.ndf ...
ngc2edif: Total memory usage is 69120 kilobytes

@N: : gig_eth_pcs_pma_v9_0.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/coreip/gig_eth_pcs_pma_v9_0.ndf"
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxnotintable of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port userclk2 of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port userclk of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port txbuferr of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port dcm_locked of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port basex_or_sgmii of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxrundisp of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxcharisk of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxdisperr of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
@W: : gig_eth_pcs_pma_v9_0.ndf(18132) | Input port rxchariscomma of gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2 is unused
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Encode.edn | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Encode.edn"
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Encode.edn | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Encode.edn"
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Decode.edn | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Decode.edn"
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Decode.edn | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Decode.edn"
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Decode_decode_8b10b_xst_1.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Decode_decode_8b10b_xst_1.ndf"
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Decode_decode_8b10b_xst_1.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Decode_decode_8b10b_xst_1.ndf"
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf"
@W: : S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf(5369) | Input port force_code of S3_2000_8B10B_Encode_encode_8b10b_xst_1 is unused
@W: : S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf(5369) | Input port force_code_b of S3_2000_8B10B_Encode_encode_8b10b_xst_1 is unused
EDIF to SRS Translation Completed
###########################################################]
@N: : S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf | Reading EDIF file "/home/warren/calicedaq/LDA/firmware/source/main/coregen/S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf"
@W: : S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf(5369) | Input port force_code of S3_2000_8B10B_Encode_encode_8b10b_xst_1 is unused
@W: : S3_2000_8B10B_Encode_encode_8b10b_xst_1.ndf(5369) | Input port force_code_b of S3_2000_8B10B_Encode_encode_8b10b_xst_1 is unused
EDIF to SRS Translation Completed
###########################################################]
@N:CD720 : std.vhd(123) | Setting time resolution to ns
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/ll_fifo_pkg.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/fifo_utils.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/DRAM/DRAM_fifo_pkg.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/DRAM/RAM_64nX1.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/DRAM/DRAM_macro.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/DRAM/DRAM_fifo.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_fifo_pkg.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_macro.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S8_S72.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S8_S144.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S16_S144.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S18_S72.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S36_S72.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S36_S144.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S72_S72.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S72_S144.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_S144_S144.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/BRAM/BRAM_fifo.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/ll_fifo_DRAM.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/ll_fifo_BRAM.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/locallink_fifo/ll_fifo.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/PCK_CRC16_D16.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/version.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/serdes_pkg.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/xilinx_encode_8b10b_wrapper.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/xilinx_decode_8b10b_wrapper.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/serial_delay.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/sipo_oversamp.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/data_recovery.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/measure_delay.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/piso.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/link_sm.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_serdes.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_protocol_sm.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_dif_links_reg.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_module.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_dif_links.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/gigethernet_xilinx.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/gigethernet_host_statemachine.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/domain_crossing.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_reg_sm.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_dif_sm.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_dif_memory.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_main_sm.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_internal_registers.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_read_serial.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/packetgen_sm.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/dif_packet.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_mac.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_mac_shim.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_mac_block.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_packetgen.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/tx_arbiter.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/rx_arbiter.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/gigethernet_host_shim.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/pause_ctrl.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/rx_client_fifo.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/tx_client_fifo.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_spi_core.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_spi_state.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/lda_spi_slave.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/single_port.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fast_decoder.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/HeaderGen.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/ll_mux2_rx_simple.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/ll_mux_ctrl_simple_rtl.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/ethernet_usb_mux.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/ll_mux_top_simple_rtl.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/md2.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/measure_delay_slr.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/ll_mux_top_struct.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/ll_mux_ctrl_rtl.vhd"
@I:: "/home/warren/calicedaq/LDA/firmware/source/main/fifo_mux/ll_mux2_rx.vhd"
VHDL syntax check successful!
Options changed - recompiling
@N:CD630 : md2.vhd(33) | Synthesizing work.md2.rtl 
@W:CD434 : md2.vhd(1630) | Signal dif_data_tx_underrun_i in the sensitivity list is not used in the process
@W:CD638 : md2.vhd(744) | Signal pma_dcm_clk0_i is undriven 
@W:CD638 : md2.vhd(752) | Signal serial_id_i is undriven 
@W:CD638 : md2.vhd(753) | Signal serial_id_done_i is undriven 
@N:CD630 : lda_spi_slave.vhd(57) | Synthesizing work.lda_spi_slave.rtl 
@N:CD630 : lda_spi_state.vhd(55) | Synthesizing work.lda_spi_state.rtl 
@N:CD231 : lda_spi_state.vhd(87) | Using onehot encoding for type spi_states (idle="100000")
Post processing for work.lda_spi_state.rtl
@W:CL169 : lda_spi_state.vhd(114) | Pruning Register tx_data_en_del_i  
@W:CL170 : lda_spi_state.vhd(160) | Pruning bit <9> of cmd_i(9 downto 0) - not in use ... 
@W:CL170 : lda_spi_state.vhd(160) | Pruning bit <8> of cmd_i(9 downto 0) - not in use ... 
@W:CL170 : lda_spi_state.vhd(160) | Pruning bit <5> of cmd_i(9 downto 0) - not in use ... 
@W:CL170 : lda_spi_state.vhd(160) | Pruning bit <4> of cmd_i(9 downto 0) - not in use ... 
@N:CD630 : lda_spi_core.vhd(30) | Synthesizing work.lda_spi_core.rtl 
Post processing for work.lda_spi_core.rtl
Post processing for work.lda_spi_slave.rtl
@N:CD630 : tx_client_fifo.vhd(104) | Synthesizing work.tx_client_fifo.rtl 
@N:CD231 : tx_client_fifo.vhd(141) | Using onehot encoding for type rd_state_typ (idle_s="100000000")
@N:CD231 : tx_client_fifo.vhd(144) | Using onehot encoding for type wr_state_typ (wait_s="1000")
@W:CD604 : tx_client_fifo.vhd(347) | OTHERS clause is not synthesized 
@W:CD326 : tx_client_fifo.vhd(1314) | Port dopa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD326 : tx_client_fifo.vhd(1314) | Port doa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD326 : tx_client_fifo.vhd(1337) | Port dopa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD326 : tx_client_fifo.vhd(1337) | Port doa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD638 : tx_client_fifo.vhd(194) | Signal rd_retran_frame_tog is undriven 
@W:CD638 : tx_client_fifo.vhd(195) | Signal wr_retran_frame_tog is undriven 
@W:CD638 : tx_client_fifo.vhd(196) | Signal wr_retran_frame_sync is undriven 
@W:CD638 : tx_client_fifo.vhd(197) | Signal wr_retran_frame_delay is undriven 
@W:CD638 : tx_client_fifo.vhd(202) | Signal wr_retransmit_frame is undriven 
@W:CD638 : tx_client_fifo.vhd(217) | Signal rd_drop_frame is undriven 
@W:CD638 : tx_client_fifo.vhd(218) | Signal rd_retransmit is undriven 
@W:CD638 : tx_client_fifo.vhd(228) | Signal rd_col_window_expire is undriven 
@W:CD638 : tx_client_fifo.vhd(229) | Signal rd_col_window_pipe is undriven 
@W:CD638 : tx_client_fifo.vhd(230) | Signal wr_col_window_pipe is undriven 
@W:CD638 : tx_client_fifo.vhd(234) | Signal rd_slot_timer is undriven 
@W:CD638 : tx_client_fifo.vhd(235) | Signal wr_col_window_expire is undriven 
@W:CD638 : tx_client_fifo.vhd(237) | Signal rd_idle_state is undriven 
Post processing for work.tx_client_fifo.rtl
@W:CL169 : tx_client_fifo.vhd(1082) | Pruning Register rd_eof_reg  
@N:CD630 : ll_mux_top_struct.vhd(39) | Synthesizing work.ll_mux_top.struct 
@N:CD630 : ll_mux_ctrl_rtl.vhd(16) | Synthesizing work.ll_arbiter.rtl 
@N:CD231 : ll_mux_ctrl_rtl.vhd(33) | Using onehot encoding for type arbiter_states (idle_state="100000000")
Post processing for work.ll_arbiter.rtl
@N:CD630 : ll_mux2_rx.vhd(14) | Synthesizing work.ll_mux2_rx.rtl 
@N:CD231 : ll_mux2_rx.vhd(42) | Using onehot encoding for type machine_state (at_zero_state="10")
@N:CD364 : ll_mux2_rx.vhd(73) | Removed redundant assignment
@N:CD364 : ll_mux2_rx.vhd(74) | Removed redundant assignment
@N:CD364 : ll_mux2_rx.vhd(75) | Removed redundant assignment
@N:CD364 : ll_mux2_rx.vhd(76) | Removed redundant assignment
Post processing for work.ll_mux2_rx.rtl
Post processing for work.ll_mux_top.struct
@N:CD630 : lda_mac_block.vhd(34) | Synthesizing work.lda_mac_block.rtl 
@N:CD630 : lda_mac.vhd(40) | Synthesizing work.lda_mac.rtl 
@W:CD638 : lda_mac.vhd(224) | Signal rx_data_del_i is undriven 
@W:CD638 : lda_mac.vhd(225) | Signal rx_data_valid_del_i is undriven 
@W:CD638 : lda_mac.vhd(226) | Signal rx_start_frame_del_i is undriven 
@N:CD630 : dif_packet.vhd(33) | Synthesizing work.dif_packet.rtl 
@N:CD231 : dif_packet.vhd(68) | Using onehot encoding for type rx_state_types (idle="10000")
@N:CD231 : dif_packet.vhd(70) | Using onehot encoding for type tx_state_types (idle="100000000")
Post processing for work.dif_packet.rtl
@W:CL169 : dif_packet.vhd(128) | Pruning Register rx_saved_crc_i(15 downto 0)  
@N:CD630 : lda_mac_shim.vhd(48) | Synthesizing work.lda_mac_shim.rtl 
@N:CD231 : lda_mac_shim.vhd(87) | Using onehot encoding for type tx_state_types (idle="10000")
@N:CD231 : lda_mac_shim.vhd(102) | Using onehot encoding for type rx_state_types (idle="10000")
@N:CD364 : lda_mac_shim.vhd(314) | Removed redundant assignment
@N:CD364 : lda_mac_shim.vhd(315) | Removed redundant assignment
@N:CD364 : lda_mac_shim.vhd(316) | Removed redundant assignment
@N:CD364 : lda_mac_shim.vhd(317) | Removed redundant assignment
Post processing for work.lda_mac_shim.rtl
@W:CL169 : lda_mac_shim.vhd(293) | Pruning Register tx_sof_i  
@W:CL169 : lda_mac_shim.vhd(190) | Pruning Register rx_data_valid_i  
@W:CL111 : lda_mac_shim.vhd(225) | All reachable assignments to tx_mac_underrun assign '0', register removed by optimization
@N:CD630 : ll_fifo.vhd(56) | Synthesizing work.ll_fifo.ll_fifo_rtl 
@N:CD630 : ll_fifo_BRAM.vhd(55) | Synthesizing work.ll_fifo_bram.ll_fifo_bram_rtl 
@W:CD638 : ll_fifo_BRAM.vhd(106) | Signal gnd is undriven 
@W:CD638 : ll_fifo_BRAM.vhd(107) | Signal pwr is undriven 
@N:CD630 : BRAM_fifo.vhd(55) | Synthesizing work.bram_fifo.bram_fifo_hdl 
@W:CD638 : BRAM_fifo.vhd(170) | Signal wr_rem_plus_one is undriven 
@W:CD638 : BRAM_fifo.vhd(177) | Signal min_addr2 is undriven 
@W:CD638 : BRAM_fifo.vhd(178) | Signal rem_sel1 is undriven 
@W:CD638 : BRAM_fifo.vhd(179) | Signal rem_sel2 is undriven 
@W:CD638 : BRAM_fifo.vhd(182) | Signal rd_addr_full is undriven 
@W:CD638 : BRAM_fifo.vhd(189) | Signal wr_addr_full is undriven 
@W:CD639 : BRAM_fifo.vhd(192) | Bit <10> of signal write_nextgray is undriven 
@W:CD639 : BRAM_fifo.vhd(192) | Bit <11> of signal write_nextgray is undriven 
@W:CD639 : BRAM_fifo.vhd(192) | Bit <12> of signal write_nextgray is undriven 
@W:CD639 : BRAM_fifo.vhd(192) | Bit <13> of signal write_nextgray is undriven 
@W:CD638 : BRAM_fifo.vhd(195) | Signal rd_allow_minor is undriven 
@W:CD638 : BRAM_fifo.vhd(197) | Signal wr_allow_minor is undriven 
@W:CD639 : BRAM_fifo.vhd(202) | Bit <10> of signal ecomp is undriven 
@W:CD639 : BRAM_fifo.vhd(202) | Bit <11> of signal ecomp is undriven 
@W:CD639 : BRAM_fifo.vhd(202) | Bit <12> of signal ecomp is undriven 
@W:CD639 : BRAM_fifo.vhd(202) | Bit <13> of signal ecomp is undriven 
@W:CD639 : BRAM_fifo.vhd(203) | Bit <10> of signal fcomp is undriven 
@W:CD639 : BRAM_fifo.vhd(203) | Bit <11> of signal fcomp is undriven 
@W:CD639 : BRAM_fifo.vhd(203) | Bit <12> of signal fcomp is undriven 
@W:CD639 : BRAM_fifo.vhd(203) | Bit <13> of signal fcomp is undriven 
@W:CD639 : BRAM_fifo.vhd(204) | Bit <9> of signal emuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(204) | Bit <10> of signal emuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(204) | Bit <11> of signal emuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(204) | Bit <12> of signal emuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(204) | Bit <13> of signal emuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(205) | Bit <9> of signal fmuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(205) | Bit <10> of signal fmuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(205) | Bit <11> of signal fmuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(205) | Bit <12> of signal fmuxcyo is undriven 
@W:CD639 : BRAM_fifo.vhd(205) | Bit <13> of signal fmuxcyo is undriven 
@W:CD638 : BRAM_fifo.vhd(215) | Signal wr_len is undriven 
@W:CD638 : BRAM_fifo.vhd(216) | Signal wr_len_p is undriven 
@W:CD638 : BRAM_fifo.vhd(217) | Signal wr_len_r is undriven 
@W:CD638 : BRAM_fifo.vhd(218) | Signal len_byte_cnt is undriven 
@W:CD638 : BRAM_fifo.vhd(219) | Signal len_byte_cnt_plus_rem is undriven 
@W:CD638 : BRAM_fifo.vhd(220) | Signal rd_len is undriven 
@W:CD638 : BRAM_fifo.vhd(221) | Signal len_word_cnt is undriven 
@W:CD638 : BRAM_fifo.vhd(223) | Signal len_byte_cnt_plus_rem_with_carry is undriven 
@W:CD638 : BRAM_fifo.vhd(224) | Signal total_len_byte_cnt_with_carry is undriven 
@W:CD638 : BRAM_fifo.vhd(225) | Signal len_word_cnt_with_carry is undriven 
@W:CD638 : BRAM_fifo.vhd(226) | Signal len_byte_cnt_with_carry is undriven 
@W:CD638 : BRAM_fifo.vhd(227) | Signal carry1 is undriven 
@W:CD638 : BRAM_fifo.vhd(227) | Signal carry2 is undriven 
@W:CD638 : BRAM_fifo.vhd(227) | Signal carry3 is undriven 
@W:CD638 : BRAM_fifo.vhd(227) | Signal carry4 is undriven 
@W:CD638 : BRAM_fifo.vhd(228) | Signal len_counter_overflow is undriven 
@W:CD638 : BRAM_fifo.vhd(230) | Signal rd_len_rdy_2 is undriven 
@W:CD638 : BRAM_fifo.vhd(231) | Signal rd_len_rdy is undriven 
@W:CD638 : BRAM_fifo.vhd(232) | Signal rd_len_rdy_p is undriven 
@W:CD638 : BRAM_fifo.vhd(233) | Signal rd_len_rdy_p_p is undriven 
@W:CD638 : BRAM_fifo.vhd(235) | Signal wr_len_rdy is undriven 
@W:CD638 : BRAM_fifo.vhd(236) | Signal wr_len_rdy_r is undriven 
@W:CD638 : BRAM_fifo.vhd(237) | Signal wr_len_rdy_p is undriven 
@W:CD638 : BRAM_fifo.vhd(238) | Signal len_wr_allow is undriven 
@W:CD638 : BRAM_fifo.vhd(239) | Signal len_wr_allow_r is undriven 
@W:CD638 : BRAM_fifo.vhd(240) | Signal len_wr_allow_p is undriven 
@W:CD638 : BRAM_fifo.vhd(241) | Signal len_rd_allow is undriven 
@W:CD638 : BRAM_fifo.vhd(242) | Signal len_rd_allow_temp is undriven 
@W:CD638 : BRAM_fifo.vhd(243) | Signal len_wr_addr is undriven 
@W:CD638 : BRAM_fifo.vhd(244) | Signal len_rd_addr is undriven 
@W:CD638 : BRAM_fifo.vhd(245) | Signal len_err is undriven 
@N:CD630 : BRAM_macro.vhd(55) | Synthesizing work.bram_macro.bram_macro_hdl 
@W:CD326 : BRAM_macro.vhd(788) | Port dopb of entity unisim.ramb16_s18_s18 is unconnected
@W:CD326 : BRAM_macro.vhd(788) | Port dob of entity unisim.ramb16_s18_s18 is unconnected
@W:CD638 : BRAM_macro.vhd(150) | Signal rd_data_p is undriven 
@W:CD638 : BRAM_macro.vhd(151) | Signal rd_ctrl_rem_p is undriven 
@W:CD638 : BRAM_macro.vhd(153) | Signal rd_ctrl_p is undriven 
@W:CD638 : BRAM_macro.vhd(154) | Signal wr_rem_plus_one is undriven 
@W:CD638 : BRAM_macro.vhd(155) | Signal wr_ctrl_rem is undriven 
@W:CD638 : BRAM_macro.vhd(156) | Signal rd_ctrl_rem is undriven 
@W:CD638 : BRAM_macro.vhd(159) | Signal rem_sel1 is undriven 
@W:CD638 : BRAM_macro.vhd(160) | Signal rem_sel2 is undriven 
@W:CD638 : BRAM_macro.vhd(168) | Signal wr_sof_temp_n is undriven 
@W:CD638 : BRAM_macro.vhd(170) | Signal c_rd_temp is undriven 
@W:CD638 : BRAM_macro.vhd(171) | Signal c_wr_temp is undriven 
@W:CD638 : BRAM_macro.vhd(172) | Signal c_wr_en is undriven 
@W:CD638 : BRAM_macro.vhd(183) | Signal bram_rd_sel is undriven 
@W:CD638 : BRAM_macro.vhd(184) | Signal bram_wr_sel is undriven 
@W:CD638 : BRAM_macro.vhd(187) | Signal rd_ctrl_rem_grp is undriven 
@W:CD638 : BRAM_macro.vhd(188) | Signal c_rd_ctrl_grp is undriven 
@W:CD638 : BRAM_macro.vhd(190) | Signal c_rd_allow1 is undriven 
@W:CD638 : BRAM_macro.vhd(191) | Signal c_wr_allow1 is undriven 
@W:CD638 : BRAM_macro.vhd(192) | Signal c_rd_allow2 is undriven 
@W:CD638 : BRAM_macro.vhd(193) | Signal c_wr_allow2 is undriven 
@W:CD638 : BRAM_macro.vhd(194) | Signal c_rd_ctrl_rem1 is undriven 
@W:CD638 : BRAM_macro.vhd(195) | Signal c_rd_ctrl_rem2 is undriven 
Post processing for work.bram_macro.bram_macro_hdl
@W:CL240 : BRAM_macro.vhd(183) | bram_rd_sel is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL169 : BRAM_macro.vhd(213) | Pruning Register rd_addr_full_r(13 downto 0)  
Post processing for work.bram_fifo.bram_fifo_hdl
@W:CL240 : BRAM_fifo.vhd(197) | wr_allow_minor is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : BRAM_fifo.vhd(195) | rd_allow_minor is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : BRAM_fifo.vhd(189) | Bit 0 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 1 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 2 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 3 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 4 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 5 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 6 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 7 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 8 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 9 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 10 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 11 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 12 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(189) | Bit 13 of signal wr_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 0 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 1 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 2 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 3 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 4 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 5 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 6 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 7 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 8 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 9 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 10 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 11 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 12 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL252 : BRAM_fifo.vhd(182) | Bit 13 of signal rd_addr_full is floating - a simulation mismatch is possible
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <13> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <12> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <11> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <10> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <5> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <4> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <3> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <2> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <1> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(956) | Pruning bit <0> of fifostatus(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(869) | Pruning bit <13> of wr_addrgray(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(869) | Pruning bit <12> of wr_addrgray(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(869) | Pruning bit <11> of wr_addrgray(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(869) | Pruning bit <10> of wr_addrgray(13 downto 0) - not in use ... 
@W:CL167 : BRAM_fifo.vhd(474) | Input rd_allow_minor of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 0 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 1 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 2 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 3 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 4 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 5 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 6 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 7 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 8 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 9 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 10 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 11 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 12 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 13 of input rd_addr_full of instance BRAM_macro_inst is floating
@W:CL167 : BRAM_fifo.vhd(474) | Input wr_allow_minor of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 0 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 1 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 2 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 3 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 4 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 5 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 6 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 7 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 8 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 9 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 10 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 11 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 12 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL245 : BRAM_fifo.vhd(474) | Bit 13 of input wr_addr_full of instance BRAM_macro_inst is floating
@W:CL170 : BRAM_fifo.vhd(947) | Pruning bit <13> of wr_addrr(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(947) | Pruning bit <12> of wr_addrr(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(947) | Pruning bit <11> of wr_addrr(13 downto 0) - not in use ... 
@W:CL170 : BRAM_fifo.vhd(947) | Pruning bit <10> of wr_addrr(13 downto 0) - not in use ... 
@W:CL111 : BRAM_fifo.vhd(895) | All reachable assignments to wr_addr_minor(0) assign '0', register removed by optimization
@W:CL111 : BRAM_fifo.vhd(882) | All reachable assignments to rd_addr_minor(0) assign '0', register removed by optimization
Post processing for work.ll_fifo_bram.ll_fifo_bram_rtl
Post processing for work.ll_fifo.ll_fifo_rtl
@N:CD630 : ll_fifo.vhd(56) | Synthesizing work.ll_fifo.ll_fifo_rtl 
Post processing for work.ll_fifo.ll_fifo_rtl
Post processing for work.lda_mac.rtl
Post processing for work.lda_mac_block.rtl
@N:CD630 : domain_crossing.vhd(37) | Synthesizing work.domain_crossing.rtl 
@N:CD231 : domain_crossing.vhd(85) | Using onehot encoding for type simple_state (waiting="1000")
Post processing for work.domain_crossing.rtl
@N:CD630 : lda_dif_links.vhd(36) | Synthesizing work.lda_dif_links.rtl 
@W:CG296 : lda_dif_links.vhd(325) | Incomplete sensitivity list - assuming completeness
@W:CG290 : lda_dif_links.vhd(327) | Referenced variable rst is not in sensitivity list
@N:CD630 : lda_dif_links_reg.vhd(54) | Synthesizing work.lda_dif_links_reg.rtl 
Post processing for work.lda_dif_links_reg.rtl
@W:CL190 : lda_dif_links_reg.vhd(98) | Optimizing register bit host_data_out(15) to a constant 0
@W:CL255 : lda_dif_links_reg.vhd(98) | Pruning Register bit 15 of host_data_out(15 downto 0)  
@N:CD630 : lda_module.vhd(35) | Synthesizing work.lda_module.rtl 
@N:CD630 : lda_serdes.vhd(31) | Synthesizing work.lda_serdes.rtl 
@N:CD630 : measure_delay.vhd(37) | Synthesizing work.measure_delay.rtl 
@N:CD231 : measure_delay.vhd(81) | Using onehot encoding for type delay_state_types (idle="10000")
@N:CD364 : measure_delay.vhd(116) | Removed redundant assignment
@N:CD630 : measure_delay_slr.vhd(27) | Synthesizing work.measure_delay_slr.rtl 
Post processing for work.measure_delay_slr.rtl
Post processing for work.measure_delay.rtl
@N:CD630 : link_sm.vhd(29) | Synthesizing work.link_sm.rtl 
@N:CD231 : link_sm.vhd(52) | Using onehot encoding for type serdes_state (startup="100000")
Post processing for work.link_sm.rtl
@N:CD630 : piso.vhd(29) | Synthesizing work.piso.rtl 
Post processing for work.piso.rtl
@N:CD630 : serial_delay.vhd(28) | Synthesizing work.serial_delay.rtl 
Post processing for work.serial_delay.rtl
@N:CD630 : xilinx_encode_8b10b_wrapper.vhd(29) | Synthesizing work.encode_8b10b_wrapper.rtl 
Post processing for work.encode_8b10b_wrapper.rtl
@W:CL169 : xilinx_encode_8b10b_wrapper.vhd(82) | Pruning Register sint_i(2 downto 0)  
@W:CL111 : xilinx_encode_8b10b_wrapper.vhd(113) | All reachable assignments to run_disp(1) assign '0', register removed by optimization
@N:CD630 : xilinx_decode_8b10b_wrapper.vhd(30) | Synthesizing work.decode_8b10b_wrapper.rtl 
Post processing for work.decode_8b10b_wrapper.rtl
@N:CD630 : sipo_oversamp.vhd(34) | Synthesizing work.sipo_oversamp.rtl 
@N:CD364 : sipo_oversamp.vhd(101) | Removed redundant assignment
Post processing for work.sipo_oversamp.rtl
@N:CD630 : data_recovery.vhd(10) | Synthesizing work.data_recovery.rtl 
Post processing for work.data_recovery.rtl
Post processing for work.lda_serdes.rtl
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <19> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <18> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <17> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <16> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <15> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <14> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <13> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <12> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <11> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <10> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <9> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <8> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <7> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <6> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <5> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <4> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(388) | Pruning bit <3> of tx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <19> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <18> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <17> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <16> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <15> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <14> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <13> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <12> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <11> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <10> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <9> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <8> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <7> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <6> of rx_valid_del_i(19 downto 0) - not in use ... 
@W:CL170 : lda_serdes.vhd(299) | Pruning bit <5> of rx_valid_del_i(19 downto 0) - not in use ... 
@N:CD630 : lda_protocol_sm.vhd(65) | Synthesizing work.lda_protocol_sm.rtl 
@N:CD231 : lda_protocol_sm.vhd(113) | Using onehot encoding for type link_state_types (init="10000000")
@W:CD604 : lda_protocol_sm.vhd(419) | OTHERS clause is not synthesized 
@W:CD604 : lda_protocol_sm.vhd(490) | OTHERS clause is not synthesized 
Post processing for work.lda_protocol_sm.rtl
@N:CL177 : lda_protocol_sm.vhd(323) | Sharing sequential element to_serial_rx_resync.
Post processing for work.lda_module.rtl
Post processing for work.lda_dif_links.rtl
@N:CD630 : lda_internal_registers.vhd(71) | Synthesizing work.lda_internal_registers.rtl 
Post processing for work.lda_internal_registers.rtl
@N:CD630 : version.vhd(29) | Synthesizing work.version_registers.rtl 
Post processing for work.version_registers.rtl
@N:CD630 : lda_packetgen.vhd(30) | Synthesizing work.lda_packetgen.rtl 
@N:CD630 : packetgen_sm.vhd(32) | Synthesizing work.packetgen_sm.rtl 
@N:CD231 : packetgen_sm.vhd(114) | Using onehot encoding for type gen_states (idle="10000000")
@N:CD231 : packetgen_sm.vhd(120) | Using onehot encoding for type cnt_type (c0="1000")
@N:CD231 : packetgen_sm.vhd(118) | Using onehot encoding for type tx_bytes_type (b0="1000000000")
@N:CD231 : packetgen_sm.vhd(117) | Using onehot encoding for type header_send_type (destadd="1000")
@W:CD604 : packetgen_sm.vhd(606) | OTHERS clause is not synthesized 
@W:CD604 : packetgen_sm.vhd(723) | OTHERS clause is not synthesized 
Post processing for work.packetgen_sm.rtl
@N:CL134 : packetgen_sm.vhd(136) | Found RAM lda2_mem, depth=8, width=8
@N:CL134 : packetgen_sm.vhd(135) | Found RAM lda1_mem, depth=8, width=8
@N:CL134 : packetgen_sm.vhd(134) | Found RAM srcmac_mem, depth=8, width=8
@N:CL134 : packetgen_sm.vhd(133) | Found RAM dstmac_mem, depth=8, width=8
Post processing for work.lda_packetgen.rtl
@N:CD630 : tx_arbiter.vhd(35) | Synthesizing work.tx_arbiter.rtl 
Post processing for work.tx_arbiter.rtl
@N:CD630 : lda_main_sm.vhd(39) | Synthesizing work.lda_main_sm.rtl 
@N:CD231 : lda_main_sm.vhd(175) | Using onehot encoding for type main_rx_states (idle="100000000")
@N:CD231 : lda_main_sm.vhd(194) | Using onehot encoding for type main_tx_header_states (buildhdr="100000")
@W:CD604 : lda_main_sm.vhd(487) | OTHERS clause is not synthesized 
@N:CD364 : lda_main_sm.vhd(1018) | Removed redundant assignment
@W:CD638 : lda_main_sm.vhd(147) | Signal rx_sm_done_mem_i is undriven 
@W:CD638 : lda_main_sm.vhd(163) | Signal mem_tx_packet_data_i is undriven 
@N:CD630 : lda_dif_sm.vhd(58) | Synthesizing work.lda_dif_sm.rtl 
@N:CD231 : lda_dif_sm.vhd(106) | Using onehot encoding for type rx_states (idle="1000000")
@N:CD231 : lda_dif_sm.vhd(111) | Using onehot encoding for type tx_states (idle="100000")
@W:CD604 : lda_dif_sm.vhd(268) | OTHERS clause is not synthesized 
@W:CD604 : lda_dif_sm.vhd(364) | OTHERS clause is not synthesized 
@W:CD604 : lda_dif_sm.vhd(453) | OTHERS clause is not synthesized 
@N:CD630 : lda_dif_memory.vhd(32) | Synthesizing work.lda_dif_memory.rtl 
Post processing for work.lda_dif_memory.rtl
Post processing for work.lda_dif_sm.rtl
@N:CD630 : lda_reg_sm.vhd(41) | Synthesizing work.lda_reg_sm.rtl 
@N:CD231 : lda_reg_sm.vhd(103) | Using onehot encoding for type reg_states (idle="100000000000000")
@N:CD231 : lda_reg_sm.vhd(157) | Using onehot encoding for type tx_bytes_type (b0="1000000000")
@N:CD231 : lda_reg_sm.vhd(155) | Using onehot encoding for type header_send_type (destadd="1000")
@N:CD231 : lda_reg_sm.vhd(154) | Using onehot encoding for type main_tx_states (idle="10000000")
Post processing for work.lda_reg_sm.rtl
@W:CL169 : lda_reg_sm.vhd(804) | Pruning Register tx_packet_idle_i  
@W:CL169 : lda_reg_sm.vhd(206) | Pruning Register running_i  
@N:CL134 : lda_reg_sm.vhd(169) | Found RAM lda2_mem, depth=8, width=8
@N:CL134 : lda_reg_sm.vhd(168) | Found RAM lda1_mem, depth=8, width=8
@N:CL134 : lda_reg_sm.vhd(167) | Found RAM srcmac_mem, depth=8, width=8
@N:CL134 : lda_reg_sm.vhd(166) | Found RAM dstmac_mem, depth=8, width=8
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_miim_sel to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_req to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_opcode(0) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_opcode(1) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(0) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(1) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(2) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(3) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(4) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(5) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(6) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(7) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(8) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_addr(9) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(0) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(1) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(2) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(3) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(4) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(5) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(6) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(7) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(8) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(9) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(10) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(11) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(12) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(13) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(14) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(15) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(16) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(17) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(18) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(19) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(20) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(21) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(22) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(23) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(24) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(25) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(26) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(27) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(28) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(29) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(30) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit lda_sm_host_wr_data(31) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit read_data_i(24) to a constant 0
@W:CL190 : lda_reg_sm.vhd(546) | Optimizing register bit read_data_i(29) to a constant 0
@W:CL169 : lda_reg_sm.vhd(546) | Pruning Register lda_sm_host_miim_sel  
@W:CL169 : lda_reg_sm.vhd(546) | Pruning Register lda_sm_host_req  
@W:CL169 : lda_reg_sm.vhd(546) | Pruning Register lda_sm_host_opcode(1 downto 0)  
@W:CL169 : lda_reg_sm.vhd(546) | Pruning Register lda_sm_host_addr(9 downto 0)  
@W:CL169 : lda_reg_sm.vhd(546) | Pruning Register lda_sm_host_wr_data(31 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 29 of read_data_i(31 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 24 of read_data_i(31 downto 0)  
Post processing for work.lda_main_sm.rtl
@W:CL252 : lda_main_sm.vhd(163) | Bit 0 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 1 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 2 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 3 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 4 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 5 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 6 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL252 : lda_main_sm.vhd(163) | Bit 7 of signal mem_tx_packet_data_i is floating - a simulation mismatch is possible
@W:CL169 : lda_main_sm.vhd(383) | Pruning Register rx_sm_start_mem_i  
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(1) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(2) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(4) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(6) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(7) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(8) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(9) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(10) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(11) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(12) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(13) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(14) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(15) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(17) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(20) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(22) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(26) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(28) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(29) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(30) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit header_store_i(31) to a constant 0
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 31 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 30 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 29 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 28 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 26 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 22 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 20 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 17 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 15 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 14 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 13 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 12 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 11 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 10 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 9 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 8 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 7 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 6 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 4 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 2 of header_store_i(175 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 1 of header_store_i(175 downto 0)  
@N:CD630 : single_port.vhd(37) | Synthesizing work.single_port.rtl 
@N:CD630 : rx_client_fifo.vhd(100) | Synthesizing work.rx_client_fifo.rtl 
@N:CD231 : rx_client_fifo.vhd(132) | Using onehot encoding for type rd_state_typ (wait_s="10000000")
@N:CD231 : rx_client_fifo.vhd(137) | Using onehot encoding for type wr_state_typ (idle_s="100000")
@W:CD604 : rx_client_fifo.vhd(332) | OTHERS clause is not synthesized 
@W:CD604 : rx_client_fifo.vhd(638) | OTHERS clause is not synthesized 
@W:CD326 : rx_client_fifo.vhd(921) | Port dopa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD326 : rx_client_fifo.vhd(921) | Port doa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD326 : rx_client_fifo.vhd(944) | Port dopa of entity unisim.ramb16_s9_s9 is unconnected
@W:CD326 : rx_client_fifo.vhd(944) | Port doa of entity unisim.ramb16_s9_s9 is unconnected
Post processing for work.rx_client_fifo.rtl
@N:CD630 : pause_ctrl.vhd(36) | Synthesizing work.pause_ctrl.rtl 
@N:CD231 : pause_ctrl.vhd(62) | Using onehot encoding for type states (idle="1000")
@W:CD604 : pause_ctrl.vhd(106) | OTHERS clause is not synthesized 
@W:CD604 : pause_ctrl.vhd(124) | OTHERS clause is not synthesized 
Post processing for work.pause_ctrl.rtl
Post processing for work.single_port.rtl
@N:CD630 : fast_decoder.vhd(75) | Synthesizing work.fast_decoder.rtl 
Post processing for work.fast_decoder.rtl
@W:CL169 : fast_decoder.vhd(163) | Pruning Register fast_type_i(15 downto 0)  
@N:CD630 : rx_arbiter.vhd(40) | Synthesizing work.rx_arbiter.rtl 
Post processing for work.rx_arbiter.rtl
@N:CL177 : rx_arbiter.vhd(90) | Sharing sequential element rx1_data.
@N:CL177 : rx_arbiter.vhd(90) | Sharing sequential element rx1_data_valid.
@N:CD630 : gigethernet_host_shim.vhd(39) | Synthesizing work.gigethernet_host_shim.rtl 
@N:CD231 : gigethernet_host_shim.vhd(146) | Using onehot encoding for type host_register_states (idle="100000000000000")
@W:CD604 : gigethernet_host_shim.vhd(307) | OTHERS clause is not synthesized 
@N:CD630 : gigethernet_host_statemachine.vhd(37) | Synthesizing work.gigethernet_host_statemachine.rtl 
@N:CD231 : gigethernet_host_statemachine.vhd(62) | Using onehot encoding for type interface_states (idle="100000000")
@W:CD604 : gigethernet_host_statemachine.vhd(188) | OTHERS clause is not synthesized 
@N:CD364 : gigethernet_host_statemachine.vhd(216) | Removed redundant assignment
@N:CD364 : gigethernet_host_statemachine.vhd(225) | Removed redundant assignment
@N:CD364 : gigethernet_host_statemachine.vhd(233) | Removed redundant assignment
@N:CD364 : gigethernet_host_statemachine.vhd(251) | Removed redundant assignment
@N:CD364 : gigethernet_host_statemachine.vhd(259) | Removed redundant assignment
@N:CD364 : gigethernet_host_statemachine.vhd(267) | Removed redundant assignment
@W:CD604 : gigethernet_host_statemachine.vhd(277) | OTHERS clause is not synthesized 
Post processing for work.gigethernet_host_statemachine.rtl
@W:CL169 : gigethernet_host_statemachine.vhd(82) | Pruning Register strobe_del2_i  
@W:CL117 : gigethernet_host_statemachine.vhd(198) | Latch generated from process for signal RD_DATA_i(31 downto 0), probably caused by a missing assignment in an if or case stmt
Post processing for work.gigethernet_host_shim.rtl
@W:CL190 : gigethernet_host_shim.vhd(211) | Optimizing register bit auto_neg_Addr_i(0) to a constant 0
@W:CL190 : gigethernet_host_shim.vhd(211) | Optimizing register bit auto_neg_Addr_i(1) to a constant 0
@W:CL190 : gigethernet_host_shim.vhd(211) | Optimizing register bit auto_neg_Addr_i(3) to a constant 0
@W:CL190 : gigethernet_host_shim.vhd(211) | Optimizing register bit auto_neg_Addr_i(5) to a constant 0
@W:CL255 : gigethernet_host_shim.vhd(211) | Pruning Register bit 5 of auto_neg_Addr_i(9 downto 0)  
@W:CL255 : gigethernet_host_shim.vhd(211) | Pruning Register bit 3 of auto_neg_Addr_i(9 downto 0)  
@W:CL255 : gigethernet_host_shim.vhd(211) | Pruning Register bit 1 of auto_neg_Addr_i(9 downto 0)  
@W:CL255 : gigethernet_host_shim.vhd(211) | Pruning Register bit 0 of auto_neg_Addr_i(9 downto 0)  
@N:CD630 : gigethernet_xilinx.vhd(34) | Synthesizing work.gigethernet.rtl 
Post processing for work.gigethernet.rtl
Post processing for work.md2.rtl
@W:CL170 : md2.vhd(1248) | Pruning bit <4> of pma_dcm_locked_sr_i(4 downto 0) - not in use ... 
@W:CL170 : md2.vhd(1248) | Pruning bit <3> of pma_dcm_locked_sr_i(4 downto 0) - not in use ... 
@N:CL201 : gigethernet_host_statemachine.vhd(110) | Trying to extract state machine for register statemachine
Extracted state machine for register statemachine
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@W:CL249 : gigethernet_host_statemachine.vhd(110) | Initial value is not supported on state machine statemachine
@N:CL201 : gigethernet_host_shim.vhd(211) | Trying to extract state machine for register statemachine
Extracted state machine for register statemachine
State machine has 15 reachable states with original encodings of:
   000000000000001
   000000000000010
   000000000000100
   000000000001000
   000000000010000
   000000000100000
   000000001000000
   000000010000000
   000000100000000
   000001000000000
   000010000000000
   000100000000000
   001000000000000
   010000000000000
   100000000000000
@W:CL249 : gigethernet_host_shim.vhd(211) | Initial value is not supported on state machine statemachine
@W:CL159 : rx_arbiter.vhd(47) | Input rx_enable is unused
@W:CL159 : fast_decoder.vhd(84) | Input rx_good_frame is unused
@W:CL159 : fast_decoder.vhd(85) | Input rx_bad_frame is unused
@N:CL201 : pause_ctrl.vhd(70) | Trying to extract state machine for register statemachine
Extracted state machine for register statemachine
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@W:CL249 : pause_ctrl.vhd(70) | Initial value is not supported on state machine statemachine
@N:CL135 : rx_client_fifo.vhd(751) | Found seqShift wr_data, depth=3, width=8
@N:CL201 : rx_client_fifo.vhd(576) | Trying to extract state machine for register wr_state
Extracted state machine for register wr_state
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@N:CL201 : rx_client_fifo.vhd(268) | Trying to extract state machine for register rd_state
Extracted state machine for register rd_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@N:CL201 : lda_reg_sm.vhd(1258) | Trying to extract state machine for register hdr_bytes
Extracted state machine for register hdr_bytes
State machine has 7 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
@N:CL201 : lda_reg_sm.vhd(941) | Trying to extract state machine for register tx_hdr_bytes
Extracted state machine for register tx_hdr_bytes
State machine has 8 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
   0010000000
@N:CL201 : lda_reg_sm.vhd(941) | Trying to extract state machine for register hdr_mode
Extracted state machine for register hdr_mode
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@N:CL201 : lda_reg_sm.vhd(804) | Trying to extract state machine for register tx_state_i
Extracted state machine for register tx_state_i
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@N:CL201 : lda_reg_sm.vhd(546) | Trying to extract state machine for register handle_memory_index_v
Extracted state machine for register handle_memory_index_v
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : lda_reg_sm.vhd(206) | Trying to extract state machine for register state_i
Extracted state machine for register state_i
State machine has 15 reachable states with original encodings of:
   000000000000001
   000000000000010
   000000000000100
   000000000001000
   000000000010000
   000000000100000
   000000001000000
   000000010000000
   000000100000000
   000001000000000
   000010000000000
   000100000000000
   001000000000000
   010000000000000
   100000000000000
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 23 of read_data_i(23 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 22 of read_data_i(23 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 21 of read_data_i(23 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 20 of read_data_i(23 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 19 of read_data_i(23 downto 0)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 31 of read_data_i(31 downto 30)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 28 of read_data_i(28 downto 25)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 27 of read_data_i(28 downto 25)  
@W:CL255 : lda_reg_sm.vhd(546) | Pruning Register bit 26 of read_data_i(28 downto 25)  
@W:CL159 : lda_reg_sm.vhd(54) | Input packet_eth_destination is unused
@W:CL159 : lda_reg_sm.vhd(58) | Input packet_lda_mod is unused
@W:CL159 : lda_reg_sm.vhd(68) | Input lda_sm_host_available is unused
@W:CL159 : lda_reg_sm.vhd(74) | Input lda_sm_host_rd_data is unused
@W:CL159 : lda_reg_sm.vhd(75) | Input lda_sm_host_miim_rdy is unused
@N:CL201 : lda_dif_sm.vhd(391) | Trying to extract state machine for register rx_state_i
Extracted state machine for register rx_state_i
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@W:CL249 : lda_dif_sm.vhd(391) | Initial value is not supported on state machine rx_state_i
@N:CL201 : lda_dif_sm.vhd(218) | Trying to extract state machine for register tx_state_i
Extracted state machine for register tx_state_i
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL249 : lda_dif_sm.vhd(218) | Initial value is not supported on state machine tx_state_i
@W:CL246 : lda_dif_sm.vhd(77) | Input port bits 15 to 8 of packet_lda_type(15 downto 0) are unused 
@W:CL246 : lda_dif_sm.vhd(78) | Input port bits 15 to 8 of packet_lda_mod(15 downto 0) are unused 
@W:CL246 : lda_dif_sm.vhd(79) | Input port bits 15 to 11 of packet_lda_len(15 downto 0) are unused 
@W:CL159 : lda_dif_sm.vhd(65) | Input tx_dst_rdy is unused
@W:CL159 : lda_dif_sm.vhd(73) | Input packet_eth_source is unused
@W:CL159 : lda_dif_sm.vhd(74) | Input packet_eth_destination is unused
@W:CL159 : lda_dif_sm.vhd(75) | Input packet_eth_type is unused
@W:CL159 : lda_dif_sm.vhd(96) | Input lda_sm_reg_mac is unused
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(1) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(2) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(4) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(6) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(7) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(8) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(9) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(10) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(11) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(12) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(13) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(14) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tmp_header_buffer_i(15) to a constant 0
@W:CL190 : lda_main_sm.vhd(679) | Optimizing register bit tx_byte_count_i(6) to a constant 0
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 6 of tx_byte_count_i(6 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 15 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 14 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 13 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 12 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 11 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 10 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 9 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 8 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 7 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 6 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 4 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 2 of tmp_header_buffer_i(63 downto 0)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 1 of tmp_header_buffer_i(63 downto 0)  
@N:CL201 : lda_main_sm.vhd(383) | Trying to extract state machine for register main_rx_state_i
Extracted state machine for register main_rx_state_i
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@W:CL249 : lda_main_sm.vhd(383) | Initial value is not supported on state machine main_rx_state_i
@N:CL201 : lda_main_sm.vhd(679) | Trying to extract state machine for register tx_state_v
Extracted state machine for register tx_state_v
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 63 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 62 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 61 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 60 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 59 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 58 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 57 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 56 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 55 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 54 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 53 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 52 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 51 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 50 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 49 of header_store_i(175 downto 32)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 19 of header_store_i(19 downto 18)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 25 of header_store_i(25 downto 23)  
@W:CL255 : lda_main_sm.vhd(679) | Pruning Register bit 24 of header_store_i(25 downto 23)  
@W:CL159 : lda_main_sm.vhd(53) | Input lda_sm_rx_fifo_status_in is unused
@W:CL159 : lda_main_sm.vhd(59) | Input lda_sm_tx_fifo_status_in is unused
@W:CL159 : lda_main_sm.vhd(99) | Input lda_sm_gig_link_up is unused
@W:CL159 : lda_main_sm.vhd(100) | Input lda_sm_ID_loaded is unused
@N:CL201 : packetgen_sm.vhd(655) | Trying to extract state machine for register statemachine
Extracted state machine for register statemachine
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@N:CL201 : packetgen_sm.vhd(386) | Trying to extract state machine for register tx_hdr_bytes
Extracted state machine for register tx_hdr_bytes
State machine has 7 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
@N:CL201 : packetgen_sm.vhd(386) | Trying to extract state machine for register hdr_mode
Extracted state machine for register hdr_mode
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@N:CL201 : packetgen_sm.vhd(386) | Trying to extract state machine for register cnt
Extracted state machine for register cnt
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@N:CL201 : packetgen_sm.vhd(298) | Trying to extract state machine for register hdr_bytes
Extracted state machine for register hdr_bytes
State machine has 7 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
@W:CL255 : packetgen_sm.vhd(298) | Pruning Register bit 7 of lda1_mem_in(7 downto 0)  
@W:CL255 : packetgen_sm.vhd(298) | Pruning Register bit 6 of lda1_mem_in(7 downto 0)  
@W:CL255 : packetgen_sm.vhd(298) | Pruning Register bit 5 of lda1_mem_in(7 downto 0)  
@W:CL255 : packetgen_sm.vhd(298) | Pruning Register bit 4 of lda1_mem_in(7 downto 0)  
@W:CL255 : packetgen_sm.vhd(298) | Pruning Register bit 2 of lda1_mem_in(7 downto 0)  
@W:CL159 : packetgen_sm.vhd(58) | Input tx_fifo_status_out is unused
@W:CL189 : lda_protocol_sm.vhd(162) | Register bit correct_idle_i(6) is always 1, optimizing ...
@W:CL189 : lda_protocol_sm.vhd(162) | Register bit correct_idle_i(5) is always 0, optimizing ...
@W:CL189 : lda_protocol_sm.vhd(162) | Register bit correct_idle_i(3) is always 0, optimizing ...
@W:CL189 : lda_protocol_sm.vhd(162) | Register bit correct_idle_i(1) is always 0, optimizing ...
@W:CL255 : lda_protocol_sm.vhd(162) | Pruning Register bit 7 of correct_idle_i(7 downto 0)  
@W:CL255 : lda_protocol_sm.vhd(162) | Pruning Register bit 6 of correct_idle_i(7 downto 0)  
@W:CL255 : lda_protocol_sm.vhd(162) | Pruning Register bit 5 of correct_idle_i(7 downto 0)  
@W:CL255 : lda_protocol_sm.vhd(162) | Pruning Register bit 3 of correct_idle_i(7 downto 0)  
@W:CL255 : lda_protocol_sm.vhd(162) | Pruning Register bit 2 of correct_idle_i(7 downto 0)  
@W:CL255 : lda_protocol_sm.vhd(162) | Pruning Register bit 1 of correct_idle_i(7 downto 0)  
@N:CL201 : lda_protocol_sm.vhd(323) | Trying to extract state machine for register state_i
Extracted state machine for register state_i
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@W:CL246 : lda_protocol_sm.vhd(74) | Input port bits 16 to 0 of lda_word_clk_strb(19 downto 0) are unused 
@N:CL135 : serial_delay.vhd(50) | Found seqShift delay, depth=32, width=1
@W:CL159 : serial_delay.vhd(32) | Input rst is unused
@N:CL201 : link_sm.vhd(95) | Trying to extract state machine for register state_i
Extracted state machine for register state_i
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL249 : link_sm.vhd(95) | Initial value is not supported on state machine state_i
@N:CL135 : measure_delay_slr.vhd(54) | Found seqShift temp, depth=32, width=1
@W:CL246 : measure_delay_slr.vhd(36) | Input port bits 31 to 5 of index(31 downto 0) are unused 
@N:CL201 : measure_delay.vhd(156) | Trying to extract state machine for register delay_state_i
Extracted state machine for register delay_state_i
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL247 : lda_dif_links_reg.vhd(60) | Input port bit 15 of host_data_in(15 downto 0) is unused 
@N:CL201 : domain_crossing.vhd(167) | Trying to extract state machine for register state2_i
Extracted state machine for register state2_i
State machine has 3 reachable states with original encodings of:
   0001
   0010
   0100
@W:CL249 : domain_crossing.vhd(167) | Initial value is not supported on state machine state2_i
@N:CL201 : domain_crossing.vhd(99) | Trying to extract state machine for register state_i
Extracted state machine for register state_i
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@W:CL249 : domain_crossing.vhd(99) | Initial value is not supported on state machine state_i
@W:CL246 : BRAM_macro.vhd(88) | Input port bits 13 to 10 of rd_addr(13 downto 0) are unused 
@W:CL246 : BRAM_macro.vhd(97) | Input port bits 13 to 10 of wr_addr(13 downto 0) are unused 
@W:CL157 : BRAM_macro.vhd(803) | Output rd_rem has undriven bits - a simulation mismatch is possible 
@W:CL159 : BRAM_macro.vhd(78) | Input fifo_gsr is unused
@W:CL159 : BRAM_macro.vhd(85) | Input rd_allow_minor is unused
@W:CL159 : BRAM_macro.vhd(86) | Input rd_addr_full is unused
@W:CL159 : BRAM_macro.vhd(87) | Input rd_addr_minor is unused
@W:CL159 : BRAM_macro.vhd(96) | Input wr_allow_minor is unused
@W:CL159 : BRAM_macro.vhd(98) | Input wr_addr_minor is unused
@W:CL159 : BRAM_macro.vhd(99) | Input wr_addr_full is unused
@W:CL159 : BRAM_macro.vhd(101) | Input wr_rem is unused
@N:CL201 : lda_mac_shim.vhd(225) | Trying to extract state machine for register tx_state_i
Extracted state machine for register tx_state_i
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@N:CL201 : lda_mac_shim.vhd(130) | Trying to extract state machine for register rx_state_i
Extracted state machine for register rx_state_i
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL159 : lda_mac_shim.vhd(56) | Input tx_ll_rem_in is unused
@N:CL201 : dif_packet.vhd(342) | Trying to extract state machine for register tx_state_i
Extracted state machine for register tx_state_i
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@N:CL201 : dif_packet.vhd(128) | Trying to extract state machine for register rx_state_i
Extracted state machine for register rx_state_i
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL255 : dif_packet.vhd(342) | Pruning Register bit 1 of to_serdes_parallel_tx_k(1 downto 0)  
@N:CL201 : ll_mux2_rx.vhd(55) | Trying to extract state machine for register mux_machine
Extracted state machine for register mux_machine
State machine has 2 reachable states with original encodings of:
   01
   10
@N:CL201 : ll_mux_ctrl_rtl.vhd(49) | Trying to extract state machine for register arbiter_machine
Extracted state machine for register arbiter_machine
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@N:CL201 : tx_client_fifo.vhd(299) | Trying to extract state machine for register wr_state
Extracted state machine for register wr_state
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@N:CL201 : tx_client_fifo.vhd(407) | Trying to extract state machine for register rd_state
Extracted state machine for register rd_state
State machine has 7 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
@W:CL255 : lda_spi_core.vhd(142) | Pruning Register bit 9 of spi_buffer_tx(9 downto 0)  
@N:CL201 : lda_spi_state.vhd(160) | Trying to extract state machine for register spi_state_i
Extracted state machine for register spi_state_i
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL249 : lda_spi_state.vhd(160) | Initial value is not supported on state machine spi_state_i
@W:CL159 : lda_spi_state.vhd(63) | Input tx_data_en is unused
@W:CL159 : lda_spi_state.vhd(64) | Input spi_enabled is unused
@W:CL246 : md2.vhd(46) | Input port bits 10 to 9 of dif_serial_rx(10 downto 1) are unused 
@W:CL157 : md2.vhd(1716) | Output dif_serial_tx has undriven bits - a simulation mismatch is possible 
@W:CL157 : md2.vhd(56) | Output user_led has undriven bits - a simulation mismatch is possible 
@W:CL159 : md2.vhd(53) | Input gig_syncen is unused
@W:CL159 : md2.vhd(58) | Input tlk_rx is unused
@W:CL159 : md2.vhd(61) | Input tlk_rx_er is unused
@W:CL159 : md2.vhd(62) | Input tlk_rx_dv is unused
@W:CL159 : md2.vhd(63) | Input tlk_rx_clk is unused
@W:CL158 : md2.vhd(71) | Inout sdram_dq is unused
# Tue Mar 16 10:30:51 2010

###########################################################]
Synopsys Netlist Filter, version comp400rc, Build 019R, built May 19 2009
@W: : md2.vhd(1118) | Unbound component OFDDRRSE of instance gloddar_dif_clk0\.gen_ddr_serial_clk 
@W: : md2.vhd(1145) | Unbound component IBUFG of instance gloddar_refclk0\.GTXIBUF 
@W: : md2.vhd(1160) | Unbound component BUFG of instance GTXGBUF 
@W: : md2.vhd(1168) | Unbound component BUFG of instance DIFGBUF 
@W: : md2.vhd(1177) | Unbound component IBUFG of instance gloddar_01\.DIFIBUF 
@W: : md2.vhd(1183) | Unbound component IBUFG of instance gloddar_01\.RBCIBUF 
@W: : md2.vhd(1190) | Unbound component BUFG of instance RBCGBUF 
@W: : md2.vhd(1199) | Unbound component DCM of instance PMACLK_DCM 
@W: : md2.vhd(1237) | Unbound component BUFG of instance PMACLK1_GBUF 
@W: : md2.vhd(1935) | Unbound component lda_wrap_dif_work_md2_rtl_0 of instance dif_packet_wrapper 
@W: : lda_dif_links.vhd(251) | Unbound component DCM of instance DCM_GEN90 
@W: : lda_dif_links.vhd(286) | Unbound component BUFG of instance DCM_CLK_BUFG_INST 
@W: : lda_dif_links.vhd(290) | Unbound component BUFG of instance DCM_CLK90_BUFG_INST 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 16 10:30:52 2010

###########################################################]
@END
Process took 0h:00m:25s realtime, 0h:00m:22s cputime
# Tue Mar 16 10:30:52 2010

###########################################################]
Synopsys Xilinx Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 14:02:53
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
Product Version C-2009.06
Reading constraint file: /home/warren/calicedaq/LDA/firmware/source/main/md2.sdc
define_clock: no clocks specified
Adding property syn_false_path1009, value "comment Just LEDs, who cares. to p:user_led[3:0]" to view:work.md2(rtl)
Adding property syn_false_path1010, value "comment Just LEDs, who cares. to p:md2_led[5:1]" to view:work.md2(rtl)
Reading constraint file: /home/warren/calicedaq/LDA/firmware/source/main/md2_conv.sdc
@N:BN261 :  | Empty union 
   line was: c_union s:10017 s:10017 
@N:BN261 :  | Empty union 
   line was: c_union s:10029 s:10029 
@N:BN261 :  | Empty union 
   line was: c_union s:10048 s:10048 
@N:BN261 :  | Empty union 
   line was: c_union s:10131 s:10131 
Adding property syn_false_path1357, value "from s:10011 to s:10023" to view:work.md2(rtl)
Adding property syn_false_path1358, value "from s:10011 to s:10035" to view:work.md2(rtl)
Adding property syn_false_path1359, value "from s:10042 to s:10035" to view:work.md2(rtl)
Adding property syn_maxdelay_path1360, value "8.000000 delay to $host" to view:work.md2(rtl)
Adding property syn_maxdelay_path1361, value "400.000000 delay to $mdio_logic" to view:work.md2(rtl)
Adding property syn_maxdelay_path1362, value "200.000000 delay from $mdc_rising to $mdc_falling" to view:work.md2(rtl)
Adding property syn_maxdelay_path1363, value "8.000000 delay from $mdio_logic to $host" to view:work.md2(rtl)
Adding property syn_maxdelay_path1364, value "8.000000 delay from $host to $mdio_logic" to view:work.md2(rtl)
Adding property syn_false_path1365, value "from s:10156 to s:10023" to view:work.md2(rtl)
Adding property syn_false_path1366, value "from s:10156 to s:10035" to view:work.md2(rtl)
Adding property syn_maxdelay_path1367, value "8.000000 delay from $FFS to $codec8b10b" to view:work.md2(rtl)
Adding property syn_maxdelay_path1368, value "8.000000 delay from $codec8b10b to $FFS" to view:work.md2(rtl)
Adding property syn_maxdelay_path1369, value "8.000000 delay from $RAMS to $rx_distmem_regs" to view:work.md2(rtl)
Adding property syn_maxdelay_path1370, value "14.000000 delay from $tx_graycode to $rx_graycode" to view:work.md2(rtl)
Adding property syn_maxdelay_path1371, value "5.000000 delay from $rx_graycode to $rx_binary" to view:work.md2(rtl)
@W:BN238 :  | Constraint object has wildcard(s) but is missing a qualifier (e.g., "p:", "i:", "t:", or "n:"): define_attribute {gig_td[?]} syn_io_slew FAST 
@W:BN238 :  | Constraint object has wildcard(s) but is missing a qualifier (e.g., "p:", "i:", "t:", or "n:"): define_attribute Ethernet_Downlink.tx_code_group* syn_useioff 1 
@W:BN238 :  | Constraint object has wildcard(s) but is missing a qualifier (e.g., "p:", "i:", "t:", or "n:"): define_attribute Ethernet_Downlink.rx_code_group_ddr* syn_useioff 1 
@W:BN238 :  | Constraint object has wildcard(s) but is missing a qualifier (e.g., "p:", "i:", "t:", or "n:"): define_attribute {dif_serial_tx[*]} syn_useioff 1 
@W:BN259 :  | One or more non-fatal issues found in constraints; please run Constraint Check for analysis 
@N:MF249 :  | Running in 32-bit mode. 
@N:MF257 :  | Gated clock conversion enabled  
Adding property syn_pad_type, value "LVTTL", to instance cpld_expansionbus_rw_1
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_er_1
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_en_1
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_1
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_2
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_3
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_4
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_5
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_6
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_7
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_8
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_9
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_10
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_11
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_12
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_13
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_14
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_15
Adding property syn_pad_type, value "LVTTL", to instance tlk_tx_16
Adding property xc_loc, value "v4", to instance cpld_expansionbus_cs
Adding property syn_pad_type, value "LVTTL", to instance cpld_expansionbus_cs
Adding property xc_loc, value "T21", to instance sdram_cas
Adding property xc_loc, value "H22", to instance sdram_cke
Adding property xc_loc, value "G21", to instance sdram_clk
Adding property xc_loc, value "R22", to instance sdram_cs
Adding property xc_loc, value "R21", to instance sdram_ras
Adding property xc_loc, value "T22", to instance sdram_we
Adding property xc_loc, value "J4", to instance tlk_enable
Adding property syn_pad_type, value "LVTTL", to instance tlk_enable
Adding property xc_loc, value "U7", to instance tlk_lockrefn
Adding property syn_pad_type, value "LVTTL", to instance tlk_lockrefn
Adding property syn_maxfan, value 250, to instance rst
Adding property xc_loc, value "AA6", to instance gig_lockrefn
Adding property syn_io_drive, value 16, to instance gig_lockrefn
Adding property syn_io_slew, value "slow", to instance gig_lockrefn
Adding property syn_pad_type, value "LVTTL", to instance gig_lockrefn
Adding property syn_io_slew, value "FAST", to instance gig_lockrefn
Adding property xc_loc, value "Y11", to port dif_clk_in
Adding property xc_loc, value "F9", to port slow_clk_sync
Adding property xc_loc, value "AB13", to port main_reset
Adding property xc_loc, value "A12", to port dif_serial_clk
Adding property syn_pad_type, value "LVTTL", to port dif_serial_clk
Adding property syn_useioff, value 1, to port dif_serial_tx[10:1]
Adding property syn_pad_type, value "LVTTL", to port dif_serial_tx[10:1]
Adding property xc_loc, value "W17", to port gig_syncen
Adding property syn_pad_type, value "LVTTL", to port gig_syncen
Adding property xc_loc, value "AA6", to port gig_lockrefn
Adding property syn_io_drive, value 16, to port gig_lockrefn
Adding property syn_io_slew, value "slow", to port gig_lockrefn
Adding property syn_pad_type, value "LVTTL", to port gig_lockrefn
Adding property syn_io_slew, value "FAST", to port gig_lockrefn
Adding property xc_loc, value "AA12", to port gig_rbc1
Adding property syn_pad_type, value "LVTTL", to port gig_rbc1
Adding property syn_pad_type, value "LVTTL", to port tlk_tx[15:0]
Adding property syn_pad_type, value "LVTTL", to port tlk_rx[15:0]
Adding property xc_loc, value "AB8", to port tlk_tx_en
Adding property syn_pad_type, value "LVTTL", to port tlk_tx_en
Adding property xc_loc, value "W8", to port tlk_tx_er
Adding property syn_pad_type, value "LVTTL", to port tlk_tx_er
Adding property xc_loc, value "Y7", to port tlk_rx_er
Adding property syn_pad_type, value "LVTTL", to port tlk_rx_er
Adding property xc_loc, value "AA7", to port tlk_rx_dv
Adding property syn_pad_type, value "LVTTL", to port tlk_rx_dv
Adding property xc_loc, value "W9", to port tlk_rx_clk
Adding property syn_pad_type, value "LVTTL", to port tlk_rx_clk
Adding property xc_loc, value "J4", to port tlk_enable
Adding property syn_pad_type, value "LVTTL", to port tlk_enable
Adding property xc_loc, value "U7", to port tlk_lockrefn
Adding property syn_pad_type, value "LVTTL", to port tlk_lockrefn
Adding property xc_loc, value "C12", to port refclk125
Adding property syn_pad_type, value "LVTTL", to port refclk125
Adding property xc_loc, value "T22", to port sdram_we
Adding property xc_loc, value "T21", to port sdram_cas
Adding property xc_loc, value "R21", to port sdram_ras
Adding property xc_loc, value "G21", to port sdram_clk
Adding property xc_loc, value "H22", to port sdram_cke
Adding property xc_loc, value "R22", to port sdram_cs
Adding property syn_pad_type, value "LVTTL", to port cpld_expansionbus[7:0]
Adding property syn_useioff, value 1, to port cpld_expansionbus[7:0]
Adding property xc_loc, value "v4", to port cpld_expansionbus_cs
Adding property syn_pad_type, value "LVTTL", to port cpld_expansionbus_cs
Adding property syn_pad_type, value "LVTTL", to port cpld_expansionbus_rw
Adding property xc_loc, value "w2", to port cpld_expansionbus_a_dn
Adding property syn_pad_type, value "LVTTL", to port cpld_expansionbus_a_dn
Adding property xc_loc, value "A3", to port bit dif_serial_tx[1]
Adding property xc_loc, value "B12", to port bit dif_serial_tx[2]
Adding property xc_loc, value "B5", to port bit dif_serial_tx[3]
Adding property xc_loc, value "C11", to port bit dif_serial_tx[4]
Adding property xc_loc, value "F14", to port bit dif_serial_tx[5]
Adding property xc_loc, value "C10", to port bit dif_serial_tx[6]
Adding property xc_loc, value "C18", to port bit dif_serial_tx[7]
Adding property xc_loc, value "C17", to port bit dif_serial_tx[8]
Adding property xc_loc, value "D15", to port bit dif_serial_tx[9]
Adding property xc_loc, value "E10", to port bit dif_serial_tx[10]
Adding property xc_loc, value "A8", to port bit dif_serial_rx[1]
Adding property xc_loc, value "B14", to port bit dif_serial_rx[2]
Adding property xc_loc, value "B8", to port bit dif_serial_rx[3]
Adding property xc_loc, value "B13", to port bit dif_serial_rx[4]
Adding property xc_loc, value "F7", to port bit dif_serial_rx[5]
Adding property xc_loc, value "E17", to port bit dif_serial_rx[6]
Adding property xc_loc, value "F6", to port bit dif_serial_rx[7]
Adding property xc_loc, value "D12", to port bit dif_serial_rx[8]
Adding property xc_loc, value "D18", to port bit dif_serial_rx[9]
Adding property xc_loc, value "A10", to port bit dif_serial_rx[10]
Adding property xc_loc, value "AB19", to port bit gig_td[0]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[0]
Adding property syn_io_slew, value "fast", to port bit gig_td[0]
Adding property syn_io_drive, value 16, to port bit gig_td[0]
Adding property xc_loc, value "W16", to port bit gig_td[1]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[1]
Adding property syn_io_slew, value "fast", to port bit gig_td[1]
Adding property syn_io_drive, value 16, to port bit gig_td[1]
Adding property xc_loc, value "V16", to port bit gig_td[2]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[2]
Adding property syn_io_slew, value "fast", to port bit gig_td[2]
Adding property syn_io_drive, value 16, to port bit gig_td[2]
Adding property xc_loc, value "AA16", to port bit gig_td[3]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[3]
Adding property syn_io_slew, value "fast", to port bit gig_td[3]
Adding property syn_io_drive, value 16, to port bit gig_td[3]
Adding property xc_loc, value "AB16", to port bit gig_td[4]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[4]
Adding property syn_io_slew, value "fast", to port bit gig_td[4]
Adding property syn_io_drive, value 16, to port bit gig_td[4]
Adding property xc_loc, value "AA15", to port bit gig_td[5]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[5]
Adding property syn_io_slew, value "fast", to port bit gig_td[5]
Adding property syn_io_drive, value 16, to port bit gig_td[5]
Adding property xc_loc, value "V15", to port bit gig_td[6]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[6]
Adding property syn_io_slew, value "fast", to port bit gig_td[6]
Adding property syn_io_drive, value 16, to port bit gig_td[6]
Adding property xc_loc, value "Y17", to port bit gig_td[7]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[7]
Adding property syn_io_slew, value "fast", to port bit gig_td[7]
Adding property syn_io_drive, value 16, to port bit gig_td[7]
Adding property xc_loc, value "W15", to port bit gig_td[8]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[8]
Adding property syn_io_slew, value "fast", to port bit gig_td[8]
Adding property syn_io_drive, value 16, to port bit gig_td[8]
Adding property xc_loc, value "Y5", to port bit gig_td[9]
Adding property syn_pad_type, value "LVTTL", to port bit gig_td[9]
Adding property syn_io_slew, value "fast", to port bit gig_td[9]
Adding property syn_io_drive, value 16, to port bit gig_td[9]
Adding property xc_loc, value "AA18", to port bit gig_rd[0]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[0]
Adding property xc_loc, value "AB18", to port bit gig_rd[1]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[1]
Adding property xc_loc, value "V12", to port bit gig_rd[2]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[2]
Adding property xc_loc, value "U12", to port bit gig_rd[3]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[3]
Adding property xc_loc, value "AA19", to port bit gig_rd[4]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[4]
Adding property xc_loc, value "W5", to port bit gig_rd[5]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[5]
Adding property xc_loc, value "Y4", to port bit gig_rd[6]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[6]
Adding property xc_loc, value "Y6", to port bit gig_rd[7]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[7]
Adding property xc_loc, value "AA9", to port bit gig_rd[8]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[8]
Adding property xc_loc, value "AB9", to port bit gig_rd[9]
Adding property syn_pad_type, value "LVTTL", to port bit gig_rd[9]
Adding property syn_io_slew, value "slow", to port bit gig_lockrefn
Adding property xc_loc, value "B19", to port bit user_led[0]
Adding property xc_loc, value "A19", to port bit user_led[1]
Adding property xc_loc, value "B18", to port bit user_led[2]
Adding property xc_loc, value "A18", to port bit user_led[3]
Adding property xc_loc, value "AB11", to port bit tlk_tx[0]
Adding property xc_loc, value "Y10", to port bit tlk_tx[1]
Adding property xc_loc, value "Y13", to port bit tlk_tx[2]
Adding property xc_loc, value "V17", to port bit tlk_tx[3]
Adding property xc_loc, value "Y13", to port bit tlk_tx[4]
Adding property xc_loc, value "V11", to port bit tlk_tx[5]
Adding property xc_loc, value "W18", to port bit tlk_tx[6]
Adding property xc_loc, value "W11", to port bit tlk_tx[7]
Adding property xc_loc, value "AB12", to port bit tlk_tx[8]
Adding property xc_loc, value "AA11", to port bit tlk_tx[9]
Adding property xc_loc, value "AA3", to port bit tlk_tx[10]
Adding property xc_loc, value "Y16", to port bit tlk_tx[11]
Adding property xc_loc, value "AB10", to port bit tlk_tx[12]
Adding property xc_loc, value "V8", to port bit tlk_tx[13]
Adding property xc_loc, value "AA8", to port bit tlk_tx[14]
Adding property xc_loc, value "AA10", to port bit tlk_tx[15]
Adding property xc_loc, value "U14", to port bit tlk_rx[0]
Adding property xc_loc, value "AB15", to port bit tlk_rx[1]
Adding property xc_loc, value "AA17", to port bit tlk_rx[2]
Adding property xc_loc, value "W13", to port bit tlk_rx[3]
Adding property xc_loc, value "U13", to port bit tlk_rx[4]
Adding property xc_loc, value "V13", to port bit tlk_rx[5]
Adding property xc_loc, value "V14", to port bit tlk_rx[6]
Adding property xc_loc, value "W10", to port bit tlk_rx[7]
Adding property xc_loc, value "V6", to port bit tlk_rx[8]
Adding property xc_loc, value "V9", to port bit tlk_rx[9]
Adding property xc_loc, value "AA4", to port bit tlk_rx[10]
Adding property xc_loc, value "AB4", to port bit tlk_rx[11]
Adding property xc_loc, value "AB7", to port bit tlk_rx[12]
Adding property xc_loc, value "W7", to port bit tlk_rx[13]
Adding property xc_loc, value "W6", to port bit tlk_rx[14]
Adding property xc_loc, value "V7", to port bit tlk_rx[15]
Adding property xc_loc, value "D4", to port bit md2_led[1]
Adding property xc_loc, value "C4", to port bit md2_led[2]
Adding property xc_loc, value "C3", to port bit md2_led[3]
Adding property xc_loc, value "C2", to port bit md2_led[4]
Adding property xc_loc, value "U5", to port bit md2_led[5]
Adding property xc_loc, value "W20", to port bit sdram_dq[0]
Adding property xc_loc, value "Y22", to port bit sdram_dq[1]
Adding property xc_loc, value "Y21", to port bit sdram_dq[2]
Adding property xc_loc, value "W22", to port bit sdram_dq[3]
Adding property xc_loc, value "W21", to port bit sdram_dq[4]
Adding property xc_loc, value "V20", to port bit sdram_dq[5]
Adding property xc_loc, value "V22", to port bit sdram_dq[6]
Adding property xc_loc, value "U21", to port bit sdram_dq[7]
Adding property xc_loc, value "G20", to port bit sdram_dq[8]
Adding property xc_loc, value "F21", to port bit sdram_dq[9]
Adding property xc_loc, value "F20", to port bit sdram_dq[10]
Adding property xc_loc, value "E22", to port bit sdram_dq[11]
Adding property xc_loc, value "E21", to port bit sdram_dq[12]
Adding property xc_loc, value "C22", to port bit sdram_dq[13]
Adding property xc_loc, value "D20", to port bit sdram_dq[14]
Adding property xc_loc, value "D21", to port bit sdram_dq[15]
Adding property xc_loc, value "P19", to port bit sdram_dq[16]
Adding property xc_loc, value "P18", to port bit sdram_dq[17]
Adding property xc_loc, value "P17", to port bit sdram_dq[18]
Adding property xc_loc, value "N18", to port bit sdram_dq[19]
Adding property xc_loc, value "N17", to port bit sdram_dq[20]
Adding property xc_loc, value "M19", to port bit sdram_dq[21]
Adding property xc_loc, value "M18", to port bit sdram_dq[22]
Adding property xc_loc, value "M17", to port bit sdram_dq[23]
Adding property xc_loc, value "L17", to port bit sdram_dq[24]
Adding property xc_loc, value "L19", to port bit sdram_dq[25]
Adding property xc_loc, value "L18", to port bit sdram_dq[26]
Adding property xc_loc, value "K17", to port bit sdram_dq[27]
Adding property xc_loc, value "K18", to port bit sdram_dq[28]
Adding property xc_loc, value "J17", to port bit sdram_dq[29]
Adding property xc_loc, value "J19", to port bit sdram_dq[30]
Adding property xc_loc, value "J18", to port bit sdram_dq[31]
Adding property xc_loc, value "N22", to port bit sdram_a[0]
Adding property xc_loc, value "M20", to port bit sdram_a[1]
Adding property xc_loc, value "M21", to port bit sdram_a[2]
Adding property xc_loc, value "L21", to port bit sdram_a[3]
Adding property xc_loc, value "K20", to port bit sdram_a[4]
Adding property xc_loc, value "K22", to port bit sdram_a[5]
Adding property xc_loc, value "K21", to port bit sdram_a[6]
Adding property xc_loc, value "J22", to port bit sdram_a[7]
Adding property xc_loc, value "J21", to port bit sdram_a[8]
Adding property xc_loc, value "H21", to port bit sdram_a[9]
Adding property xc_loc, value "N21", to port bit sdram_a[10]
Adding property xc_loc, value "P21", to port bit sdram_a[11]
Adding property xc_loc, value "T20", to port bit sdram_dqm[0]
Adding property xc_loc, value "J18", to port bit sdram_dqm[1]
Adding property xc_loc, value "M22", to port bit sdram_dqm[2]
Adding property xc_loc, value "H18", to port bit sdram_dqm[3]
Adding property xc_loc, value "P22", to port bit sdram_ba[0]
Adding property xc_loc, value "N20", to port bit sdram_ba[1]
Adding property xc_loc, value "v3", to port bit cpld_expansionbus[0]
Adding property xc_loc, value "w1", to port bit cpld_expansionbus[1]
Adding property xc_loc, value "u4", to port bit cpld_expansionbus[2]
Adding property xc_loc, value "u3", to port bit cpld_expansionbus[3]
Adding property xc_loc, value "v1", to port bit cpld_expansionbus[4]
Adding property xc_loc, value "y2", to port bit cpld_expansionbus[5]
Adding property xc_loc, value "y3", to port bit cpld_expansionbus[6]
Adding property xc_loc, value "v2", to port bit cpld_expansionbus[7]
Adding property syn_useioff, value 1, to instance Ethernet_Downlink.en_cdet
Adding property syn_useioff, value 1, to instance Ethernet_Downlink.ewrap
Adding property syn_useioff, value 1, to instance Ethernet_Downlink.tx_code_group[9:0]
Adding property syn_useioff, value 1, to port Ethernet_Downlink.tx_code_group[9:0]
Adding property syn_useioff, value 1, to port Ethernet_Downlink.ewrap
Adding property syn_useioff, value 1, to port Ethernet_Downlink.en_cdet
Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] 
Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] 
@N: :  | Running in logic synthesis mode without enhanced optimization 
@W:FX474 :  | User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code  

Adding property syn_io_slew, value "slow", to instance gig_lockrefn
Adding property syn_io_slew, value "FAST", to instance gig_lockrefn
Adding property syn_io_slew, value "slow", to port gig_lockrefn
Adding property syn_io_slew, value "FAST", to port gig_lockrefn
Automatic dissolve during optimization of view:work.lda_dif_sm_work_md2_rtl_3layer0(rtl) of DIF_memory_buffer(lda_dif_memory_work_md2_rtl_2layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.18\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.16\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.4\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.5\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.6\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.0\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.10\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.14\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.8\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.15\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.9\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.19\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.7\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.17\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.11\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.13\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.3\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.2\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.1\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
Automatic dissolve during optimization of view:work.measure_delay_work_md2_rtl_6layer0(rtl) of shift_logic\.12\.slr16_array(measure_delay_slr_work_md2_rtl_5layer0)
@W:MO111 : BRAM_macro.vhd(803) | tristate driver rd_rem_1 on net rd_rem_1 has its enable tied to GND (module BRAM_macro_work_md2_rtl_10layer0) 
@W:MO111 :  | tristate driver read_rem_out_t[1] on net read_rem_out[1] has its enable tied to GND (module BRAM_fifo_work_md2_rtl_11layer0)  
@W:MO111 :  | tristate driver rem_out_t[1] on net rem_out[1] has its enable tied to GND (module ll_fifo_BRAM_work_md2_rtl_12layer0)  
@W:MO111 :  | tristate driver rem_out_r_t[0] on net rem_out_r[0] has its enable tied to GND (module ll_fifo_work_md2_rtl_9layer0)  
@W:MO111 :  | tristate driver rem_out_r_t[0] on net rem_out_r[0] has its enable tied to GND (module ll_fifo_work_md2_rtl_8layer0)  
@W:MO111 :  | tristate driver tx_rem_out_i_t[0] on net tx_rem_out_i[0] has its enable tied to GND (module lda_mac)  
@W:MO111 :  | tristate driver rx_rem_out_t[0] on net rx_rem_out[0] has its enable tied to GND (module lda_mac)  
@W:MO111 :  | tristate driver rx_rem_out_7_t[0] on net rx_rem_out_7[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_6_t[0] on net rx_rem_out_6[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_5_t[0] on net rx_rem_out_5[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_4_t[0] on net rx_rem_out_4[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_3_t[0] on net rx_rem_out_3[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_2_t[0] on net rx_rem_out_2[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_1_t[0] on net rx_rem_out_1[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
@W:MO111 :  | tristate driver rx_rem_out_0_t[0] on net rx_rem_out_0[0] has its enable tied to GND (module lda_mac_block_work_md2_rtl_13layer0)  
Automatic dissolve during optimization of view:work.md2(rtl) of Version_Revision(version_registers)
@W:MO111 : md2.vhd(56) | tristate driver user_led_2 on net user_led[2] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(56) | tristate driver user_led_1 on net user_led[3] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2026) | tristate driver tlk_tx_er_1 on net tlk_tx_er has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2026) | tristate driver tlk_tx_en_1 on net tlk_tx_en has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_16 on net tlk_tx[0] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_15 on net tlk_tx[1] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_14 on net tlk_tx[2] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_13 on net tlk_tx[3] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_12 on net tlk_tx[4] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_11 on net tlk_tx[5] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_10 on net tlk_tx[6] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_9 on net tlk_tx[7] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_8 on net tlk_tx[8] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_7 on net tlk_tx[9] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_6 on net tlk_tx[10] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_5 on net tlk_tx[11] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_4 on net tlk_tx[12] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_3 on net tlk_tx[13] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_2 on net tlk_tx[14] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2036) | tristate driver tlk_tx_1 on net tlk_tx[15] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2050) | tristate driver sdram_dqm_4 on net sdram_dqm[0] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2050) | tristate driver sdram_dqm_3 on net sdram_dqm[1] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2050) | tristate driver sdram_dqm_2 on net sdram_dqm[2] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2050) | tristate driver sdram_dqm_1 on net sdram_dqm[3] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(1716) | tristate driver dif_serial_tx_2 on net dif_serial_tx[9] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(1716) | tristate driver dif_serial_tx_1 on net dif_serial_tx[10] has its enable tied to GND (module md2) 
@W:MO111 : md2.vhd(2026) | tristate driver cpld_expansionbus_rw_1 on net cpld_expansionbus_rw has its enable tied to GND (module md2) 
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[23],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[21],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[18],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[16],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[5],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[3],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance header_store_i[0],  because it is equivalent to instance header_store_i[27]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance tmp_header_buffer_i[3],  because it is equivalent to instance tmp_header_buffer_i[5]
@W:BN132 : lda_main_sm.vhd(679) | Removing sequential instance tmp_header_buffer_i[0],  because it is equivalent to instance tmp_header_buffer_i[5]
@W:BN132 : link_sm.vhd(95) | Removing sequential instance looped_back,  because it is equivalent to instance serial_loop_back_en
@W:MO129 : lda_serdes.vhd(444) | Sequential instance external_loop_back_en_i has been reduced to a combinational gate by constant propagation
@W:MO129 : tx_client_fifo.vhd(283) | Sequential instance rd_enable_delay has been reduced to a combinational gate by constant propagation
Automatic dissolve at startup in view:work.lda_serdes(rtl) of serializer(piso)
Automatic dissolve at startup in view:work.lda_serdes(rtl) of delay_line(serial_delay)
Automatic dissolve at startup in view:work.BRAM_fifo_work_md2_rtl_11layer0(bram_fifo_hdl) of BRAM_macro_inst(BRAM_macro_work_md2_rtl_10layer0)
Automatic dissolve at startup in view:work.BRAM_fifo_work_md2_rtl_11layer0_B_RAM_FIFO(bram_fifo_hdl) of BRAM_macro_inst(BRAM_macro_work_md2_rtl_10layer0_BRAM_macro_inst)

Available hyper_sources - for debug and ip models
	None Found

@N:FX493 :  | Applying Initial value "0000" on instance: sync_reset_in.sync_reset_in®rst_sr[3:0]  
Adding property syn_io_slew, value "slow", to instance gig_lockrefn
Adding property syn_io_slew, value "FAST", to instance gig_lockrefn
Adding property syn_io_slew, value "slow", to port gig_lockrefn
Adding property syn_io_slew, value "FAST", to port gig_lockrefn
Adding property syn_io_slew, value "slow", to instance gig_lockrefn
Adding property syn_io_slew, value "FAST", to instance gig_lockrefn
Adding property syn_io_slew, value "slow", to port gig_lockrefn
Adding property syn_io_slew, value "FAST", to port gig_lockrefn
Finished RTL optimizations (Time elapsed 0h:00m:06s; Memory used current: 104MB peak: 110MB)

Encoding state machine work.gigethernet_host_shim_work_md2_rtl_0layer0(rtl)-statemachine[0:14]
original code -> new code
   000000000000001 -> 000000000000001
   000000000000010 -> 000000000000010
   000000000000100 -> 000000000000100
   000000000001000 -> 000000000001000
   000000000010000 -> 000000000010000
   000000000100000 -> 000000000100000
   000000001000000 -> 000000001000000
   000000010000000 -> 000000010000000
   000000100000000 -> 000000100000000
   000001000000000 -> 000001000000000
   000010000000000 -> 000010000000000
   000100000000000 -> 000100000000000
   001000000000000 -> 001000000000000
   010000000000000 -> 010000000000000
   100000000000000 -> 100000000000000
Encoding state machine work.gigethernet_host_statemachine(rtl)-statemachine[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.pause_ctrl(rtl)-statemachine[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
@N: : pause_ctrl.vhd(132) | Found counter in view:work.pause_ctrl(rtl) inst counter_i[15:0]
@N: : pause_ctrl.vhd(132) | Found counter in view:work.pause_ctrl(rtl) inst counter_small_i[5:0]
Encoding state machine work.tx_client_fifo_work_md2_rtl_14layer0_port1_tx_fifo(rtl)-rd_state[0:6]
original code -> new code
   000000001 -> 0000001
   000000010 -> 0000010
   000000100 -> 0000100
   000001000 -> 0001000
   000010000 -> 0010000
   000100000 -> 0100000
   001000000 -> 1000000
Encoding state machine work.tx_client_fifo_work_md2_rtl_14layer0_port1_tx_fifo(rtl)-wr_state[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
@N: : tx_client_fifo.vhd(852) | Found counter in view:work.tx_client_fifo_work_md2_rtl_14layer0_port1_tx_fifo(rtl) inst rd_addr[11:0]
@N: : tx_client_fifo.vhd(706) | Found updn counter in view:work.tx_client_fifo_work_md2_rtl_14layer0_port1_tx_fifo(rtl) inst wr_frames[8:0] 
Encoding state machine work.rx_client_fifo(rtl)-rd_state[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine work.rx_client_fifo(rtl)-wr_state[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : rx_client_fifo.vhd(550) | Found updn counter in view:work.rx_client_fifo(rtl) inst rd_frames[8:0] 
@N: : rx_client_fifo.vhd(686) | Found counter in view:work.rx_client_fifo(rtl) inst wr_addr[11:0]
@N:FX404 : rx_client_fifo.vhd(857) | Found addmux in view:work.rx_client_fifo(rtl) inst p_addr_diff\.wr_addr_diff_1_m[11:0] from p_addr_diff\.wr_addr_diff_0[11:0] 
Encoding state machine work.lda_main_sm_work_md2_rtl_4layer0(rtl)-main_rx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.lda_main_sm_work_md2_rtl_4layer0(rtl)-tx_state_v[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : lda_main_sm.vhd(383) | Found counter in view:work.lda_main_sm_work_md2_rtl_4layer0(rtl) inst rx_main_byte_count_in_i[4:0]
@N: : lda_main_sm.vhd(679) | Found counter in view:work.lda_main_sm_work_md2_rtl_4layer0(rtl) inst tx_byte_count_i[5:0]
@W:BN132 : lda_main_sm.vhd(679) | Removing instance Main_Statemachine.header_store_i[48],  because it is equivalent to instance Main_Statemachine.header_store_i[27]
@N:MF179 : lda_main_sm.vhd(301) | Found 48 bit by 48 bit '==' comparator, 'check_dest_mac\.un3_rx_packet_eth_destination_i'
Encoding state machine work.lda_reg_sm(rtl)-tx_state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine work.lda_reg_sm(rtl)-state_i[0:14]
original code -> new code
   000000000000001 -> 000000000000001
   000000000000010 -> 000000000000010
   000000000000100 -> 000000000000100
   000000000001000 -> 000000000001000
   000000000010000 -> 000000000010000
   000000000100000 -> 000000000100000
   000000001000000 -> 000000001000000
   000000010000000 -> 000000010000000
   000000100000000 -> 000000100000000
   000001000000000 -> 000001000000000
   000010000000000 -> 000010000000000
   000100000000000 -> 000100000000000
   001000000000000 -> 001000000000000
   010000000000000 -> 010000000000000
   100000000000000 -> 100000000000000
Encoding state machine work.lda_reg_sm(rtl)-tx_hdr_bytes[0:7]
original code -> new code
   0000000001 -> 00000001
   0000000010 -> 00000010
   0000000100 -> 00000100
   0000001000 -> 00001000
   0000010000 -> 00010000
   0000100000 -> 00100000
   0001000000 -> 01000000
   0010000000 -> 10000000
Encoding state machine work.lda_reg_sm(rtl)-hdr_mode[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
Encoding state machine work.lda_reg_sm(rtl)-hdr_bytes[0:6]
original code -> new code
   0000000001 -> 0000000001
   0000000010 -> 0000000010
   0000000100 -> 0000000100
   0000001000 -> 0000001000
   0000010000 -> 0000010000
   0000100000 -> 0000100000
   0001000000 -> 0001000000
Encoding state machine work.lda_reg_sm(rtl)-handle_memory_index_v[0:2]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@W:MO129 : lda_reg_sm.vhd(1258) | Sequential instance Main_Statemachine.Register_SM.hdr_bytes[7] has been reduced to a combinational gate by constant propagation
@W:MO129 : lda_reg_sm.vhd(1258) | Sequential instance Main_Statemachine.Register_SM.hdr_bytes[8] has been reduced to a combinational gate by constant propagation
@W:MO129 : lda_reg_sm.vhd(1258) | Sequential instance Main_Statemachine.Register_SM.hdr_bytes[9] has been reduced to a combinational gate by constant propagation
@W:BN132 : lda_reg_sm.vhd(546) | Removing instance Main_Statemachine.Register_SM.read_data_i[18],  because it is equivalent to instance Main_Statemachine.Register_SM.read_data_i[30]
@W:BN132 : lda_reg_sm.vhd(546) | Removing instance Main_Statemachine.Register_SM.read_data_i[16],  because it is equivalent to instance Main_Statemachine.Register_SM.read_data_i[25]
@N: : lda_reg_sm.vhd(206) | Found counter in view:work.lda_reg_sm(rtl) inst block_count_i[15:0]
@N: : lda_reg_sm.vhd(941) | Found counter in view:work.lda_reg_sm(rtl) inst bad_byte_count_i[5:0]
@N:MF179 : lda_reg_sm.vhd(251) | Found 16 bit by 16 bit '==' comparator, 'main_reg_state_machine\.un1_block_count_i'
Encoding state machine work.lda_dif_sm_work_md2_rtl_3layer0(rtl)-tx_state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
Encoding state machine work.lda_dif_sm_work_md2_rtl_3layer0(rtl)-rx_state_i[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@N: : lda_dif_sm.vhd(391) | Found counter in view:work.lda_dif_sm_work_md2_rtl_3layer0(rtl) inst dif_len_saved_i[10:0]
@N: : lda_dif_sm.vhd(391) | Found counter in view:work.lda_dif_sm_work_md2_rtl_3layer0(rtl) inst mem_wr_address_tmp_i[9:0]
@N: : lda_dif_sm.vhd(218) | Found counter in view:work.lda_dif_sm_work_md2_rtl_3layer0(rtl) inst mem_rd_address_i[9:0]
@W:MO161 : lda_dif_sm.vhd(218) | Register bit dif_out_len_i[0] is always 1, optimizing ...
@N:MF179 :  | Found 12 bit by 12 bit '==' comparator, 'dif_output_statemachine\.un4_dif_len_i' 
@N:MF179 : lda_dif_sm.vhd(429) | Found 11 bit by 11 bit '==' comparator, 'rx_state_machine\.un4_dif_len_saved_i'
@N:FX404 : tx_arbiter.vhd(89) | Found addmux in view:work.tx_arbiter(rtl) inst pkt_counter\.counter_i_5[7:0] from un1_counter_i_0_sqmuxa[7:0] 
Encoding state machine work.tx_client_fifo_work_md2_rtl_14layer0(rtl)-rd_state[0:6]
original code -> new code
   000000001 -> 0000001
   000000010 -> 0000010
   000000100 -> 0000100
   000001000 -> 0001000
   000010000 -> 0010000
   000100000 -> 0100000
   001000000 -> 1000000
Encoding state machine work.tx_client_fifo_work_md2_rtl_14layer0(rtl)-wr_state[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
@N: : tx_client_fifo.vhd(852) | Found counter in view:work.tx_client_fifo_work_md2_rtl_14layer0(rtl) inst rd_addr[11:0]
@N: : tx_client_fifo.vhd(706) | Found updn counter in view:work.tx_client_fifo_work_md2_rtl_14layer0(rtl) inst wr_frames[8:0] 
Encoding state machine work.packetgen_sm(rtl)-statemachine[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine work.packetgen_sm(rtl)-cnt[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
Encoding state machine work.packetgen_sm(rtl)-hdr_bytes[0:6]
original code -> new code
   0000000001 -> 0000000001
   0000000010 -> 0000000010
   0000000100 -> 0000000100
   0000001000 -> 0000001000
   0000010000 -> 0000010000
   0000100000 -> 0000100000
   0001000000 -> 0001000000
Encoding state machine work.packetgen_sm(rtl)-hdr_mode[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
Encoding state machine work.packetgen_sm(rtl)-tx_hdr_bytes[0:6]
original code -> new code
   0000000001 -> 0000001
   0000000010 -> 0000010
   0000000100 -> 0000100
   0000001000 -> 0001000
   0000010000 -> 0010000
   0000100000 -> 0100000
   0001000000 -> 1000000
@W:MO129 : packetgen_sm.vhd(298) | Sequential instance PacketGenerator.Generator_SM.hdr_bytes[7] has been reduced to a combinational gate by constant propagation
@W:MO129 : packetgen_sm.vhd(298) | Sequential instance PacketGenerator.Generator_SM.hdr_bytes[8] has been reduced to a combinational gate by constant propagation
@W:MO129 : packetgen_sm.vhd(298) | Sequential instance PacketGenerator.Generator_SM.hdr_bytes[9] has been reduced to a combinational gate by constant propagation
@N: : packetgen_sm.vhd(226) | Found counter in view:work.packetgen_sm(rtl) inst gen_delay_i[15:0]
@N: : packetgen_sm.vhd(247) | Found counter in view:work.packetgen_sm(rtl) inst gen_size_i[11:0]
@N: : packetgen_sm.vhd(275) | Found counter in view:work.packetgen_sm(rtl) inst gen_count_i[15:0]
@N: : lda_dif_links.vhd(339) | Found counter in view:work.lda_dif_links(rtl) inst word_clk_cnt_i[4:0]
Encoding state machine work.lda_protocol_sm_state_machine(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_0(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_0(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_0(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_0(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_0(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_0(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_0(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_0(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_1(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_1(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_1(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_1(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_1(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_1(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_1(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_1(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_2(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_2(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_2(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_2(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_2(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_2(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_2(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_2(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_3(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_3(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_3(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_3(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_3(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_3(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_3(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_3(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_4(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_4(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_4(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_4(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_4(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_4(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_4(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_4(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_5(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_5(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_5(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_5(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_5(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_5(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_5(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_5(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.lda_protocol_sm_state_machine_6(rtl)-state_i[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_6(rtl) inst word_counter_i[5:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_6(rtl) inst start_counter_i[4:0]
@N: : lda_protocol_sm.vhd(505) | Found counter in view:work.lda_protocol_sm_state_machine_6(rtl) inst init_counter_i[7:0]
@W:MO129 : lda_protocol_sm.vhd(323) | Sequential instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_k_i[1] has been reduced to a combinational gate by constant propagation
Encoding state machine work.link_sm_link_statemachine_6(rtl)-state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N: : link_sm.vhd(95) | Found counter in view:work.link_sm_link_statemachine_6(rtl) inst spio_count[7:0]
@W:MO161 : link_sm.vhd(171) | Register bit state_i[0] is always 0, optimizing ...
@N:BN116 : link_sm.vhd(95) | Removing sequential instance serial_loop_back_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.measure_delay_work_md2_rtl_6layer0_delay_calc_6(rtl)-delay_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : measure_delay.vhd(156) | Found counter in view:work.measure_delay_work_md2_rtl_6layer0_delay_calc_6(rtl) inst delay_index[4:0]
@N:MF179 : measure_delay.vhd(215) | Found 20 bit by 20 bit '==' comparator, 'statemachine_main\.delay_reg'
Encoding state machine work.domain_crossing_work_md2_rtl_7layer0(rtl)-state2_i[0:2]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
Encoding state machine work.domain_crossing_work_md2_rtl_7layer0(rtl)-state_i[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
@N:BN116 : domain_crossing.vhd(167) | Removing sequential instance read_buffer_i[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : domain_crossing.vhd(99) | Removing sequential instance domain_1_data_out[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.lda_mac_shim_shim_block(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_0(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_0(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_0(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_0(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_1(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_1(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_1(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_1(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_2(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_2(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_2(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_2(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_3(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_3(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_3(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_3(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_4(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_4(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_4(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_4(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_5(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_5(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_5(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_5(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_6(rtl)-tx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.lda_mac_shim_shim_block_6(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.dif_packet_packet_block_6(rtl)-tx_state_i[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine work.dif_packet_packet_block_6(rtl)-rx_state_i[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine work.ll_mux2_rx_Umux_a0(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_mux2_rx_Umux_a1(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_mux2_rx_Umux_a2(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_mux2_rx_Umux_a3(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_mux2_rx_Umux_b0(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_mux2_rx_Umux_b1(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_mux2_rx_Umux_c(rtl)-mux_machine[0:1]
original code -> new code
   01 -> 0
   10 -> 1
Encoding state machine work.ll_Arbiter(rtl)-arbiter_machine[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
@N:BN116 : ll_mux_ctrl_rtl.vhd(62) | Removing sequential instance arbiter_machine_i[8] of view:PrimLib.dff(prim) because there are no references to its outputs 
Encoding state machine work.tx_client_fifo_work_md2_rtl_14layer0_dif_mux_output_fifo(rtl)-rd_state[0:6]
original code -> new code
   000000001 -> 0000001
   000000010 -> 0000010
   000000100 -> 0000100
   000001000 -> 0001000
   000010000 -> 0010000
   000100000 -> 0100000
   001000000 -> 1000000
Encoding state machine work.tx_client_fifo_work_md2_rtl_14layer0_dif_mux_output_fifo(rtl)-wr_state[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
@N: : tx_client_fifo.vhd(852) | Found counter in view:work.tx_client_fifo_work_md2_rtl_14layer0_dif_mux_output_fifo(rtl) inst rd_addr[11:0]
@N: : tx_client_fifo.vhd(706) | Found updn counter in view:work.tx_client_fifo_work_md2_rtl_14layer0_dif_mux_output_fifo(rtl) inst wr_frames[8:0] 
Encoding state machine work.lda_spi_state(rtl)-spi_state_i[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@W:BN132 : lda_spi_state.vhd(160) | Removing instance SPI_SLAVE.SPI_Statemachine.tx_data_i[8],  because it is equivalent to instance SPI_SLAVE.SPI_Statemachine.tx_data_i[9]
@W:BN132 : lda_spi_state.vhd(128) | Removing instance SPI_SLAVE.SPI_Statemachine.tx_data[9],  because it is equivalent to instance SPI_SLAVE.SPI_Statemachine.tx_data[8]
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance pktgen_fifo.wr_fifo_status[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance pktgen_fifo.wr_fifo_status[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance pktgen_fifo.wr_fifo_status[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance pktgen_fifo.wr_fifo_status[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1205) | Removing sequential instance pktgen_fifo.wr_addr_diff[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1205) | Removing sequential instance pktgen_fifo.wr_addr_diff[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.3.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.3.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.3.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.7.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.7.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.7.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.1.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.1.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.1.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.8.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.8.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.8.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.5.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.5.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.5.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.6.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.6.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.6.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Encode8B10B.enable_del[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(107) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.rx_valid_del_i[2]
@W:BN132 : xilinx_encode_8b10b_wrapper.vhd(97) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Encode8B10B.enable_del[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.tx_valid_del_i[1]
@W:BN132 : link_sm.vhd(268) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.serdes.link_statemachine.parallel_rx_valid_del_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.rx_valid_del_i[4]
@W:BN132 : lda_serdes.vhd(299) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.serdes.rx_valid_del_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.enable_del[1]
@W:BN132 : lda_serdes.vhd(388) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.serdes.tx_valid_del_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Encode8B10B.enable_del[1]
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_tx_stb of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx_eof of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx_sof of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx_vld of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_data_rx[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_state.vhd(160) | Removing sequential instance SPI_SLAVE.SPI_Statemachine.usb_mode_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_core.vhd(101) | Removing sequential instance SPI_SLAVE.SPI_Shifter.spi_buffer_rx[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_core.vhd(101) | Removing sequential instance SPI_SLAVE.SPI_Shifter.spi_buffer_rx[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_spi_core.vhd(142) | Removing sequential instance SPI_SLAVE.SPI_Shifter.tx_data_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance dif_mux_output_fifo.wr_fifo_status[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance dif_mux_output_fifo.wr_fifo_status[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance dif_mux_output_fifo.wr_fifo_status[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance dif_mux_output_fifo.wr_fifo_status[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1205) | Removing sequential instance dif_mux_output_fifo.wr_addr_diff[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1205) | Removing sequential instance dif_mux_output_fifo.wr_addr_diff[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : domain_crossing.vhd(99) | Removing sequential instance dif_domain_crossing.write_buffer_i[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : domain_crossing.vhd(167) | Removing sequential instance dif_domain_crossing.domain_2_stb of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : domain_crossing.vhd(167) | Removing sequential instance dif_domain_crossing.domain_2_data_out[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_internal_registers.vhd(297) | Removing sequential instance LDA_Registers.lda_int_reg_enables[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : rx_arbiter.vhd(90) | Removing sequential instance RX_Packet_Filter.rx2_bad_frame of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : rx_arbiter.vhd(90) | Removing sequential instance RX_Packet_Filter.rx2_good_frame of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : gigethernet_host_statemachine.vhd(185) | Removing sequential instance Ethernet_autoneg_shim.HOSTAccess_SM.statemachine[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : gigethernet_xilinx.vhd(290) | Removing sequential instance Ethernet_Downlink.ewrap of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : gigethernet_xilinx.vhd(290) | Removing sequential instance Ethernet_Downlink.en_cdet of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Finished factoring (Time elapsed 0h:00m:18s; Memory used current: 193MB peak: 193MB)

@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(956) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.fifostatus[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(919) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.read_truegray[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(947) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addrr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(931) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rag_writesync[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : lda_reg_sm.vhd(546) | Removing sequential instance Main_Statemachine.Register_SM.lda_sm_dif_reg_data_out[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance SM_FIFOs.port1_tx_fifo.wr_fifo_status[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance SM_FIFOs.port1_tx_fifo.wr_fifo_status[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance SM_FIFOs.port1_tx_fifo.wr_fifo_status[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1292) | Removing sequential instance SM_FIFOs.port1_tx_fifo.wr_fifo_status[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1205) | Removing sequential instance SM_FIFOs.port1_tx_fifo.wr_addr_diff[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : tx_client_fifo.vhd(1205) | Removing sequential instance SM_FIFOs.port1_tx_fifo.wr_addr_diff[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : lda_protocol_sm.vhd(323) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_parallel_tx_en_i,  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_parallel_tx_en_i
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_slow_clock_offset_i[4],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[4]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_slow_clock_offset_i[3],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[3]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_slow_clock_offset_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[2]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_slow_clock_offset_i[1],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[1]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : lda_protocol_sm.vhd(217) | Removing instance DIF_Links.dif_link_modules.4.lda_mod.state_machine.sm_slow_clock_offset_i[0],  because it is equivalent to instance DIF_Links.dif_link_modules.2.lda_mod.state_machine.sm_slow_clock_offset_i[0]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.6.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.5.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.8.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.1.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.7.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.3.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
@W:BN132 : xilinx_decode_8b10b_wrapper.vhd(98) | Removing instance DIF_Links.dif_link_modules.2.lda_mod.serdes.Decode8B10B.sint_i[2],  because it is equivalent to instance DIF_Links.dif_link_modules.4.lda_mod.serdes.Decode8B10B.sint_i[2]
Adding property syn_io_slew, value "slow", to port gig_lockrefn
Adding property syn_io_slew, value "FAST", to port gig_lockrefn


#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================
                 sync_reset_in.rst_sr[0]:C              Not Done
                         pma_dcm_reset_i:C              Not Done
         dif_mux_output_fifo.wr_state[1]:C              Not Done
                 DIF_Links.dcm_locked2_i:C              Not Done
Ethernet_Downlink.rx_code_group0_rereg[1]:C              Not Done


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:21s; Memory used current: 180MB peak: 200MB)

@N:FX430 :  | Found 6 global buffers instantiated by user  
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:28s; Memory used current: 193MB peak: 200MB)

@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.0\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.1\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.2\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.5\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.3\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.6\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.4\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_RX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(789) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.rd_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : BRAM_fifo.vhd(843) | Removing sequential instance LDA_DIF_MACS.individual_mac_block\.7\.MAC.DIF_TX_FIFO.BRAM_GEN\.BRAMFIFO.B_RAM_FIFO.wr_addr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Starting Early Timing Optimization (Time elapsed 0h:00m:34s; Memory used current: 199MB peak: 200MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:54s; Memory used current: 200MB peak: 201MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:56s; Memory used current: 195MB peak: 201MB)

Finished preparing to map (Time elapsed 0h:01m:13s; Memory used current: 200MB peak: 201MB)

Finished technology mapping (Time elapsed 0h:01m:26s; Memory used current: 233MB peak: 245MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:01m:31s		    -0.48ns		16030 /     11896
   2		0h:01m:32s		    -0.48ns		16030 /     11896
   3		0h:01m:34s		    -0.48ns		16031 /     11896
   4		0h:01m:36s		    -0.48ns		16031 /     11896
   5		0h:01m:37s		    -0.48ns		16031 /     11896
   6		0h:01m:39s		    -0.48ns		16031 /     11896
------------------------------------------------------------

Timing driven replication report
@N:FX271 : md2.vhd(1100) | Instance "gb_reset_i" with 87 loads has been replicated 1 time(s) to improve timing 
@N:FX271 : md2.vhd(1102) | Instance "rst" with 8941 loads has been replicated 1 time(s) to improve timing 
@N:FX271 : md2.vhd(1100) | Instance "gb_reset_i" with 16 loads has been replicated 1 time(s) to improve timing 
@N:FX271 : md2.vhd(1102) | Instance "rst" with 239 loads has been replicated 3 time(s) to improve timing 
Added 6 Registers via timing driven replication
Added 0 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:02m:02s		    -0.48ns		16030 /     11902
   2		0h:02m:04s		    -0.48ns		16030 /     11902
Timing driven replication report
No replication required.

   3		0h:02m:06s		    -0.48ns		16030 /     11902
   4		0h:02m:07s		    -0.48ns		16030 /     11902
   5		0h:02m:09s		    -0.48ns		16030 /     11902
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:02m:13s		    -0.48ns		16030 /     11902
Timing driven replication report
No replication required.

   2		0h:02m:15s		    -0.48ns		16030 /     11902
   3		0h:02m:16s		    -0.48ns		16030 /     11902
   4		0h:02m:18s		    -0.48ns		16030 /     11902
------------------------------------------------------------

Net buffering Report for view:work.md2(rtl):
@N:FX103 : md2.vhd(1102) | Instance "rst_iso" with "706" loads has been replicated "2" time(s) due to a hard fanout limit of "250" 
Added 0 Buffers
Added 2 Registers via replication
Added 0 LUTs via replication

Net buffering Report for view:gig_eth_mac_v8_3_lib.gig_eth_mac_v8_3_gmac_gen_1_BU2(view_1):
No nets needed buffering.

Net buffering Report for view:gig_eth_mac_v8_3_lib.gig_eth_mac_v8_3(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:gig_eth_pcs_pma_v9_0_lib.gig_eth_pcs_pma_v9_0_gpcs_pma_gen_1_BU2(view_1):
No nets needed buffering.

Net buffering Report for view:gig_eth_pcs_pma_v9_0_lib.gig_eth_pcs_pma_v9_0(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_0(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_0(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_0(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_0(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_1(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_1(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_1(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_1(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_2(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_2(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_2(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_2(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_3(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_3(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_3(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_3(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_4(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_4(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_4(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_4(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_5(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_5(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_5(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_5(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Decode_decode_8b10b_xst_1_lib.S3_2000_8B10B_Decode_decode_8b10b_xst_1_BU2_6(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Decode_Decode8B10B_6(_view_1_compressed):
No nets needed buffering.

Net buffering Report for view:S3_2000_8B10B_Encode_encode_8b10b_xst_1_lib.S3_2000_8B10B_Encode_encode_8b10b_xst_1_BU2_6(view_1):
No nets needed buffering.

Net buffering Report for view:test_lib.S3_2000_8B10B_Encode_Encode8B10B_6(_view_1_compressed):
No nets needed buffering.

@N:MF322 :  | Retiming summary: 0 registers retimed to 0  

		#####  BEGIN RETIMING REPORT  #####

Retiming summary : 0 registers retimed to 0

Original and Pipelined registers replaced by retiming :
		None

New registers created by retiming :
		None


		#####   END RETIMING REPORT  #####

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:02m:21s; Memory used current: 236MB peak: 245MB)

@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.6\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.5\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.4\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@W:FX477 :  | rloc constraint ignored for DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_a0, as it is packed in IOB 
@N:FX164 :  | The option to pack flops in the IOB has not been specified  
Finished restoring hierarchy (Time elapsed 0h:02m:25s; Memory used current: 241MB peak: 245MB)

@W:BN105 :  | Cannot apply constraint xc_loc to cpld_expansionbus_r_w 
@W:BN105 :  | Cannot apply constraint syn_useioff to Ethernet_Downlink.rx_code_group_ddr* 
@W:BN105 :  | Cannot apply constraint KEEP to iice_inst_0.mdic_link_reg[0:36] 
Writing Analyst data base /home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/ll_mux2_rx.srm
@N:MF203 :  | Set autoconstraint_io  
Finished Writing Netlist Databases (Time elapsed 0h:02m:34s; Memory used current: 220MB peak: 245MB)

Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/netattr.txt] 
C-2009.06
C-2009.06
iprotect -vendor xilinx /home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/syntmp/gig_eth_pcs_pma_v9_0_syn_encrypt.edf /home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/gig_eth_pcs_pma_v9_0_syn.edf (/unix/local/xilinx/11.1/ISE/bin/lin64/iprotect)
C-2009.06
iprotect -vendor xilinx /home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/syntmp/gig_eth_mac_v8_3_syn_encrypt.edf /home/warren/calicedaq/LDA/firmware/syn/main/md2/rev_1/gig_eth_mac_v8_3_syn.edf (/unix/local/xilinx/11.1/ISE/bin/lin64/iprotect)
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:02m:43s; Memory used current: 222MB peak: 245MB)

Starting Writing Gated Clock Conversion Report (Time elapsed 0h:02m:44s; Memory used current: 218MB peak: 245MB)

@N:MF276 :  | Gated clock conversion enabled, but no gated clocks found in design  
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:02m:44s; Memory used current: 218MB peak: 245MB)

Starting Writing Generated Clock Conversion Report (Time elapsed 0h:02m:44s; Memory used current: 218MB peak: 245MB)

@N:MF333 :  | Generated clock conversion enabled, but no generated clocks found in design  
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:02m:44s; Memory used current: 218MB peak: 245MB)

Found clock main_dif_clk with period 20.00ns 
Found clock tlk_rx_clk with period 8.00ns 
Found clock md2|pma_dcm_clk1_i_derived_clock with period 16.00ns 
Found clock gtx125_clk with period 8.00ns 
Found clock rbc1_clk with period 16.00ns 
Found clock lda_dif_links|DCM_CLK90_BUF_derived_clock with period 20.00ns 
Found clock lda_dif_links|DCM_CLK0_BUF_derived_clock with period 20.00ns 
@W:MT246 : md2.vhd(1935) | Blackbox lda_wrap_dif_work_md2_rtl_0 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Mar 16 10:33:58 2010
#


Top view:               md2
Requested Frequency:    25.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    /home/warren/calicedaq/LDA/firmware/source/main/md2.sdc
                       /home/warren/calicedaq/LDA/firmware/source/main/md2_conv.sdc
                       
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 


Performance Summary 
*******************


Worst slack in design: -0.025

                                              Requested     Estimated     Requested     Estimated                Clock                           Clock              
Starting Clock                                Frequency     Frequency     Period        Period        Slack      Type                            Group              
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
gtx125_clk                                    125.0 MHz     127.6 MHz     8.000         7.837         0.163      declared                        clkgroup_gtx125_clk
lda_dif_links|DCM_CLK0_BUF_derived_clock      50.0 MHz      62.3 MHz      20.000        16.048        2.329      derived (from main_dif_clk)     clkgroup_dif_clk   
lda_dif_links|DCM_CLK90_BUF_derived_clock     50.0 MHz      478.9 MHz     20.000        2.088         13.434     derived (from main_dif_clk)     clkgroup_dif_clk   
main_dif_clk                                  50.0 MHz      469.2 MHz     20.000        2.131         17.869     declared                        clkgroup_dif_clk   
md2|pma_dcm_clk1_i_derived_clock              62.5 MHz      105.5 MHz     16.000        9.480         3.260      derived (from rbc1_clk)         clkgroup_rbc1_clk  
rbc1_clk                                      62.5 MHz      351.5 MHz     16.000        2.845         13.155     declared                        clkgroup_rbc1_clk  
tlk_rx_clk                                    125.0 MHz     NA            8.000         NA            NA         declared                        clkgroup_tlk_rx_clk
System                                        129.0 MHz     128.6 MHz     7.752         7.777         -0.025     system                          default_clkgroup6  
====================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                |    rise  to  rise    |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                   Ending                                     |  constraint  slack   |  constraint  slack   |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
gtx125_clk                                 gtx125_clk                                 |  8.000       0.163   |  No paths    -       |  No paths    -      |  No paths    -    
gtx125_clk                                 md2|pma_dcm_clk1_i_derived_clock           |  Diff grp    -       |  No paths    -       |  Diff grp    -      |  No paths    -    
gtx125_clk                                 lda_dif_links|DCM_CLK0_BUF_derived_clock   |  Diff grp    -       |  No paths    -       |  No paths    -      |  No paths    -    
main_dif_clk                               main_dif_clk                               |  20.000      5.869   |  No paths    -       |  No paths    -      |  No paths    -    
main_dif_clk                               lda_dif_links|DCM_CLK0_BUF_derived_clock   |  20.000      17.869  |  No paths    -       |  No paths    -      |  No paths    -    
rbc1_clk                                   rbc1_clk                                   |  16.000      13.155  |  No paths    -       |  No paths    -      |  No paths    -    
md2|pma_dcm_clk1_i_derived_clock           gtx125_clk                                 |  Diff grp    -       |  No paths    -       |  No paths    -      |  No paths    -    
md2|pma_dcm_clk1_i_derived_clock           md2|pma_dcm_clk1_i_derived_clock           |  16.000      11.260  |  16.000      15.976  |  No paths    -      |  8.000       3.260
lda_dif_links|DCM_CLK0_BUF_derived_clock   gtx125_clk                                 |  Diff grp    -       |  No paths    -       |  No paths    -      |  Diff grp    -    
lda_dif_links|DCM_CLK0_BUF_derived_clock   main_dif_clk                               |  20.000      5.910   |  No paths    -       |  No paths    -      |  No paths    -    
lda_dif_links|DCM_CLK0_BUF_derived_clock   lda_dif_links|DCM_CLK0_BUF_derived_clock   |  20.000      2.329   |  20.000      3.952   |  10.000      2.613  |  10.000      7.945
lda_dif_links|DCM_CLK90_BUF_derived_clock  lda_dif_links|DCM_CLK0_BUF_derived_clock   |  15.000      13.434  |  15.000      13.434  |  No paths    -      |  No paths    -    
lda_dif_links|DCM_CLK90_BUF_derived_clock  lda_dif_links|DCM_CLK90_BUF_derived_clock  |  20.000      19.024  |  20.000      19.024  |  No paths    -      |  No paths    -    
==============================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port                       Starting            User           Arrival     Required          
Name                       Reference           Constraint     Time        Time         Slack
                           Clock                                                            
--------------------------------------------------------------------------------------------
ccc_cont_in                System (rising)     NA             0.000       -0.025            
ccc_ftrig_in               System (rising)     NA             0.000       -0.025            
cpld_expansionbus[0]       System (rising)     NA             0.000       5.360             
cpld_expansionbus[1]       System (rising)     NA             0.000       5.360             
cpld_expansionbus[2]       System (rising)     NA             0.000       4.625             
cpld_expansionbus[4]       NA                  NA             NA          NA           NA   
cpld_expansionbus[5]       NA                  NA             NA          NA           NA   
cpld_expansionbus[6]       NA                  NA             NA          NA           NA   
cpld_expansionbus[7]       NA                  NA             NA          NA           NA   
cpld_expansionbus_a_dn     System (rising)     NA             0.000       15.609            
dif_clk_in                 NA                  NA             NA          NA           NA   
dif_serial_rx[1]           System (rising)     NA             0.000       17.360            
dif_serial_rx[2]           System (rising)     NA             0.000       17.360            
dif_serial_rx[3]           System (rising)     NA             0.000       17.360            
dif_serial_rx[4]           System (rising)     NA             0.000       17.360            
dif_serial_rx[5]           System (rising)     NA             0.000       17.360            
dif_serial_rx[6]           System (rising)     NA             0.000       17.360            
dif_serial_rx[7]           System (rising)     NA             0.000       17.360            
dif_serial_rx[8]           System (rising)     NA             0.000       17.360            
dif_serial_rx[9]           NA                  NA             NA          NA           NA   
dif_serial_rx[10]          NA                  NA             NA          NA           NA   
gig_rbc1                   NA                  NA             NA          NA           NA   
gig_rd[0]                  System (rising)     NA             0.000       15.976            
gig_rd[1]                  System (rising)     NA             0.000       15.976            
gig_rd[2]                  System (rising)     NA             0.000       15.976            
gig_rd[3]                  System (rising)     NA             0.000       15.976            
gig_rd[4]                  System (rising)     NA             0.000       15.976            
gig_rd[5]                  System (rising)     NA             0.000       15.976            
gig_rd[6]                  System (rising)     NA             0.000       15.976            
gig_rd[7]                  System (rising)     NA             0.000       15.976            
gig_rd[8]                  System (rising)     NA             0.000       15.976            
gig_rd[9]                  System (rising)     NA             0.000       15.976            
gig_syncen                 NA                  NA             NA          NA           NA   
main_reset                 System (rising)     NA             0.000       5.049             
refclk125                  NA                  NA             NA          NA           NA   
sdram_dq[0]                NA                  NA             NA          NA           NA   
sdram_dq[1]                NA                  NA             NA          NA           NA   
sdram_dq[2]                NA                  NA             NA          NA           NA   
sdram_dq[3]                NA                  NA             NA          NA           NA   
sdram_dq[4]                NA                  NA             NA          NA           NA   
sdram_dq[5]                NA                  NA             NA          NA           NA   
sdram_dq[6]                NA                  NA             NA          NA           NA   
sdram_dq[7]                NA                  NA             NA          NA           NA   
sdram_dq[8]                NA                  NA             NA          NA           NA   
sdram_dq[9]                NA                  NA             NA          NA           NA   
sdram_dq[10]               NA                  NA             NA          NA           NA   
sdram_dq[11]               NA                  NA             NA          NA           NA   
sdram_dq[12]               NA                  NA             NA          NA           NA   
sdram_dq[13]               NA                  NA             NA          NA           NA   
sdram_dq[14]               NA                  NA             NA          NA           NA   
sdram_dq[15]               NA                  NA             NA          NA           NA   
sdram_dq[16]               NA                  NA             NA          NA           NA   
sdram_dq[17]               NA                  NA             NA          NA           NA   
sdram_dq[18]               NA                  NA             NA          NA           NA   
sdram_dq[19]               NA                  NA             NA          NA           NA   
sdram_dq[20]               NA                  NA             NA          NA           NA   
sdram_dq[21]               NA                  NA             NA          NA           NA   
sdram_dq[22]               NA                  NA             NA          NA           NA   
sdram_dq[23]               NA                  NA             NA          NA           NA   
sdram_dq[24]               NA                  NA             NA          NA           NA   
sdram_dq[25]               NA                  NA             NA          NA           NA   
sdram_dq[26]               NA                  NA             NA          NA           NA   
sdram_dq[27]               NA                  NA             NA          NA           NA   
sdram_dq[28]               NA                  NA             NA          NA           NA   
sdram_dq[29]               NA                  NA             NA          NA           NA   
sdram_dq[30]               NA                  NA             NA          NA           NA   
sdram_dq[31]               NA                  NA             NA          NA           NA   
slow_clk_sync              System (rising)     NA             0.000       15.218            
tlk_rx[0]                  NA                  NA             NA          NA           NA   
tlk_rx[1]                  NA                  NA             NA          NA           NA   
tlk_rx[2]                  NA                  NA             NA          NA           NA   
tlk_rx[3]                  NA                  NA             NA          NA           NA   
tlk_rx[4]                  NA                  NA             NA          NA           NA   
tlk_rx[5]                  NA                  NA             NA          NA           NA   
tlk_rx[6]                  NA                  NA             NA          NA           NA   
tlk_rx[7]                  NA                  NA             NA          NA           NA   
tlk_rx[8]                  NA                  NA             NA          NA           NA   
tlk_rx[9]                  NA                  NA             NA          NA           NA   
tlk_rx[10]                 NA                  NA             NA          NA           NA   
tlk_rx[11]                 NA                  NA             NA          NA           NA   
tlk_rx[12]                 NA                  NA             NA          NA           NA   
tlk_rx[13]                 NA                  NA             NA          NA           NA   
tlk_rx[14]                 NA                  NA             NA          NA           NA   
tlk_rx[15]                 NA                  NA             NA          NA           NA   
tlk_rx_clk                 NA                  NA             NA          NA           NA   
tlk_rx_dv                  NA                  NA             NA          NA           NA   
tlk_rx_er                  NA                  NA             NA          NA           NA   
============================================================================================


Output Ports: 

Port                     Starting                                               User           Arrival     Required          
Name                     Reference                                              Constraint     Time        Time         Slack
                         Clock                                                                                               
-----------------------------------------------------------------------------------------------------------------------------
ccc_busy_out             System (rising)                                        NA             7.777       7.752             
ccc_spare_out            System (rising)                                        NA             7.777       7.752             
cpld_expansionbus[3]     gtx125_clk (rising)                                    NA             3.800       7.752             
cpld_expansionbus_cs     gtx125_clk (rising)                                    NA             3.800       7.752             
cpld_expansionbus_rw     NA                                                     NA             NA          NA           NA   
dif_serial_clk           lda_dif_links|DCM_CLK0_BUF_derived_clock (falling)     NA             3.800       7.752             
dif_serial_tx[1]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[2]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[3]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[4]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[5]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[6]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[7]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[8]         lda_dif_links|DCM_CLK0_BUF_derived_clock (rising)      NA             3.800       7.752             
dif_serial_tx[9]         NA                                                     NA             NA          NA           NA   
dif_serial_tx[10]        NA                                                     NA             NA          NA           NA   
gig_lockrefn             gtx125_clk (rising)                                    NA             7.397       7.752             
gig_td[0]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[1]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[2]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[3]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[4]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[5]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[6]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[7]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[8]                gtx125_clk (rising)                                    NA             1.101       7.752             
gig_td[9]                gtx125_clk (rising)                                    NA             1.101       7.752             
md2_led[1]               NA                                                     NA             NA          NA           NA   
md2_led[2]               NA                                                     NA             NA          NA           NA   
md2_led[3]               NA                                                     NA             NA          NA           NA   
md2_led[4]               NA                                                     NA             NA          NA           NA   
md2_led[5]               NA                                                     NA             NA          NA           NA   
sdram_a[0]               NA                                                     NA             NA          NA           NA   
sdram_a[1]               NA                                                     NA             NA          NA           NA   
sdram_a[2]               NA                                                     NA             NA          NA           NA   
sdram_a[3]               NA                                                     NA             NA          NA           NA   
sdram_a[4]               NA                                                     NA             NA          NA           NA   
sdram_a[5]               NA                                                     NA             NA          NA           NA   
sdram_a[6]               NA                                                     NA             NA          NA           NA   
sdram_a[7]               NA                                                     NA             NA          NA           NA   
sdram_a[8]               NA                                                     NA             NA          NA           NA   
sdram_a[9]               NA                                                     NA             NA          NA           NA   
sdram_a[10]              NA                                                     NA             NA          NA           NA   
sdram_a[11]              NA                                                     NA             NA          NA           NA   
sdram_ba[0]              NA                                                     NA             NA          NA           NA   
sdram_ba[1]              NA                                                     NA             NA          NA           NA   
sdram_cas                NA                                                     NA             NA          NA           NA   
sdram_cke                NA                                                     NA             NA          NA           NA   
sdram_clk                NA                                                     NA             NA          NA           NA   
sdram_cs                 NA                                                     NA             NA          NA           NA   
sdram_dqm[0]             NA                                                     NA             NA          NA           NA   
sdram_dqm[1]             NA                                                     NA             NA          NA           NA   
sdram_dqm[2]             NA                                                     NA             NA          NA           NA   
sdram_dqm[3]             NA                                                     NA             NA          NA           NA   
sdram_ras                NA                                                     NA             NA          NA           NA   
sdram_we                 NA                                                     NA             NA          NA           NA   
tlk_enable               NA                                                     NA             NA          NA           NA   
tlk_lockrefn             NA                                                     NA             NA          NA           NA   
tlk_tx[0]                NA                                                     NA             NA          NA           NA   
tlk_tx[1]                NA                                                     NA             NA          NA           NA   
tlk_tx[2]                NA                                                     NA             NA          NA           NA   
tlk_tx[3]                NA                                                     NA             NA          NA           NA   
tlk_tx[4]                NA                                                     NA             NA          NA           NA   
tlk_tx[5]                NA                                                     NA             NA          NA           NA   
tlk_tx[6]                NA                                                     NA             NA          NA           NA   
tlk_tx[7]                NA                                                     NA             NA          NA           NA   
tlk_tx[8]                NA                                                     NA             NA          NA           NA   
tlk_tx[9]                NA                                                     NA             NA          NA           NA   
tlk_tx[10]               NA                                                     NA             NA          NA           NA   
tlk_tx[11]               NA                                                     NA             NA          NA           NA   
tlk_tx[12]               NA                                                     NA             NA          NA           NA   
tlk_tx[13]               NA                                                     NA             NA          NA           NA   
tlk_tx[14]               NA                                                     NA             NA          NA           NA   
tlk_tx[15]               NA                                                     NA             NA          NA           NA   
tlk_tx_en                NA                                                     NA             NA          NA           NA   
tlk_tx_er                NA                                                     NA             NA          NA           NA   
user_led[0]              NA                                                     NA             NA          NA           NA   
user_led[1]              NA                                                     NA             NA          NA           NA   
user_led[2]              NA                                                     NA             NA          NA           NA   
user_led[3]              NA                                                     NA             NA          NA           NA   
=============================================================================================================================



====================================
Detailed Report for Clock: gtx125_clk
====================================



Starting Points with Worst Slack
********************************

                                              Starting                                               Arrival          
Instance                                      Reference      Type     Pin     Net                    Time        Slack
                                              Clock                                                                   
----------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[0]          gtx125_clk     FDCE     Q       tx_byte_count_i[0]     0.626       0.163
Main_Statemachine.tx_byte_count_i[1]          gtx125_clk     FDCE     Q       tx_byte_count_i[1]     0.626       0.166
Main_Statemachine.tx_byte_count_i[4]          gtx125_clk     FDCE     Q       tx_byte_count_i[4]     0.626       0.169
Main_Statemachine.tx_byte_count_i[5]          gtx125_clk     FDCE     Q       tx_byte_count_i[5]     0.626       0.169
Main_Statemachine.tx_byte_count_i[2]          gtx125_clk     FDCE     Q       tx_byte_count_i[2]     0.626       0.194
Main_Statemachine.tx_state_v[4]               gtx125_clk     FDP      Q       tx_state_v[4]          0.626       0.262
Main_Statemachine.tx_state_v[3]               gtx125_clk     FDC      Q       tx_state_v[3]          0.626       0.283
Main_Statemachine.tx_byte_count_i[3]          gtx125_clk     FDCE     Q       tx_byte_count_i[3]     0.626       0.309
gb_reset_i_fast                               gtx125_clk     FDS      Q       gb_reset_i_fast        0.626       0.355
SM_FIFOs.port1_rx_fifo.wr_rd_addr_gray[8]     gtx125_clk     FDR      Q       wr_rd_addr_gray[8]     0.626       0.407
======================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                          Starting                                                                                                         Required          
Instance                                                                                                  Reference      Type     Pin              Net                                                                     Time         Slack
                                                                                                          Clock                                                                                                                              
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[0]                                                                      gtx125_clk     FDCE     D                tx_byte_count_i_lm[0]                                                   7.904        0.163
Main_Statemachine.tx_byte_count_i[1]                                                                      gtx125_clk     FDCE     D                tx_byte_count_i_lm[1]                                                   7.904        0.275
Main_Statemachine.tx_byte_count_i[2]                                                                      gtx125_clk     FDCE     D                tx_byte_count_i_lm[2]                                                   7.904        0.275
gig_lockrefn                                                                                              gtx125_clk     Port     gig_lockrefn     gig_lockrefn                                                            7.752        0.355
SM_FIFOs.port1_rx_fifo.wr_addr_diff[11]                                                                   gtx125_clk     FDR      D                wr_addr_diff_1[11]                                                      7.904        0.407
Ethernet_Downlink.gig_eth_pcs_pma_core.BU2.U0.USE_TBI.PCS_OUTPUT.BASEX.RECLOCK_RX_DATA.RD_OCCUPANCY_3     gtx125_clk     FDR      D                U0.USE_TBI.PCS_OUTPUT.BASEX.RECLOCK_RX_DATA.RD_OCCUPANCY_sub0000[3]     4.824        0.432
SM_FIFOs.port1_rx_fifo.wr_addr_diff[10]                                                                   gtx125_clk     FDR      D                wr_addr_diff_1[10]                                                      7.904        0.459
SM_FIFOs.port1_rx_fifo.wr_addr_diff[9]                                                                    gtx125_clk     FDR      D                wr_addr_diff_1[9]                                                       7.904        0.511
Main_Statemachine.Dif_SM.dif_out_len_i[10]                                                                gtx125_clk     FDC      D                dif_out_len_i_4[10]                                                     7.904        0.542
SM_FIFOs.port1_rx_fifo.wr_addr_diff[8]                                                                    gtx125_clk     FDR      D                wr_addr_diff_1[8]                                                       7.904        0.563
=============================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      7.741
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.163

    Number of logic level(s):                6
    Starting point:                          Main_Statemachine.tx_byte_count_i[0] / Q
    Ending point:                            Main_Statemachine.tx_byte_count_i[0] / D
    The start point is clocked by            gtx125_clk [rising] on pin C
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                                                                        Pin      Pin               Arrival     No. of    
Name                                                                       Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[0]                                       FDCE       Q        Out     0.626     0.626       -         
tx_byte_count_i[0]                                                         Net        -        -       0.919     -           19        
Main_Statemachine.main_tx\.un22_main_tx_default_reply_start_i_0_a2_i_o2    LUT2       I0       In      -         1.545       -         
Main_Statemachine.main_tx\.un22_main_tx_default_reply_start_i_0_a2_i_o2    LUT2       O        Out     0.504     2.049       -         
N_2854                                                                     Net        -        -       0.836     -           6         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                       LUT4       I2       In      -         2.885       -         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                       LUT4       O        Out     0.504     3.389       -         
N_2303                                                                     Net        -        -       0.878     -           11        
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                LUT2       I1       In      -         4.267       -         
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                LUT2       O        Out     0.504     4.771       -         
tx_byte_count_i_3_sqmuxa_1                                                 Net        -        -       0.829     -           5         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                             LUT4_L     I0       In      -         5.599       -         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                             LUT4_L     LO       Out     0.504     6.103       -         
tx_byte_count_i_27_1_iv_0[0]                                               Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                LUT4_L     I3       In      -         6.418       -         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                LUT4_L     LO       Out     0.504     6.922       -         
tx_byte_count_i_lm_0_1[0]                                                  Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                  LUT4_L     I2       In      -         7.237       -         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                  LUT4_L     LO       Out     0.504     7.741       -         
tx_byte_count_i_lm[0]                                                      Net        -        -       0.000     -           1         
Main_Statemachine.tx_byte_count_i[0]                                       FDCE       D        In      -         7.741       -         
=======================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.837 is 3.746(47.8%) logic and 4.091(52.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      7.738
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.166

    Number of logic level(s):                6
    Starting point:                          Main_Statemachine.tx_byte_count_i[1] / Q
    Ending point:                            Main_Statemachine.tx_byte_count_i[0] / D
    The start point is clocked by            gtx125_clk [rising] on pin C
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                                                                        Pin      Pin               Arrival     No. of    
Name                                                                       Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[1]                                       FDCE       Q        Out     0.626     0.626       -         
tx_byte_count_i[1]                                                         Net        -        -       0.916     -           18        
Main_Statemachine.main_tx\.un22_main_tx_default_reply_start_i_0_a2_i_o2    LUT2       I1       In      -         1.542       -         
Main_Statemachine.main_tx\.un22_main_tx_default_reply_start_i_0_a2_i_o2    LUT2       O        Out     0.504     2.046       -         
N_2854                                                                     Net        -        -       0.836     -           6         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                       LUT4       I2       In      -         2.881       -         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                       LUT4       O        Out     0.504     3.385       -         
N_2303                                                                     Net        -        -       0.878     -           11        
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                LUT2       I1       In      -         4.263       -         
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                LUT2       O        Out     0.504     4.767       -         
tx_byte_count_i_3_sqmuxa_1                                                 Net        -        -       0.829     -           5         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                             LUT4_L     I0       In      -         5.596       -         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                             LUT4_L     LO       Out     0.504     6.100       -         
tx_byte_count_i_27_1_iv_0[0]                                               Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                LUT4_L     I3       In      -         6.415       -         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                LUT4_L     LO       Out     0.504     6.919       -         
tx_byte_count_i_lm_0_1[0]                                                  Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                  LUT4_L     I2       In      -         7.234       -         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                  LUT4_L     LO       Out     0.504     7.738       -         
tx_byte_count_i_lm[0]                                                      Net        -        -       0.000     -           1         
Main_Statemachine.tx_byte_count_i[0]                                       FDCE       D        In      -         7.738       -         
=======================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.834 is 3.746(47.8%) logic and 4.088(52.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      7.735
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.169

    Number of logic level(s):                6
    Starting point:                          Main_Statemachine.tx_byte_count_i[4] / Q
    Ending point:                            Main_Statemachine.tx_byte_count_i[0] / D
    The start point is clocked by            gtx125_clk [rising] on pin C
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                 Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[4]                                                 FDCE       Q        Out     0.626     0.626       -         
tx_byte_count_i[4]                                                                   Net        -        -       0.878     -           9         
Main_Statemachine.main_tx\.un132_main_tx_default_reply_start_i_1_2_0_i2_i_o2_0_o2    LUT2       I0       In      -         1.504       -         
Main_Statemachine.main_tx\.un132_main_tx_default_reply_start_i_1_2_0_i2_i_o2_0_o2    LUT2       O        Out     0.504     2.008       -         
N_74                                                                                 Net        -        -       0.871     -           9         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                                 LUT4       I0       In      -         2.879       -         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                                 LUT4       O        Out     0.504     3.383       -         
N_2303                                                                               Net        -        -       0.878     -           11        
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                          LUT2       I1       In      -         4.260       -         
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                          LUT2       O        Out     0.504     4.764       -         
tx_byte_count_i_3_sqmuxa_1                                                           Net        -        -       0.829     -           5         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                                       LUT4_L     I0       In      -         5.593       -         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                                       LUT4_L     LO       Out     0.504     6.097       -         
tx_byte_count_i_27_1_iv_0[0]                                                         Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                          LUT4_L     I3       In      -         6.412       -         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                          LUT4_L     LO       Out     0.504     6.916       -         
tx_byte_count_i_lm_0_1[0]                                                            Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                            LUT4_L     I2       In      -         7.231       -         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                            LUT4_L     LO       Out     0.504     7.735       -         
tx_byte_count_i_lm[0]                                                                Net        -        -       0.000     -           1         
Main_Statemachine.tx_byte_count_i[0]                                                 FDCE       D        In      -         7.735       -         
=================================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.831 is 3.746(47.8%) logic and 4.085(52.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      7.735
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.169

    Number of logic level(s):                6
    Starting point:                          Main_Statemachine.tx_byte_count_i[5] / Q
    Ending point:                            Main_Statemachine.tx_byte_count_i[0] / D
    The start point is clocked by            gtx125_clk [rising] on pin C
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                 Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[5]                                                 FDCE       Q        Out     0.626     0.626       -         
tx_byte_count_i[5]                                                                   Net        -        -       0.878     -           9         
Main_Statemachine.main_tx\.un132_main_tx_default_reply_start_i_1_2_0_i2_i_o2_0_o2    LUT2       I1       In      -         1.504       -         
Main_Statemachine.main_tx\.un132_main_tx_default_reply_start_i_1_2_0_i2_i_o2_0_o2    LUT2       O        Out     0.504     2.008       -         
N_74                                                                                 Net        -        -       0.871     -           9         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                                 LUT4       I0       In      -         2.879       -         
Main_Statemachine.un1_main_tx_packet_data_i_2_sqmuxa                                 LUT4       O        Out     0.504     3.383       -         
N_2303                                                                               Net        -        -       0.878     -           11        
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                          LUT2       I1       In      -         4.260       -         
Main_Statemachine.tx_byte_count_i_3_sqmuxa_1_0_a2_0_a3_0_a2                          LUT2       O        Out     0.504     4.764       -         
tx_byte_count_i_3_sqmuxa_1                                                           Net        -        -       0.829     -           5         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                                       LUT4_L     I0       In      -         5.593       -         
Main_Statemachine.tx_byte_count_i_27_1_iv_0[0]                                       LUT4_L     LO       Out     0.504     6.097       -         
tx_byte_count_i_27_1_iv_0[0]                                                         Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                          LUT4_L     I3       In      -         6.412       -         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                          LUT4_L     LO       Out     0.504     6.916       -         
tx_byte_count_i_lm_0_1[0]                                                            Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                            LUT4_L     I2       In      -         7.231       -         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                            LUT4_L     LO       Out     0.504     7.735       -         
tx_byte_count_i_lm[0]                                                                Net        -        -       0.000     -           1         
Main_Statemachine.tx_byte_count_i[0]                                                 FDCE       D        In      -         7.735       -         
=================================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.831 is 3.746(47.8%) logic and 4.085(52.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      7.721
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.183

    Number of logic level(s):                6
    Starting point:                          Main_Statemachine.tx_byte_count_i[4] / Q
    Ending point:                            Main_Statemachine.tx_byte_count_i[0] / D
    The start point is clocked by            gtx125_clk [rising] on pin C
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                 Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
Main_Statemachine.tx_byte_count_i[4]                                                 FDCE       Q        Out     0.626     0.626       -         
tx_byte_count_i[4]                                                                   Net        -        -       0.878     -           9         
Main_Statemachine.main_tx\.un132_main_tx_default_reply_start_i_1_2_0_i2_i_o2_0_o2    LUT2       I0       In      -         1.504       -         
Main_Statemachine.main_tx\.un132_main_tx_default_reply_start_i_1_2_0_i2_i_o2_0_o2    LUT2       O        Out     0.504     2.008       -         
N_74                                                                                 Net        -        -       0.871     -           9         
Main_Statemachine.un1_main_tx_packet_data_i_1_sqmuxa_0_0_o2                          LUT4       I0       In      -         2.879       -         
Main_Statemachine.un1_main_tx_packet_data_i_1_sqmuxa_0_0_o2                          LUT4       O        Out     0.504     3.383       -         
N_369                                                                                Net        -        -       0.829     -           5         
Main_Statemachine.tx_byte_count_i_2_sqmuxa_2_0_a2_0_a3_0_a2_m2_e                     LUT4       I0       In      -         4.211       -         
Main_Statemachine.tx_byte_count_i_2_sqmuxa_2_0_a2_0_a3_0_a2_m2_e                     LUT4       O        Out     0.504     4.715       -         
tx_byte_count_i_2_sqmuxa_2                                                           Net        -        -       0.864     -           8         
Main_Statemachine.tx_byte_count_i_lm_0_1_RNO[0]                                      LUT4       I0       In      -         5.579       -         
Main_Statemachine.tx_byte_count_i_lm_0_1_RNO[0]                                      LUT4       O        Out     0.504     6.083       -         
tx_byte_count_i_4_m_1[0]                                                             Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                          LUT4_L     I2       In      -         6.398       -         
Main_Statemachine.tx_byte_count_i_lm_0_1[0]                                          LUT4_L     LO       Out     0.504     6.902       -         
tx_byte_count_i_lm_0_1[0]                                                            Net        -        -       0.315     -           1         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                            LUT4_L     I2       In      -         7.217       -         
Main_Statemachine.tx_byte_count_i_lm_0[0]                                            LUT4_L     LO       Out     0.504     7.721       -         
tx_byte_count_i_lm[0]                                                                Net        -        -       0.000     -           1         
Main_Statemachine.tx_byte_count_i[0]                                                 FDCE       D        In      -         7.721       -         
=================================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.817 is 3.746(47.9%) logic and 4.071(52.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint




====================================
Detailed Report for Clock: lda_dif_links|DCM_CLK0_BUF_derived_clock
====================================



Starting Points with Worst Slack
********************************

                                                                          Starting                                                                                                  Arrival          
Instance                                                                  Reference                                    Type     Pin     Net                                         Time        Slack
                                                                          Clock                                                                                                                      
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.MDIO_CLK                lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.MDIO_CLK                0.626       2.329
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_CLK_REG        lda_dif_links|DCM_CLK0_BUF_derived_clock     FDC      Q       U0.MANIFGEN.MANAGEN.PHY.MDIO_CLK_REG        0.626       2.343
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.MDIO_REQ_INT            lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.MDIO_REQ_INT            0.626       2.385
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.ENABLE_REG          lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.PHY.ENABLE_REG          0.626       2.385
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_2       lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT[2]      0.626       2.613
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_4_1     lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_4_1     0.626       2.658
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_5_1     lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_5_1     0.626       2.679
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_5       lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT[5]      0.626       2.696
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_4       lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT[4]      0.626       2.699
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.OP_INT_1                lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE     Q       U0.MANIFGEN.MANAGEN.OP_INT[1]               0.626       2.729
=====================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                          Starting                                                                                                                      Required          
Instance                                                                  Reference                                    Type       Pin                  Net                                              Time         Slack
                                                                          Clock                                                                                                                                           
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT           lda_dif_links|DCM_CLK0_BUF_derived_clock     FDPE       CE                   U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001        7.476        2.329
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT            lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE_1     D                    U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING          7.904        2.613
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_5       lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE       D                    U0.MANIFGEN.MANAGEN.PHY.Mcount_STATE_COUNT15     7.824        3.398
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_5_1     lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE       D                    U0.MANIFGEN.MANAGEN.PHY.Mcount_STATE_COUNT15     7.824        3.398
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.ENABLE_REG          lda_dif_links|DCM_CLK0_BUF_derived_clock     FDCE       D                    U0.MANIFGEN.MANAGEN.MDIO_ENABLE                  7.904        3.851
dif_serial_tx[10:1]                                                       lda_dif_links|DCM_CLK0_BUF_derived_clock     Port       dif_serial_tx[1]     dif_serial_tx[1]                                 7.752        3.952
dif_serial_tx[10:1]                                                       lda_dif_links|DCM_CLK0_BUF_derived_clock     Port       dif_serial_tx[2]     dif_serial_tx[2]                                 7.752        3.952
dif_serial_tx[10:1]                                                       lda_dif_links|DCM_CLK0_BUF_derived_clock     Port       dif_serial_tx[3]     dif_serial_tx[3]                                 7.752        3.952
dif_serial_tx[10:1]                                                       lda_dif_links|DCM_CLK0_BUF_derived_clock     Port       dif_serial_tx[4]     dif_serial_tx[4]                                 7.752        3.952
dif_serial_tx[10:1]                                                       lda_dif_links|DCM_CLK0_BUF_derived_clock     Port       dif_serial_tx[5]     dif_serial_tx[5]                                 7.752        3.952
==========================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        8.000
    - Setup time:                            0.524
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.476

    - Propagation time:                      5.147
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.329

    Number of logic level(s):                4
    Starting point:                          Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.MDIO_CLK / Q
    Ending point:                            Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT / CE
    The start point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.MDIO_CLK                        FDCE      Q        Out     0.626     0.626       -         
U0.MANIFGEN.MANAGEN.MDIO_CLK                                                      Net       -        -       0.885     -           10        
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      I0       In      -         1.511       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      O        Out     0.504     2.015       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001_bdd1                                    Net       -        -       0.706     -           2         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      I1       In      -         2.721       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      O        Out     0.504     3.225       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014_map21                                  Net       -        -       0.315     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      I3       In      -         3.540       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      O        Out     0.504     4.044       -         
N4028                                                                             Net       -        -       0.000     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     I1       In      -         4.044       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     O        Out     0.339     4.383       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001                                         Net       -        -       0.764     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT                   FDPE      CE       In      -         5.147       -         
=============================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.671 is 3.001(52.9%) logic and 2.670(47.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        8.000
    - Setup time:                            0.524
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.476

    - Propagation time:                      5.133
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.343

    Number of logic level(s):                4
    Starting point:                          Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_CLK_REG / Q
    Ending point:                            Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT / CE
    The start point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_CLK_REG                FDC       Q        Out     0.626     0.626       -         
U0.MANIFGEN.MANAGEN.PHY.MDIO_CLK_REG                                              Net       -        -       0.871     -           7         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      I3       In      -         1.497       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      O        Out     0.504     2.001       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001_bdd1                                    Net       -        -       0.706     -           2         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      I1       In      -         2.707       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      O        Out     0.504     3.211       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014_map21                                  Net       -        -       0.315     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      I3       In      -         3.526       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      O        Out     0.504     4.030       -         
N4028                                                                             Net       -        -       0.000     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     I1       In      -         4.030       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     O        Out     0.339     4.369       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001                                         Net       -        -       0.764     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT                   FDPE      CE       In      -         5.133       -         
=============================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.657 is 3.001(53.0%) logic and 2.656(47.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        8.000
    - Setup time:                            0.524
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.476

    - Propagation time:                      5.091
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.385

    Number of logic level(s):                4
    Starting point:                          Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.MDIO_REQ_INT / Q
    Ending point:                            Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT / CE
    The start point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.MDIO_REQ_INT                    FDCE      Q        Out     0.626     0.626       -         
U0.MANIFGEN.MANAGEN.MDIO_REQ_INT                                                  Net       -        -       0.829     -           3         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      I2       In      -         1.455       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      O        Out     0.504     1.959       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001_bdd1                                    Net       -        -       0.706     -           2         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      I1       In      -         2.665       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      O        Out     0.504     3.169       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014_map21                                  Net       -        -       0.315     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      I3       In      -         3.484       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      O        Out     0.504     3.988       -         
N4028                                                                             Net       -        -       0.000     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     I1       In      -         3.988       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     O        Out     0.339     4.327       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001                                         Net       -        -       0.764     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT                   FDPE      CE       In      -         5.091       -         
=============================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.615 is 3.001(53.4%) logic and 2.614(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        8.000
    - Setup time:                            0.524
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.476

    - Propagation time:                      5.091
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.385

    Number of logic level(s):                4
    Starting point:                          Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.ENABLE_REG / Q
    Ending point:                            Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT / CE
    The start point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (from $mdio_logic to $host)

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.ENABLE_REG                  FDCE      Q        Out     0.626     0.626       -         
U0.MANIFGEN.MANAGEN.PHY.ENABLE_REG                                                Net       -        -       0.829     -           3         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      I1       In      -         1.455       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not000161         LUT4      O        Out     0.504     1.959       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001_bdd1                                    Net       -        -       0.706     -           2         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      I1       In      -         2.665       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001460        LUT4      O        Out     0.504     3.169       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014_map21                                  Net       -        -       0.315     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      I3       In      -         3.484       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165_G     LUT4      O        Out     0.504     3.988       -         
N4028                                                                             Net       -        -       0.000     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     I1       In      -         3.988       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT_not00014165       MUXF5     O        Out     0.339     4.327       -         
U0.MANIFGEN.MANAGEN.PHY.READY_INT_not0001                                         Net       -        -       0.764     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.READY_INT                   FDPE      CE       In      -         5.091       -         
=============================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.615 is 3.001(53.4%) logic and 2.614(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      5.291
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.613

    Number of logic level(s):                5
    Starting point:                          Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_2 / Q
    Ending point:                            Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT / D
    The start point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [falling] on pin C
    -Timing constraint applied as path with max delay 8.000000 (from $mdio_logic to $host)

Instance / Net                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT_2                 FDCE       Q        Out     0.626     0.626       -         
U0.MANIFGEN.MANAGEN.PHY.STATE_COUNT[2]                                              Net        -        -       0.916     -           18        
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1687_F_SW0     LUT4       I3       In      -         1.542       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1687_F_SW0     LUT4       O        Out     0.504     2.046       -         
N3902                                                                               Net        -        -       0.315     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1687_F         LUT4       I3       In      -         2.361       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1687_F         LUT4       O        Out     0.504     2.865       -         
N3887                                                                               Net        -        -       0.000     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1687           MUXF5      I0       In      -         2.865       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1687           MUXF5      O        Out     0.339     3.204       -         
U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1_map139                                     Net        -        -       0.764     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1716           LUT4_L     I3       In      -         3.968       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1716           LUT4_L     LO       Out     0.504     4.472       -         
U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1_map142                                     Net        -        -       0.315     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1746           LUT4       I3       In      -         4.787       -         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING1746           LUT4       O        Out     0.504     5.291       -         
U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT_RISING                                             Net        -        -       0.000     -           1         
Ethernet_Downlink.gig_mac.BU2.U0.MANIFGEN.MANAGEN.PHY.MDIO_OUT                      FDCE_1     D        In      -         5.291       -         
================================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.387 is 3.077(57.1%) logic and 2.310(42.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint




====================================
Detailed Report for Clock: lda_dif_links|DCM_CLK90_BUF_derived_clock
====================================



Starting Points with Worst Slack
********************************

                                                                           Starting                                                                 Arrival           
Instance                                                                   Reference                                     Type     Pin     Net       Time        Slack 
                                                                           Clock                                                                                      
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.5\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.6\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.4\.lda_mod.serdes.data_recovery_module.ff_b0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       bz[0]     0.626       13.434
DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_d0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       dz[0]     0.626       13.434
DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_d0   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      Q       dz[0]     0.626       13.434
======================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                           Starting                                                                 Required           
Instance                                                                   Reference                                     Type     Pin     Net       Time         Slack 
                                                                           Clock                                                                                       
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.5\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.6\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.4\.lda_mod.serdes.data_recovery_module.ff_b1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       bz[0]     14.824       13.434
DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_d1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       dz[0]     14.824       13.434
DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_d1   lda_dif_links|DCM_CLK90_BUF_derived_clock     FDC      D       dz[0]     14.824       13.434
=======================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        15.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         14.824

    - Propagation time:                      1.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.434

    Number of logic level(s):                0
    Starting point:                          DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_b0 / Q
    Ending point:                            DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_b1 / D
    The start point is clocked by            lda_dif_links|DCM_CLK90_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_b0   FDC      Q        Out     0.626     0.626       -         
bz[0]                                                                      Net      -        -       0.764     -           1         
DIF_Links.dif_link_modules\.2\.lda_mod.serdes.data_recovery_module.ff_b1   FDC      D        In      -         1.390       -         
=====================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 1.566 is 0.802(51.2%) logic and 0.764(48.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        15.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         14.824

    - Propagation time:                      1.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.434

    Number of logic level(s):                0
    Starting point:                          DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_b0 / Q
    Ending point:                            DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_b1 / D
    The start point is clocked by            lda_dif_links|DCM_CLK90_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_b0   FDC      Q        Out     0.626     0.626       -         
bz[0]                                                                      Net      -        -       0.764     -           1         
DIF_Links.dif_link_modules\.3\.lda_mod.serdes.data_recovery_module.ff_b1   FDC      D        In      -         1.390       -         
=====================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 1.566 is 0.802(51.2%) logic and 0.764(48.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        15.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         14.824

    - Propagation time:                      1.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.434

    Number of logic level(s):                0
    Starting point:                          DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_b0 / Q
    Ending point:                            DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_b1 / D
    The start point is clocked by            lda_dif_links|DCM_CLK90_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_b0   FDC      Q        Out     0.626     0.626       -         
bz[0]                                                                      Net      -        -       0.764     -           1         
DIF_Links.dif_link_modules\.7\.lda_mod.serdes.data_recovery_module.ff_b1   FDC      D        In      -         1.390       -         
=====================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 1.566 is 0.802(51.2%) logic and 0.764(48.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        15.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         14.824

    - Propagation time:                      1.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.434

    Number of logic level(s):                0
    Starting point:                          DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_b0 / Q
    Ending point:                            DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_b1 / D
    The start point is clocked by            lda_dif_links|DCM_CLK90_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_b0   FDC      Q        Out     0.626     0.626       -         
bz[0]                                                                      Net      -        -       0.764     -           1         
DIF_Links.dif_link_modules\.1\.lda_mod.serdes.data_recovery_module.ff_b1   FDC      D        In      -         1.390       -         
=====================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 1.566 is 0.802(51.2%) logic and 0.764(48.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        15.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         14.824

    - Propagation time:                      1.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.434

    Number of logic level(s):                0
    Starting point:                          DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_b0 / Q
    Ending point:                            DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_b1 / D
    The start point is clocked by            lda_dif_links|DCM_CLK90_BUF_derived_clock [rising] on pin C
    The end   point is clocked by            lda_dif_links|DCM_CLK0_BUF_derived_clock [rising] on pin C

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_b0   FDC      Q        Out     0.626     0.626       -         
bz[0]                                                                      Net      -        -       0.764     -           1         
DIF_Links.dif_link_modules\.8\.lda_mod.serdes.data_recovery_module.ff_b1   FDC      D        In      -         1.390       -         
=====================================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 1.566 is 0.802(51.2%) logic and 0.764(48.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint




====================================
Detailed Report for Clock: main_dif_clk
====================================



Starting Points with Worst Slack
********************************

                             Starting                                             Arrival          
Instance                     Reference        Type     Pin     Net                Time        Slack
                             Clock                                                                 
---------------------------------------------------------------------------------------------------
DIF_Links.dcm_locked2_i      main_dif_clk     FDC      Q       dcm_locked2_i      0.626       5.869
DIF_Links.dcm_reset_i[0]     main_dif_clk     FDP      Q       dcm_reset_i[0]     0.626       5.974
DIF_Links.dcm_reset_i[1]     main_dif_clk     FDC      Q       dcm_reset_i[1]     0.626       5.974
DIF_Links.dcm_reset_i[2]     main_dif_clk     FDC      Q       dcm_reset_i[2]     0.626       5.974
DIF_Links.dcm_reset_i[3]     main_dif_clk     FDC      Q       dcm_reset_i[3]     0.626       5.974
DIF_Links.dcm_reset_i[4]     main_dif_clk     FDC      Q       dcm_reset_i[4]     0.626       5.974
===================================================================================================


Ending Points with Worst Slack
******************************

                                                                    Starting                                                   Required           
Instance                                                            Reference        Type     Pin     Net                      Time         Slack 
                                                                    Clock                                                                         
--------------------------------------------------------------------------------------------------------------------------------------------------
DIF_Links.dcm_reset_i[0]                                            main_dif_clk     FDP      D       un3_dcm_locked_i_i_i     7.904        5.869 
DIF_Links.dcm_reset_i[1]                                            main_dif_clk     FDC      D       dcm_reset_i_3[1]         7.904        5.869 
DIF_Links.dcm_reset_i[2]                                            main_dif_clk     FDC      D       dcm_reset_i_3[2]         7.904        5.869 
DIF_Links.dcm_reset_i[3]                                            main_dif_clk     FDC      D       dcm_reset_i_3[3]         7.904        5.869 
DIF_Links.dcm_reset_i[4]                                            main_dif_clk     FDC      D       dcm_reset_i_3[4]         7.904        5.869 
DIF_Links.dcm_reset_i[5]                                            main_dif_clk     FDC      D       dcm_reset_i_3[5]         7.904        5.869 
DIF_Links.dif_link_modules\.7\.lda_mod.state_machine.go_to_init_i   main_dif_clk     FDS      D       go_to_init_is            19.904       17.869
DIF_Links.dif_link_modules\.1\.lda_mod.state_machine.go_to_init_i   main_dif_clk     FDS      D       go_to_init_is            19.904       17.869
DIF_Links.dif_link_modules\.2\.lda_mod.state_machine.go_to_init_i   main_dif_clk     FDS      D       go_to_init_is            19.904       17.869
DIF_Links.dif_link_modules\.3\.lda_mod.state_machine.go_to_init_i   main_dif_clk     FDS      D       go_to_init_is            19.904       17.869
==================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      2.035
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.869

    Number of logic level(s):                1
    Starting point:                          DIF_Links.dcm_locked2_i / Q
    Ending point:                            DIF_Links.dcm_reset_i[1] / D
    The start point is clocked by            main_dif_clk [rising] on pin C
    The end   point is clocked by            main_dif_clk [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                           Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
DIF_Links.dcm_locked2_i        FDC        Q        Out     0.626     0.626       -         
dcm_locked2_i                  Net        -        -       0.905     -           15        
DIF_Links.dcm_reset_i_3[1]     LUT4_L     I0       In      -         1.531       -         
DIF_Links.dcm_reset_i_3[1]     LUT4_L     LO       Out     0.504     2.035       -         
dcm_reset_i_3[1]               Net        -        -       0.000     -           1         
DIF_Links.dcm_reset_i[1]       FDC        D        In      -         2.035       -         
===========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.131 is 1.226(57.5%) logic and 0.905(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      2.035
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.869

    Number of logic level(s):                1
    Starting point:                          DIF_Links.dcm_locked2_i / Q
    Ending point:                            DIF_Links.dcm_reset_i[5] / D
    The start point is clocked by            main_dif_clk [rising] on pin C
    The end   point is clocked by            main_dif_clk [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                           Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
DIF_Links.dcm_locked2_i        FDC        Q        Out     0.626     0.626       -         
dcm_locked2_i                  Net        -        -       0.905     -           15        
DIF_Links.dcm_reset_i_3[5]     LUT4_L     I0       In      -         1.531       -         
DIF_Links.dcm_reset_i_3[5]     LUT4_L     LO       Out     0.504     2.035       -         
dcm_reset_i_3[5]               Net        -        -       0.000     -           1         
DIF_Links.dcm_reset_i[5]       FDC        D        In      -         2.035       -         
===========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.131 is 1.226(57.5%) logic and 0.905(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      2.035
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.869

    Number of logic level(s):                1
    Starting point:                          DIF_Links.dcm_locked2_i / Q
    Ending point:                            DIF_Links.dcm_reset_i[4] / D
    The start point is clocked by            main_dif_clk [rising] on pin C
    The end   point is clocked by            main_dif_clk [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                           Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
DIF_Links.dcm_locked2_i        FDC        Q        Out     0.626     0.626       -         
dcm_locked2_i                  Net        -        -       0.905     -           15        
DIF_Links.dcm_reset_i_3[4]     LUT4_L     I0       In      -         1.531       -         
DIF_Links.dcm_reset_i_3[4]     LUT4_L     LO       Out     0.504     2.035       -         
dcm_reset_i_3[4]               Net        -        -       0.000     -           1         
DIF_Links.dcm_reset_i[4]       FDC        D        In      -         2.035       -         
===========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.131 is 1.226(57.5%) logic and 0.905(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      2.035
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.869

    Number of logic level(s):                1
    Starting point:                          DIF_Links.dcm_locked2_i / Q
    Ending point:                            DIF_Links.dcm_reset_i[3] / D
    The start point is clocked by            main_dif_clk [rising] on pin C
    The end   point is clocked by            main_dif_clk [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                           Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
DIF_Links.dcm_locked2_i        FDC        Q        Out     0.626     0.626       -         
dcm_locked2_i                  Net        -        -       0.905     -           15        
DIF_Links.dcm_reset_i_3[3]     LUT4_L     I0       In      -         1.531       -         
DIF_Links.dcm_reset_i_3[3]     LUT4_L     LO       Out     0.504     2.035       -         
dcm_reset_i_3[3]               Net        -        -       0.000     -           1         
DIF_Links.dcm_reset_i[3]       FDC        D        In      -         2.035       -         
===========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.131 is 1.226(57.5%) logic and 0.905(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      2.035
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.869

    Number of logic level(s):                1
    Starting point:                          DIF_Links.dcm_locked2_i / Q
    Ending point:                            DIF_Links.dcm_reset_i[2] / D
    The start point is clocked by            main_dif_clk [rising] on pin C
    The end   point is clocked by            main_dif_clk [rising] on pin C
    -Timing constraint applied as path with max delay 8.000000 (to $host)

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                           Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
DIF_Links.dcm_locked2_i        FDC        Q        Out     0.626     0.626       -         
dcm_locked2_i                  Net        -        -       0.905     -           15        
DIF_Links.dcm_reset_i_3[2]     LUT4_L     I0       In      -         1.531       -         
DIF_Links.dcm_reset_i_3[2]     LUT4_L     LO       Out     0.504     2.035       -         
dcm_reset_i_3[2]               Net        -        -       0.000     -           1         
DIF_Links.dcm_reset_i[2]       FDC        D        In      -         2.035       -         
===========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.131 is 1.226(57.5%) logic and 0.905(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint




====================================
Detailed Report for Clock: md2|pma_dcm_clk1_i_derived_clock
====================================



Starting Points with Worst Slack
********************************

                                                        Starting                                                                            Arrival          
Instance                                                Reference                            Type         Pin     Net                       Time        Slack
                                                        Clock                                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.DDR_PMA_Input\.0\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q0      rx_code_group0_reg[0]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.0\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q1      rx_code_group1_reg[0]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.1\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q0      rx_code_group0_reg[1]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.1\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q1      rx_code_group1_reg[1]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.2\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q0      rx_code_group0_reg[2]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.2\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q1      rx_code_group1_reg[2]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.3\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q0      rx_code_group0_reg[3]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.3\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q1      rx_code_group1_reg[3]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.4\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q0      rx_code_group0_reg[4]     3.800       3.260
Ethernet_Downlink.DDR_PMA_Input\.4\.rx_code_group_ddr   md2|pma_dcm_clk1_i_derived_clock     IFDDRCPE     Q1      rx_code_group1_reg[4]     3.800       3.260
=============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                              Starting                                                                        Required          
Instance                                      Reference                            Type     Pin     Net                       Time         Slack
                                              Clock                                                                                             
------------------------------------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.rx_code_group0_rereg[0]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[0]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[1]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[1]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[2]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[2]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[3]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[3]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[4]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[4]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[5]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[5]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[6]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[6]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[7]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[7]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[8]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[8]     7.824        3.260
Ethernet_Downlink.rx_code_group0_rereg[9]     md2|pma_dcm_clk1_i_derived_clock     FD       D       rx_code_group0_reg[9]     7.824        3.260
================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        8.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.824

    - Propagation time:                      4.564
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.260

    Number of logic level(s):                0
    Starting point:                          Ethernet_Downlink.DDR_PMA_Input\.0\.rx_code_group_ddr / Q0
    Ending point:                            Ethernet_Downlink.rx_code_group0_rereg[0] / D
    The start point is clocked by            md2|pma_dcm_clk1_i_derived_clock [falling] on pin C0
    The end   point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.DDR_PMA_Input\.0\.rx_code_group_ddr   IFDDRCPE     Q0       Out     3.800     3.800       -         
rx_code_group0_reg[0]                                   Net          -        -       0.764     -           1         
Ethernet_Downlink.rx_code_group0_rereg[0]               FD           D        In      -         4.564       -         
======================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 4.740 is 3.976(83.9%) logic and 0.764(16.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        16.000
    - Setup time:                            8.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.824

    - Propagation time:                      4.564
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.260

    Number of logic level(s):                0
    Starting point:                          Ethernet_Downlink.DDR_PMA_Input\.0\.rx_code_group_ddr / Q1
    Ending point:                            Ethernet_Downlink.rx_code_group1_rereg[0] / D
    The start point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C0
    The end   point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.DDR_PMA_Input\.0\.rx_code_group_ddr   IFDDRCPE     Q1       Out     3.800     3.800       -         
rx_code_group1_reg[0]                                   Net          -        -       0.764     -           1         
Ethernet_Downlink.rx_code_group1_rereg[0]               FD           D        In      -         4.564       -         
======================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 12.740 is 11.976(94.0%) logic and 0.764(6.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        8.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.824

    - Propagation time:                      4.564
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.260

    Number of logic level(s):                0
    Starting point:                          Ethernet_Downlink.DDR_PMA_Input\.1\.rx_code_group_ddr / Q0
    Ending point:                            Ethernet_Downlink.rx_code_group0_rereg[1] / D
    The start point is clocked by            md2|pma_dcm_clk1_i_derived_clock [falling] on pin C0
    The end   point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.DDR_PMA_Input\.1\.rx_code_group_ddr   IFDDRCPE     Q0       Out     3.800     3.800       -         
rx_code_group0_reg[1]                                   Net          -        -       0.764     -           1         
Ethernet_Downlink.rx_code_group0_rereg[1]               FD           D        In      -         4.564       -         
======================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 4.740 is 3.976(83.9%) logic and 0.764(16.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        16.000
    - Setup time:                            8.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.824

    - Propagation time:                      4.564
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.260

    Number of logic level(s):                0
    Starting point:                          Ethernet_Downlink.DDR_PMA_Input\.1\.rx_code_group_ddr / Q1
    Ending point:                            Ethernet_Downlink.rx_code_group1_rereg[1] / D
    The start point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C0
    The end   point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.DDR_PMA_Input\.1\.rx_code_group_ddr   IFDDRCPE     Q1       Out     3.800     3.800       -         
rx_code_group1_reg[1]                                   Net          -        -       0.764     -           1         
Ethernet_Downlink.rx_code_group1_rereg[1]               FD           D        In      -         4.564       -         
======================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 12.740 is 11.976(94.0%) logic and 0.764(6.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        8.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.824

    - Propagation time:                      4.564
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.260

    Number of logic level(s):                0
    Starting point:                          Ethernet_Downlink.DDR_PMA_Input\.2\.rx_code_group_ddr / Q0
    Ending point:                            Ethernet_Downlink.rx_code_group0_rereg[2] / D
    The start point is clocked by            md2|pma_dcm_clk1_i_derived_clock [falling] on pin C0
    The end   point is clocked by            md2|pma_dcm_clk1_i_derived_clock [rising] on pin C

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
Ethernet_Downlink.DDR_PMA_Input\.2\.rx_code_group_ddr   IFDDRCPE     Q0       Out     3.800     3.800       -         
rx_code_group0_reg[2]                                   Net          -        -       0.764     -           1         
Ethernet_Downlink.rx_code_group0_rereg[2]               FD           D        In      -         4.564       -         
======================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 4.740 is 3.976(83.9%) logic and 0.764(16.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint




====================================
Detailed Report for Clock: rbc1_clk
====================================



Starting Points with Worst Slack
********************************

                           Starting                                                  Arrival           
Instance                   Reference     Type     Pin     Net                        Time        Slack 
                           Clock                                                                       
-------------------------------------------------------------------------------------------------------
pma_dcm_reset_sr_i[0]      rbc1_clk      FDP      Q       pma_dcm_reset_sr_i[0]      0.626       13.155
pma_dcm_reset_sr_i[1]      rbc1_clk      FDP      Q       pma_dcm_reset_sr_i[1]      0.626       13.155
pma_dcm_locked_sr_i[1]     rbc1_clk      FDC      Q       pma_dcm_locked_sr_i[1]     0.626       13.974
pma_dcm_reset_sr_i[2]      rbc1_clk      FDP      Q       pma_dcm_reset_sr_i[2]      0.626       13.974
pma_dcm_reset_sr_i[3]      rbc1_clk      FDP      Q       pma_dcm_reset_sr_i[3]      0.626       13.974
pma_dcm_locked_sr_i[2]     rbc1_clk      FDC      Q       pma_dcm_locked_sr_i[2]     0.626       14.010
pma_dcm_reset_sr_i[4]      rbc1_clk      FDP      Q       pma_dcm_reset_sr_i[4]      0.626       14.010
pma_dcm_locked_sr_i[0]     rbc1_clk      FDC      Q       pma_dcm_locked_sr_i[0]     0.626       14.434
=======================================================================================================


Ending Points with Worst Slack
******************************

                           Starting                                                             Required           
Instance                   Reference     Type     Pin     Net                                   Time         Slack 
                           Clock                                                                                   
-------------------------------------------------------------------------------------------------------------------
pma_dcm_reset_i            rbc1_clk      FDCP     D       N_68_i                                15.904       13.155
pma_dcm_reset_sr_i[0]      rbc1_clk      FDP      D       reset_dcm\.pma_dcm_reset_sr_i_2[0]    15.904       13.974
pma_dcm_locked_sr_i[2]     rbc1_clk      FDC      D       pma_dcm_locked_sr_i[1]                15.824       14.398
pma_dcm_reset_sr_i[1]      rbc1_clk      FDP      D       pma_dcm_reset_sr_i[0]                 15.824       14.398
pma_dcm_reset_sr_i[2]      rbc1_clk      FDP      D       pma_dcm_reset_sr_i[1]                 15.824       14.398
pma_dcm_reset_sr_i[3]      rbc1_clk      FDP      D       pma_dcm_reset_sr_i[2]                 15.824       14.398
pma_dcm_reset_sr_i[4]      rbc1_clk      FDP      D       pma_dcm_reset_sr_i[3]                 15.824       14.398
pma_dcm_locked_sr_i[1]     rbc1_clk      FDC      D       pma_dcm_locked_sr_i[0]                15.824       14.434
===================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        16.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.904

    - Propagation time:                      2.749
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.155

    Number of logic level(s):                2
    Starting point:                          pma_dcm_reset_sr_i[0] / Q
    Ending point:                            pma_dcm_reset_i / D
    The start point is clocked by            rbc1_clk [rising] on pin C
    The end   point is clocked by            rbc1_clk [rising] on pin C

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                              Type       Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
pma_dcm_reset_sr_i[0]             FDP        Q        Out     0.626     0.626       -         
pma_dcm_reset_sr_i[0]             Net        -        -       0.800     -           2         
reset_dcm\.pma_dcm_reset_i_1_1    LUT2_L     I0       In      -         1.426       -         
reset_dcm\.pma_dcm_reset_i_1_1    LUT2_L     LO       Out     0.504     1.930       -         
reset_dcm\.pma_dcm_reset_i_1_1    Net        -        -       0.315     -           1         
pma_dcm_reset_i_RNO               LUT4_L     I3       In      -         2.245       -         
pma_dcm_reset_i_RNO               LUT4_L     LO       Out     0.504     2.749       -         
N_68_i                            Net        -        -       0.000     -           1         
pma_dcm_reset_i                   FDCP       D        In      -         2.749       -         
==============================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.845 is 1.730(60.8%) logic and 1.115(39.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        16.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.904

    - Propagation time:                      2.749
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.155

    Number of logic level(s):                2
    Starting point:                          pma_dcm_reset_sr_i[1] / Q
    Ending point:                            pma_dcm_reset_i / D
    The start point is clocked by            rbc1_clk [rising] on pin C
    The end   point is clocked by            rbc1_clk [rising] on pin C

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                              Type       Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
pma_dcm_reset_sr_i[1]             FDP        Q        Out     0.626     0.626       -         
pma_dcm_reset_sr_i[1]             Net        -        -       0.800     -           2         
reset_dcm\.pma_dcm_reset_i_1_1    LUT2_L     I1       In      -         1.426       -         
reset_dcm\.pma_dcm_reset_i_1_1    LUT2_L     LO       Out     0.504     1.930       -         
reset_dcm\.pma_dcm_reset_i_1_1    Net        -        -       0.315     -           1         
pma_dcm_reset_i_RNO               LUT4_L     I3       In      -         2.245       -         
pma_dcm_reset_i_RNO               LUT4_L     LO       Out     0.504     2.749       -         
N_68_i                            Net        -        -       0.000     -           1         
pma_dcm_reset_i                   FDCP       D        In      -         2.749       -         
==============================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.845 is 1.730(60.8%) logic and 1.115(39.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        16.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.904

    - Propagation time:                      1.930
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.974

    Number of logic level(s):                1
    Starting point:                          pma_dcm_locked_sr_i[1] / Q
    Ending point:                            pma_dcm_reset_sr_i[0] / D
    The start point is clocked by            rbc1_clk [rising] on pin C
    The end   point is clocked by            rbc1_clk [rising] on pin C

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                  Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
pma_dcm_locked_sr_i[1]                FDC        Q        Out     0.626     0.626       -         
pma_dcm_locked_sr_i[1]                Net        -        -       0.800     -           2         
reset_dcm\.pma_dcm_reset_sr_i_2[0]    LUT2_L     I0       In      -         1.426       -         
reset_dcm\.pma_dcm_reset_sr_i_2[0]    LUT2_L     LO       Out     0.504     1.930       -         
reset_dcm\.pma_dcm_reset_sr_i_2[0]    Net        -        -       0.000     -           1         
pma_dcm_reset_sr_i[0]                 FDP        D        In      -         1.930       -         
==================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.026 is 1.226(60.5%) logic and 0.800(39.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        16.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.904

    - Propagation time:                      1.930
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.974

    Number of logic level(s):                1
    Starting point:                          pma_dcm_reset_sr_i[2] / Q
    Ending point:                            pma_dcm_reset_i / D
    The start point is clocked by            rbc1_clk [rising] on pin C
    The end   point is clocked by            rbc1_clk [rising] on pin C

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                      Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
pma_dcm_reset_sr_i[2]     FDP        Q        Out     0.626     0.626       -         
pma_dcm_reset_sr_i[2]     Net        -        -       0.800     -           2         
pma_dcm_reset_i_RNO       LUT4_L     I0       In      -         1.426       -         
pma_dcm_reset_i_RNO       LUT4_L     LO       Out     0.504     1.930       -         
N_68_i                    Net        -        -       0.000     -           1         
pma_dcm_reset_i           FDCP       D        In      -         1.930       -         
======================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.026 is 1.226(60.5%) logic and 0.800(39.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        16.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.904

    - Propagation time:                      1.930
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.974

    Number of logic level(s):                1
    Starting point:                          pma_dcm_reset_sr_i[3] / Q
    Ending point:                            pma_dcm_reset_i / D
    The start point is clocked by            rbc1_clk [rising] on pin C
    The end   point is clocked by            rbc1_clk [rising] on pin C

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                      Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
pma_dcm_reset_sr_i[3]     FDP        Q        Out     0.626     0.626       -         
pma_dcm_reset_sr_i[3]     Net        -        -       0.800     -           2         
pma_dcm_reset_i_RNO       LUT4_L     I1       In      -         1.426       -         
pma_dcm_reset_i_RNO       LUT4_L     LO       Out     0.504     1.930       -         
N_68_i                    Net        -        -       0.000     -           1         
pma_dcm_reset_i           FDCP       D        In      -         1.930       -         
======================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.026 is 1.226(60.5%) logic and 0.800(39.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                           Starting                                                                                            Arrival           
Instance                   Reference     Type                            Pin                        Net                        Time        Slack 
                           Clock                                                                                                                 
-------------------------------------------------------------------------------------------------------------------------------------------------
ccc_cont_in                System        Port                            ccc_cont_in                ccc_cont_in                0.000       -0.025
ccc_ftrig_in               System        Port                            ccc_ftrig_in               ccc_ftrig_in               0.000       -0.025
cpld_expansionbus[7:0]     System        Port                            cpld_expansionbus[2]       cpld_expansionbus[2]       0.000       4.625 
main_reset                 System        Port                            main_reset                 main_reset                 0.000       5.049 
cpld_expansionbus[7:0]     System        Port                            cpld_expansionbus[0]       cpld_expansionbus[0]       0.000       5.360 
cpld_expansionbus[7:0]     System        Port                            cpld_expansionbus[1]       cpld_expansionbus[1]       0.000       5.360 
dif_packet_wrapper         System        lda_wrap_dif_work_md2_rtl_0     input_dst_rdy_n            dif_mux_dst_rdy_n          0.000       5.578 
slow_clk_sync              System        Port                            slow_clk_sync              slow_clk_sync              0.000       15.218
cpld_expansionbus_a_dn     System        Port                            cpld_expansionbus_a_dn     cpld_expansionbus_a_dn     0.000       15.609
gig_rd[9:0]                System        Port                            gig_rd[0]                  gig_rd[0]                  0.000       15.976
=================================================================================================================================================


Ending Points with Worst Slack
******************************

                                           Starting                                                                                   Required           
Instance                                   Reference     Type                            Pin               Net                        Time         Slack 
                                           Clock                                                                                                         
---------------------------------------------------------------------------------------------------------------------------------------------------------
ccc_busy_out                               System        Port                            ccc_busy_out      ccc_busy_out               7.752        -0.025
ccc_spare_out                              System        Port                            ccc_spare_out     ccc_spare_out              7.752        -0.025
SPI_SLAVE.SPI_Shifter.spi_buffer_rx[0]     System        FDCE                            D                 N_612_i                    7.904        4.625 
sync_reset_in\.rst_sr[0]                   System        FD                              D                 main_reset_c               7.824        5.049 
SPI_SLAVE.SPI_Shifter.sclk_sync            System        FDC                             D                 cpld_expansionbus_c[1]     5.360        5.360 
SPI_SLAVE.SPI_Shifter.tx_spi_cs            System        FDCE                            D                 cpld_expansionbus_c[0]     5.360        5.360 
dif_packet_wrapper                         System        lda_wrap_dif_work_md2_rtl_0     input_port[0]     dif_wrap_input_port[0]     7.752        5.578 
dif_packet_wrapper                         System        lda_wrap_dif_work_md2_rtl_0     input_port[1]     dif_wrap_input_port[1]     7.752        5.578 
dif_packet_wrapper                         System        lda_wrap_dif_work_md2_rtl_0     input_port[2]     dif_wrap_input_port[2]     7.752        5.578 
dif_packet_wrapper                         System        lda_wrap_dif_work_md2_rtl_0     input_port[3]     dif_wrap_input_port[3]     7.752        5.578 
=========================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        7.752
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         7.752

    - Propagation time:                      7.777
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.025

    Number of logic level(s):                2
    Starting point:                          ccc_cont_in / ccc_cont_in
    Ending point:                            ccc_busy_out / ccc_busy_out
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                 Pin              Pin               Arrival     No. of    
Name                  Type     Name             Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
ccc_cont_in           Port     ccc_cont_in      In      0.000     0.000       -         
ccc_cont_in           Net      -                -       0.000     -           1         
ccc_cont_in_ibuf      IBUF     I                In      -         0.000       -         
ccc_cont_in_ibuf      IBUF     O                Out     2.136     2.136       -         
ccc_cont_in_c         Net      -                -       0.639     -           1         
ccc_busy_out_obuf     OBUF     I                In      -         2.775       -         
ccc_busy_out_obuf     OBUF     O                Out     5.002     7.777       -         
ccc_busy_out          Net      -                -       0.000     -           1         
ccc_busy_out          Port     ccc_busy_out     Out     -         7.777       -         
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.777 is 7.138(91.8%) logic and 0.639(8.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        7.752
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         7.752

    - Propagation time:                      7.777
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.025

    Number of logic level(s):                2
    Starting point:                          ccc_ftrig_in / ccc_ftrig_in
    Ending point:                            ccc_spare_out / ccc_spare_out
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                  Pin               Pin               Arrival     No. of    
Name                   Type     Name              Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------
ccc_ftrig_in           Port     ccc_ftrig_in      In      0.000     0.000       -         
ccc_ftrig_in           Net      -                 -       0.000     -           1         
ccc_ftrig_in_ibuf      IBUF     I                 In      -         0.000       -         
ccc_ftrig_in_ibuf      IBUF     O                 Out     2.136     2.136       -         
ccc_ftrig_in_c         Net      -                 -       0.639     -           1         
ccc_spare_out_obuf     OBUF     I                 In      -         2.775       -         
ccc_spare_out_obuf     OBUF     O                 Out     5.002     7.777       -         
ccc_spare_out          Net      -                 -       0.000     -           1         
ccc_spare_out          Port     ccc_spare_out     Out     -         7.777       -         
==========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.777 is 7.138(91.8%) logic and 0.639(8.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        8.000
    - Setup time:                            0.096
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.904

    - Propagation time:                      3.279
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.625

    Number of logic level(s):                2
    Starting point:                          cpld_expansionbus[7:0] / cpld_expansionbus[2]
    Ending point:                            SPI_SLAVE.SPI_Shifter.spi_buffer_rx[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                                            Pin                      Pin               Arrival     No. of    
Name                                           Type       Name                     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
cpld_expansionbus[7:0]                         Port       cpld_expansionbus[2]     In      0.000     0.000       -         
cpld_expansionbus[2]                           Net        -                        -       0.000     -           1         
cpld_expansionbus_ibuf[2]                      IBUF       I                        In      -         0.000       -         
cpld_expansionbus_ibuf[2]                      IBUF       O                        Out     2.136     2.136       -         
cpld_expansionbus_c[2]                         Net        -                        -       0.639     -           1         
SPI_SLAVE.SPI_Shifter.spi_buffer_rx_RNO[0]     LUT2_L     I1                       In      -         2.775       -         
SPI_SLAVE.SPI_Shifter.spi_buffer_rx_RNO[0]     LUT2_L     LO                       Out     0.504     3.279       -         
N_612_i                                        Net        -                        -       0.000     -           1         
SPI_SLAVE.SPI_Shifter.spi_buffer_rx[0]         FDCE       D                        In      -         3.279       -         
===========================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 3.375 is 2.736(81.1%) logic and 0.639(18.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        8.000
    - Setup time:                            0.176
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.824

    - Propagation time:                      2.775
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.049

    Number of logic level(s):                1
    Starting point:                          main_reset / main_reset
    Ending point:                            sync_reset_in\.rst_sr[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                       Pin            Pin               Arrival     No. of    
Name                        Type     Name           Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
main_reset                  Port     main_reset     In      0.000     0.000       -         
main_reset                  Net      -              -       0.000     -           1         
main_reset_ibuf             IBUF     I              In      -         0.000       -         
main_reset_ibuf             IBUF     O              Out     2.136     2.136       -         
main_reset_c                Net      -              -       0.639     -           1         
sync_reset_in\.rst_sr[0]    FD       D              In      -         2.775       -         
============================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.951 is 2.312(78.3%) logic and 0.639(21.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        8.000
    - Setup time:                            2.640
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.360

    - Propagation time:                      0.000
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.360

    Number of logic level(s):                1
    Starting point:                          cpld_expansionbus[7:0] / cpld_expansionbus[0]
    Ending point:                            SPI_SLAVE.SPI_Shifter.tx_spi_cs / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            gtx125_clk [rising] on pin C

Instance / Net                               Pin                      Pin               Arrival     No. of    
Name                                Type     Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
cpld_expansionbus[7:0]              Port     cpld_expansionbus[0]     In      0.000     0.000       -         
cpld_expansionbus[0]                Net      -                        -       0.000     -           1         
cpld_expansionbus_ibuf[0]           IBUF     I                        In      -         0.000       -         
cpld_expansionbus_ibuf[0]           IBUF     O                        Out     0.000     0.000       -         
cpld_expansionbus_c[0]              Net      -                        -       0.000     -           2         
SPI_SLAVE.SPI_Shifter.tx_spi_cs     FDCE     D                        In      -         0.000       -         
==============================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.640 is 2.640(100.0%) logic and 0.000(0.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint



##### END OF TIMING REPORT #####]

@W:MT305 :  | Timing constraint (from $config_to_rx to $rx_clock) (false path) never applies in design and was not found in design. To be verified  
@W:MT305 :  | Timing constraint (from $config_to_rx to $tx_clock) (false path) never applies in design and was not found in design. To be verified  
@W:MT305 :  | Timing constraint (from $config_to_tx to $tx_clock) (false path) never applies in design and was not found in design. To be verified  
@W:MT299 :  | Timing constraint (to $mdio_logic) (max delay 400.000000) never applies in design and was not found in design. To be verified  
@W:MT299 :  | Timing constraint (from $mdc_rising to $mdc_falling) (max delay 200.000000) never applies in design and was not found in design. To be verified  
@W:MT299 :  | Timing constraint (from $host to $mdio_logic) (max delay 8.000000) never applies in design and was not found in design. To be verified  
@W:MT305 :  | Timing constraint (from $host to $rx_clock) (false path) never applies in design and was not found in design. To be verified  
@W:MT305 :  | Timing constraint (from $host to $tx_clock) (false path) never applies in design and was not found in design. To be verified  
@W:MT299 :  | Timing constraint (from $FFS to $codec8b10b) (max delay 8.000000) never applies in design and was not found in design. To be verified  
@W:MT299 :  | Timing constraint (from $codec8b10b to $FFS) (max delay 8.000000) never applies in design and was not found in design. To be verified  
---------------------------------------
Resource Usage Report for md2 

Mapping to part: xc3s2000fg456-5
Cell usage:
DCM             2 uses
FD              317 uses
FDC             2530 uses
FDCE            6366 uses
FDCE_1          1 use
FDCP            1 use
FDE             265 uses
FDP             179 uses
FDPE            674 uses
FDPE_1          1 use
FDR             631 uses
FDRE            753 uses
FDRS            39 uses
FDRSE           40 uses
FDS             33 uses
FDSE            74 uses
GND             408 uses
MULT_AND        7 uses
MUXCY           170 uses
MUXCY_L         1399 uses
MUXF5           1437 uses
MUXF6           170 uses
MUXF7           48 uses
RAMB16_S18_S18  18 uses
RAMB16_S9_S18   1 use
RAMB16_S9_S9    8 uses
VCC             384 uses
XORCY           1118 uses
lda_wrap_dif_work_md2_rtl_0  1 use
LUT1            805 uses
LUT2            3864 uses
LUT3            3610 uses
LUT4            7867 uses

I/O ports: 167
I/O primitives: 109
IBUF           16 uses
IBUFG          3 uses
IFDDRCPE       10 uses
OBUF           52 uses
OBUFT          27 uses
OFDDRRSE       1 use

BUFG           6 uses

SRL primitives:
SRLC16         336 uses
SRL16          28 uses
SRL16E         2 uses

I/O Register bits:                  41
Register bits not including I/Os:   11874 (28%)

RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 148
Block Rams : 27 of 40 (67%)


Global Clock Buffers: 6 of 8 (75%)

Total load per clock:
   gtx125_clk: 4276
   rbc1_clk: 10
   lda_dif_links|DCM_CLK0_BUF_derived_clock: 8080
   md2|pma_dcm_clk1_i_derived_clock: 84
   lda_dif_links|DCM_CLK90_BUF_derived_clock: 9
   main_dif_clk: 8

Mapping Summary:
Total  LUTs: 16808 (41%)

Mapper successful!
Process took 0h:03m:02s realtime, 0h:02m:48s cputime
# Tue Mar 16 10:34:01 2010

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