Adding property xc_loc, value "G22", to port bit RX7_SP_P Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/lvds_drivers_receivers.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jan 13 14:26:40 2010 ###########################################################] to port bit CLK6_N Adding property xc_loc, value "G18", to port bit RX7_DATA_P Adding property xc_loc, value "G17", to port bit RX7_DATA_N Adding property xc_loc, value "G22", to port bit RX7_SP_P Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jan 13 14:28:29 2010 ###########################################################] Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jan 13 14:34:44 2010 ###########################################################] Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jan 13 14:36:46 2010 ###########################################################] Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jan 13 14:37:29 2010 ###########################################################] port bit RX7_DATA_P Adding property xc_loc, value "G17", to port bit RX7_DATA_N Adding property xc_loc, value "G22", to port bit RX7_SP_P Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 11:50:05 2010 ###########################################################] c_loc, value "M2", to port bit CLK2_N Adding property xc_loc, value "T4", to port bit RX3_DATA_P Adding property xc_loc, value "U4", to port bit RX3_DATA_N Adding property xc_loc, value "T2", to port bit RX3_SP_P Adding property xc_loc, value "T1", to port bit RX3_SP_N Adding property xc_loc, value "N3", to port bit TX3_DATA_P Adding property xc_loc, value "N4", to port bit TX3_DATA_N Adding property xc_loc, value "V1", to port bit TX3_UTP_P Adding property xc_loc, value "V2", to port bit TX3_UTP_N Adding property xc_loc, value "N1", to port bit CLK3_P Adding property xc_loc, value "N2", to port bit CLK3_N Adding property xc_loc, value "W1", to port bit RX4_DATA_P Adding property xc_loc, value "W2", to port bit RX4_DATA_N Adding property xc_loc, value "AA3", to port bit RX4_SP_P Adding property xc_loc, value "Y4", to port bit RX4_SP_N Adding property xc_loc, value "W3", to port bit TX4_DATA_P Adding property xc_loc, value "W4", to port bit TX4_DATA_N Adding property xc_loc, value "W5", to port bit TX4_UTP_P Adding property xc_loc, value "Y5", to port bit TX4_UTP_N Adding property xc_loc, value "V3", to port bit CLK4_P Adding property xc_loc, value "V4", to port bit CLK4_N Adding property xc_loc, value "L22", to port bit RX5_DATA_P Adding property xc_loc, value "L21", to port bit RX5_DATA_N Adding property xc_loc, value "N21", to port bit RX5_SP_P Adding property xc_loc, value "N22", to port bit RX5_SP_N Adding property xc_loc, value "M17", to port bit TX5_DATA_P Adding property xc_loc, value "M18", to port bit TX5_DATA_N Adding property xc_loc, value "M19", to port bit TX5_UTP_P Adding property xc_loc, value "M20", to port bit TX5_UTP_N Adding property xc_loc, value "L18", to port bit CLK5_P Adding property xc_loc, value "L17", to port bit CLK5_N Adding property xc_loc, value "U20", to port bit RX6_DATA_P Adding property xc_loc, value "U21", to port bit RX6_DATA_N Adding property xc_loc, value "W22", to port bit RX6_SP_P Adding property xc_loc, value "Y22", to port bit RX6_SP_N Adding property xc_loc, value "T21", to port bit TX6_DATA_P Adding property xc_loc, value "T22", to port bit TX6_DATA_N Adding property xc_loc, value "V22", to port bit TX6_UTP_P Adding property xc_loc, value "V21", to port bit TX6_UTP_N Adding property xc_loc, value "N19", to port bit CLK6_P Adding property xc_loc, value "N20", to port bit CLK6_N Adding property xc_loc, value "G18", to port bit RX7_DATA_P Adding property xc_loc, value "G17", to port bit RX7_DATA_N Adding property xc_loc, value "G22", to port bit RX7_SP_P Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 16 14:32:17 2010 ###########################################################] "M1", to port bit CLK2_P Adding property xc_loc, value "M2", to port bit CLK2_N Adding property xc_loc, value "T4", to port bit RX3_DATA_P Adding property xc_loc, value "U4", to port bit RX3_DATA_N Adding property xc_loc, value "T2", to port bit RX3_SP_P Adding property xc_loc, value "T1", to port bit RX3_SP_N Adding property xc_loc, value "N3", to port bit TX3_DATA_P Adding property xc_loc, value "N4", to port bit TX3_DATA_N Adding property xc_loc, value "V1", to port bit TX3_UTP_P Adding property xc_loc, value "V2", to port bit TX3_UTP_N Adding property xc_loc, value "N1", to port bit CLK3_P Adding property xc_loc, value "N2", to port bit CLK3_N Adding property xc_loc, value "W1", to port bit RX4_DATA_P Adding property xc_loc, value "W2", to port bit RX4_DATA_N Adding property xc_loc, value "AA3", to port bit RX4_SP_P Adding property xc_loc, value "Y4", to port bit RX4_SP_N Adding property xc_loc, value "W3", to port bit TX4_DATA_P Adding property xc_loc, value "W4", to port bit TX4_DATA_N Adding property xc_loc, value "W5", to port bit TX4_UTP_P Adding property xc_loc, value "Y5", to port bit TX4_UTP_N Adding property xc_loc, value "V3", to port bit CLK4_P Adding property xc_loc, value "V4", to port bit CLK4_N Adding property xc_loc, value "L22", to port bit RX5_DATA_P Adding property xc_loc, value "L21", to port bit RX5_DATA_N Adding property xc_loc, value "N21", to port bit RX5_SP_P Adding property xc_loc, value "N22", to port bit RX5_SP_N Adding property xc_loc, value "M17", to port bit TX5_DATA_P Adding property xc_loc, value "M18", to port bit TX5_DATA_N Adding property xc_loc, value "M19", to port bit TX5_UTP_P Adding property xc_loc, value "M20", to port bit TX5_UTP_N Adding property xc_loc, value "L18", to port bit CLK5_P Adding property xc_loc, value "L17", to port bit CLK5_N Adding property xc_loc, value "U20", to port bit RX6_DATA_P Adding property xc_loc, value "U21", to port bit RX6_DATA_N Adding property xc_loc, value "W22", to port bit RX6_SP_P Adding property xc_loc, value "Y22", to port bit RX6_SP_N Adding property xc_loc, value "T21", to port bit TX6_DATA_P Adding property xc_loc, value "T22", to port bit TX6_DATA_N Adding property xc_loc, value "V22", to port bit TX6_UTP_P Adding property xc_loc, value "V21", to port bit TX6_UTP_N Adding property xc_loc, value "N19", to port bit CLK6_P Adding property xc_loc, value "N20", to port bit CLK6_N Adding property xc_loc, value "G18", to port bit RX7_DATA_P Adding property xc_loc, value "G17", to port bit RX7_DATA_N Adding property xc_loc, value "G22", to port bit RX7_SP_P Adding property xc_loc, value "G21", to port bit RX7_SP_N Adding property xc_loc, value "G19", to port bit TX7_DATA_P Adding property xc_loc, value "F19", to port bit TX7_DATA_N Adding property xc_loc, value "F21", to port bit CLK7_P Adding property xc_loc, value "F20", to port bit CLK7_N Adding property xc_loc, value "K20", to port bit RX8_DATA_P Adding property xc_loc, value "K19", to port bit RX8_DATA_N Adding property xc_loc, value "K21", to port bit RX8_SP_P Adding property xc_loc, value "K22", to port bit RX8_SP_N Adding property xc_loc, value "L20", to port bit TX8_UTP_P Adding property xc_loc, value "L19", to port bit TX8_UTP_N Adding property xc_loc, value "E18", to port bit RX9_DATA_P Adding property xc_loc, value "F18", to port bit RX9_DATA_N Adding property xc_loc, value "D19", to port bit RX9_SP_P Adding property xc_loc, value "D20", to port bit RX9_SP_N Adding property xc_loc, value "E20", to port bit TX9_DATA_P Adding property xc_loc, value "E19", to port bit TX9_DATA_N Adding property xc_loc, value "E21", to port bit TX9_UTP_P Adding property xc_loc, value "E22", to port bit TX9_UTP_N Adding property xc_loc, value "D21", to port bit CLK9_P Adding property xc_loc, value "D22", to port bit CLK9_N Adding property xc_loc, value "K4", to port bit RX10_DATA_P Adding property xc_loc, value "K3", to port bit RX10_DATA_N Adding property xc_loc, value "F4", to port bit RX10_SP_P Adding property xc_loc, value "E3", to port bit RX10_SP_N Adding property xc_loc, value "G2", to port bit TX10_DATA_P Adding property xc_loc, value "G1", to port bit TX10_DATA_N Adding property xc_loc, value "E2", to port bit TX10_UTP_P Adding property xc_loc, value "E1", to port bit TX10_UTP_N Adding property xc_loc, value "C1", to port bit CLK10_P Adding property xc_loc, value "D1", to port bit CLK10_N Adding property xc_loc, value "B12", to port bit SPARE2 Adding property xc_loc, value "C12", to port bit SPARE3 Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/hdmi.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 16 14:34:37 2010 ###########################################################]