port DCD_N Adding property xc_loc, value "J4", to port DTR_N Adding property syn_pad_type, value "LVCMOS_25", to port DTR_N Adding property xc_loc, value "E7", to port R_N Adding property syn_pad_type, value "LVCMOS_33", to port R_N Adding property xc_loc, value "G16", to port PS2_1_1 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_1 Adding property xc_loc, value "H16", to port PS2_1_2 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_2 Adding property xc_loc, value "G13", to port PS2_1_5 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_5 Adding property xc_loc, value "H15", to port PS2_1_6 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_6 Adding property xc_loc, value "F16", to port PS2_2_1 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_1 Adding property xc_loc, value "F13", to port PS2_2_2 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_2 Adding property xc_loc, value "F14", to port PS2_2_5 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_5 Adding property xc_loc, value "G14", to port PS2_2_6 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_6 Adding property xc_loc, value "N13", to port EN2 Adding property syn_pad_type, value "LVCMOS_33", to port EN2 Adding property xc_loc, value "P15", to port EN3 Adding property syn_pad_type, value "LVCMOS_33", to port EN3 Adding property xc_loc, value "L16", to port EN5 Adding property syn_pad_type, value "LVCMOS_33", to port EN5 Adding property xc_loc, value "L14", to port EN6 Adding property syn_pad_type, value "LVCMOS_33", to port EN6 Adding property xc_loc, value "M15", to port EN7 Adding property syn_pad_type, value "LVCMOS_33", to port EN7 Adding property xc_loc, value "N16", to port EN8 Adding property syn_pad_type, value "LVCMOS_33", to port EN8 Adding property xc_loc, value "L13", to port EN9 Adding property syn_pad_type, value "LVCMOS_33", to port EN9 Adding property xc_loc, value "F15", to port MAIN_ON_3V3_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_3V3_N Adding property xc_loc, value "E13", to port MAIN_ON_1V2_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_1V2_N Adding property xc_loc, value "K14", to port bit SWDIP[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[1] Adding property xc_loc, value "K13", to port bit SWDIP[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[2] Adding property xc_loc, value "K15", to port bit SWDIP[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[3] Adding property xc_loc, value "K16", to port bit SWDIP[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[4] Adding property xc_loc, value "J16", to port bit SWDIP[5] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[5] Adding property xc_loc, value "J13", to port bit SWDIP[6] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[6] Adding property xc_loc, value "J12", to port bit SWDIP[7] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[7] Adding property xc_loc, value "H13", to port bit SWDIP[8] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[8] Adding property xc_loc, value "T9", to port bit S2000_M[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[0] Adding property xc_loc, value "P9", to port bit S2000_M[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[1] Adding property xc_loc, value "R9", to port bit S2000_M[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[2] Adding property xc_loc, value "N9", to port bit EXPANSION_BUS[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[0] Adding property xc_loc, value "N11", to port bit EXPANSION_BUS[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[1] Adding property xc_loc, value "R5", to port bit EXPANSION_BUS[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[2] Adding property xc_loc, value "T5", to port bit EXPANSION_BUS[3] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[3] Adding property xc_loc, value "T4", to port bit EXPANSION_BUS[4] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[4] Adding property xc_loc, value "R7", to port bit EXPANSION_BUS[5] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[5] Adding property xc_loc, value "T6", to port bit EXPANSION_BUS[6] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[6] Adding property xc_loc, value "P11", to port bit EXPANSION_BUS[7] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[7] Adding property xc_loc, value "B4", to port bit LEDS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[1] Adding property xc_loc, value "C4", to port bit LEDS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[2] Adding property xc_loc, value "B3", to port bit LEDS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[3] Adding property xc_loc, value "D10", to port bit USB_CBUS[0] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[0] Adding property xc_loc, value "D9", to port bit USB_CBUS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[1] Adding property xc_loc, value "A6", to port bit USB_CBUS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[2] Adding property xc_loc, value "B6", to port bit USB_CBUS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[3] Adding property xc_loc, value "C7", to port bit USB_CBUS[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[4] Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @W:MO111 : startup_fpga.vhd(305) | tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_SERAL_DIN_1 on net S2000_SERAL_DIN_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_CCLK_1 on net S2000_CCLK_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver RTS_N_1 on net RTS_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver D_RESET_N_1 on net D_RESET_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver DTR_N_1 on net DTR_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_P_1 on net CLOCK4_P_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_N_1 on net CLOCK4_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK3_N_1 on net CLOCK3_N_1 has its enable tied to GND (module startup_fpga) @W:BN105 : | Cannot apply constraint xc_loc to CSN_ETH @W:BN105 : | Cannot apply constraint xc_pulldown to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to CSN_ETH @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/startup/md2_startup/rev_1/md2_startup.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:28:07 2010 ###########################################################] _N Adding property syn_pad_type, value "LVCMOS_25", to port DTR_N Adding property xc_loc, value "E7", to port R_N Adding property syn_pad_type, value "LVCMOS_33", to port R_N Adding property xc_loc, value "G16", to port PS2_1_1 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_1 Adding property xc_loc, value "H16", to port PS2_1_2 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_2 Adding property xc_loc, value "G13", to port PS2_1_5 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_5 Adding property xc_loc, value "H15", to port PS2_1_6 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_6 Adding property xc_loc, value "F16", to port PS2_2_1 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_1 Adding property xc_loc, value "F13", to port PS2_2_2 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_2 Adding property xc_loc, value "F14", to port PS2_2_5 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_5 Adding property xc_loc, value "G14", to port PS2_2_6 Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_6 Adding property xc_loc, value "N13", to port EN2 Adding property syn_pad_type, value "LVCMOS_33", to port EN2 Adding property xc_loc, value "P15", to port EN3 Adding property syn_pad_type, value "LVCMOS_33", to port EN3 Adding property xc_loc, value "L16", to port EN5 Adding property syn_pad_type, value "LVCMOS_33", to port EN5 Adding property xc_loc, value "L14", to port EN6 Adding property syn_pad_type, value "LVCMOS_33", to port EN6 Adding property xc_loc, value "M15", to port EN7 Adding property syn_pad_type, value "LVCMOS_33", to port EN7 Adding property xc_loc, value "N16", to port EN8 Adding property syn_pad_type, value "LVCMOS_33", to port EN8 Adding property xc_loc, value "L13", to port EN9 Adding property syn_pad_type, value "LVCMOS_33", to port EN9 Adding property xc_loc, value "F15", to port MAIN_ON_3V3_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_3V3_N Adding property xc_loc, value "E13", to port MAIN_ON_1V2_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_1V2_N Adding property xc_loc, value "K14", to port bit SWDIP[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[1] Adding property xc_loc, value "K13", to port bit SWDIP[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[2] Adding property xc_loc, value "K15", to port bit SWDIP[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[3] Adding property xc_loc, value "K16", to port bit SWDIP[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[4] Adding property xc_loc, value "J16", to port bit SWDIP[5] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[5] Adding property xc_loc, value "J13", to port bit SWDIP[6] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[6] Adding property xc_loc, value "J12", to port bit SWDIP[7] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[7] Adding property xc_loc, value "H13", to port bit SWDIP[8] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[8] Adding property xc_loc, value "T9", to port bit S2000_M[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[0] Adding property xc_loc, value "P9", to port bit S2000_M[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[1] Adding property xc_loc, value "R9", to port bit S2000_M[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[2] Adding property xc_loc, value "N9", to port bit EXPANSION_BUS[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[0] Adding property xc_loc, value "N11", to port bit EXPANSION_BUS[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[1] Adding property xc_loc, value "R5", to port bit EXPANSION_BUS[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[2] Adding property xc_loc, value "T5", to port bit EXPANSION_BUS[3] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[3] Adding property xc_loc, value "T4", to port bit EXPANSION_BUS[4] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[4] Adding property xc_loc, value "R7", to port bit EXPANSION_BUS[5] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[5] Adding property xc_loc, value "T6", to port bit EXPANSION_BUS[6] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[6] Adding property xc_loc, value "P11", to port bit EXPANSION_BUS[7] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[7] Adding property xc_loc, value "B4", to port bit LEDS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[1] Adding property xc_loc, value "C4", to port bit LEDS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[2] Adding property xc_loc, value "B3", to port bit LEDS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[3] Adding property xc_loc, value "D10", to port bit USB_CBUS[0] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[0] Adding property xc_loc, value "D9", to port bit USB_CBUS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[1] Adding property xc_loc, value "A6", to port bit USB_CBUS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[2] Adding property xc_loc, value "B6", to port bit USB_CBUS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[3] Adding property xc_loc, value "C7", to port bit USB_CBUS[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[4] Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @W:MO111 : startup_fpga.vhd(305) | tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_SERAL_DIN_1 on net S2000_SERAL_DIN_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_CCLK_1 on net S2000_CCLK_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver RTS_N_1 on net RTS_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver D_RESET_N_1 on net D_RESET_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver DTR_N_1 on net DTR_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_P_1 on net CLOCK4_P_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_N_1 on net CLOCK4_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK3_N_1 on net CLOCK3_N_1 has its enable tied to GND (module startup_fpga) @W:BN105 : | Cannot apply constraint xc_loc to CSN_ETH @W:BN105 : | Cannot apply constraint xc_pulldown to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to CSN_ETH @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/startup/md2_startup/rev_1/md2_startup.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:28:54 2010 ###########################################################] t EN6 Adding property syn_pad_type, value "LVCMOS_33", to port EN6 Adding property xc_loc, value "M15", to port EN7 Adding property syn_pad_type, value "LVCMOS_33", to port EN7 Adding property xc_loc, value "N16", to port EN8 Adding property syn_pad_type, value "LVCMOS_33", to port EN8 Adding property xc_loc, value "L13", to port EN9 Adding property syn_pad_type, value "LVCMOS_33", to port EN9 Adding property xc_loc, value "F15", to port MAIN_ON_3V3_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_3V3_N Adding property xc_loc, value "E13", to port MAIN_ON_1V2_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_1V2_N Adding property xc_loc, value "K14", to port bit SWDIP[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[1] Adding property xc_loc, value "K13", to port bit SWDIP[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[2] Adding property xc_loc, value "K15", to port bit SWDIP[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[3] Adding property xc_loc, value "K16", to port bit SWDIP[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[4] Adding property xc_loc, value "J16", to port bit SWDIP[5] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[5] Adding property xc_loc, value "J13", to port bit SWDIP[6] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[6] Adding property xc_loc, value "J12", to port bit SWDIP[7] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[7] Adding property xc_loc, value "H13", to port bit SWDIP[8] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[8] Adding property xc_loc, value "T9", to port bit S2000_M[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[0] Adding property xc_loc, value "P9", to port bit S2000_M[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[1] Adding property xc_loc, value "R9", to port bit S2000_M[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[2] Adding property xc_loc, value "N9", to port bit EXPANSION_BUS[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[0] Adding property xc_loc, value "N11", to port bit EXPANSION_BUS[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[1] Adding property xc_loc, value "R5", to port bit EXPANSION_BUS[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[2] Adding property xc_loc, value "T5", to port bit EXPANSION_BUS[3] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[3] Adding property xc_loc, value "T4", to port bit EXPANSION_BUS[4] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[4] Adding property xc_loc, value "R7", to port bit EXPANSION_BUS[5] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[5] Adding property xc_loc, value "T6", to port bit EXPANSION_BUS[6] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[6] Adding property xc_loc, value "P11", to port bit EXPANSION_BUS[7] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[7] Adding property xc_loc, value "B4", to port bit LEDS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[1] Adding property xc_loc, value "C4", to port bit LEDS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[2] Adding property xc_loc, value "B3", to port bit LEDS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[3] Adding property xc_loc, value "D10", to port bit USB_CBUS[0] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[0] Adding property xc_loc, value "D9", to port bit USB_CBUS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[1] Adding property xc_loc, value "A6", to port bit USB_CBUS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[2] Adding property xc_loc, value "B6", to port bit USB_CBUS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[3] Adding property xc_loc, value "C7", to port bit USB_CBUS[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[4] Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @W:FX474 : | User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code @W:MO111 : startup_fpga.vhd(305) | tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_SERAL_DIN_1 on net S2000_SERAL_DIN_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_CCLK_1 on net S2000_CCLK_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver RTS_N_1 on net RTS_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver D_RESET_N_1 on net D_RESET_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver DTR_N_1 on net DTR_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_P_1 on net CLOCK4_P_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_N_1 on net CLOCK4_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK3_N_1 on net CLOCK3_N_1 has its enable tied to GND (module startup_fpga) @W:BN105 : | Cannot apply constraint xc_loc to CSN_ETH @W:BN105 : | Cannot apply constraint xc_pulldown to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to CSN_ETH @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/startup/md2_startup/rev_1/md2_startup.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:30:20 2010 ###########################################################] d_type, value "LVCMOS_33", to port EN6 Adding property xc_loc, value "M15", to port EN7 Adding property syn_pad_type, value "LVCMOS_33", to port EN7 Adding property xc_loc, value "N16", to port EN8 Adding property syn_pad_type, value "LVCMOS_33", to port EN8 Adding property xc_loc, value "L13", to port EN9 Adding property syn_pad_type, value "LVCMOS_33", to port EN9 Adding property xc_loc, value "F15", to port MAIN_ON_3V3_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_3V3_N Adding property xc_loc, value "E13", to port MAIN_ON_1V2_N Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_1V2_N Adding property xc_loc, value "K14", to port bit SWDIP[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[1] Adding property xc_loc, value "K13", to port bit SWDIP[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[2] Adding property xc_loc, value "K15", to port bit SWDIP[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[3] Adding property xc_loc, value "K16", to port bit SWDIP[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[4] Adding property xc_loc, value "J16", to port bit SWDIP[5] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[5] Adding property xc_loc, value "J13", to port bit SWDIP[6] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[6] Adding property xc_loc, value "J12", to port bit SWDIP[7] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[7] Adding property xc_loc, value "H13", to port bit SWDIP[8] Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[8] Adding property xc_loc, value "T9", to port bit S2000_M[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[0] Adding property xc_loc, value "P9", to port bit S2000_M[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[1] Adding property xc_loc, value "R9", to port bit S2000_M[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[2] Adding property xc_loc, value "N9", to port bit EXPANSION_BUS[0] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[0] Adding property xc_loc, value "N11", to port bit EXPANSION_BUS[1] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[1] Adding property xc_loc, value "R5", to port bit EXPANSION_BUS[2] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[2] Adding property xc_loc, value "T5", to port bit EXPANSION_BUS[3] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[3] Adding property xc_loc, value "T4", to port bit EXPANSION_BUS[4] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[4] Adding property xc_loc, value "R7", to port bit EXPANSION_BUS[5] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[5] Adding property xc_loc, value "T6", to port bit EXPANSION_BUS[6] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[6] Adding property xc_loc, value "P11", to port bit EXPANSION_BUS[7] Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[7] Adding property xc_loc, value "B4", to port bit LEDS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[1] Adding property xc_loc, value "C4", to port bit LEDS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[2] Adding property xc_loc, value "B3", to port bit LEDS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[3] Adding property xc_loc, value "D10", to port bit USB_CBUS[0] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[0] Adding property xc_loc, value "D9", to port bit USB_CBUS[1] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[1] Adding property xc_loc, value "A6", to port bit USB_CBUS[2] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[2] Adding property xc_loc, value "B6", to port bit USB_CBUS[3] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[3] Adding property xc_loc, value "C7", to port bit USB_CBUS[4] Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[4] Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] @N: : | Running in logic synthesis mode without enhanced optimization @W: : | Ignoring synthesis effort setting for the design. This is not supported by the current technology. @W:FX474 : | User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code @W:MO111 : startup_fpga.vhd(305) | tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_SERAL_DIN_1 on net S2000_SERAL_DIN_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_CCLK_1 on net S2000_CCLK_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver RTS_N_1 on net RTS_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver D_RESET_N_1 on net D_RESET_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver DTR_N_1 on net DTR_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_P_1 on net CLOCK4_P_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_N_1 on net CLOCK4_N_1 has its enable tied to GND (module startup_fpga) @W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK3_N_1 on net CLOCK3_N_1 has its enable tied to GND (module startup_fpga) @W:BN105 : | Cannot apply constraint xc_loc to CSN_ETH @W:BN105 : | Cannot apply constraint xc_pulldown to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to S2000_HSWAP_EN @W:BN105 : | Cannot apply constraint syn_pad_type to CSN_ETH @N:BN225 : | Writing default property annotation file /home/warren/calicedaq/LDA/firmware/syn/startup/md2_startup/rev_1/md2_startup.sap. Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:38:57 2010 ###########################################################]