#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
#install: /unix/local/synopsys/synplicity/fpga_c200906
#OS: Linux
#Hostname: pc140.hep.ucl.ac.uk
#Implementation: rev_1
#Wed Feb 17 16:38:55 2010
$ Start of Compile
#Wed Feb 17 16:38:55 2010
$ Running Xilinx xtclsh. See log file:
@N: : xflow.log |
#Wed Feb 17 16:38:55 2010
Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : startup_fpga.vhd(67) | Top entity is set to startup_fpga.
VHDL syntax check successful!
Compiler output is up to date. No re-compile necessary
@N:CD630 : startup_fpga.vhd(67) | Synthesizing work.startup_fpga.rtl
@W:CD280 : startup_fpga.vhd(279) | Unbound component FDS mapped to black box
@N:CD630 : startup_fpga.vhd(279) | Synthesizing work.fds.syn_black_box
Post processing for work.fds.syn_black_box
@W:CD280 : startup_fpga.vhd(292) | Unbound component FD mapped to black box
@W:CD604 : startup_fpga.vhd(362) | OTHERS clause is not synthesized
@N:CD630 : lda_spi_master.vhd(31) | Synthesizing work.lda_spi_master.rtl
@N:CD231 : lda_spi_master.vhd(111) | Using onehot encoding for type spi_states (idle="100000")
@W:CD280 : lda_spi_master.vhd(54) | Unbound component SRL16 mapped to black box
@W:CD604 : lda_spi_master.vhd(238) | OTHERS clause is not synthesized
@N:CD630 : lda_spi_core_master.vhd(26) | Synthesizing work.lda_spi_core_master.rtl
Post processing for work.lda_spi_core_master.rtl
@N:CD630 : lda_spi_master.vhd(54) | Synthesizing work.srl16.syn_black_box
Post processing for work.srl16.syn_black_box
Post processing for work.lda_spi_master.rtl
@W:CL169 : lda_spi_master.vhd(176) | Pruning Register rx_data_sm_i(9 downto 0)
@W:CL169 : lda_spi_master.vhd(159) | Pruning Register rx_data_vld_del_i
@W:CL190 : lda_spi_master.vhd(197) | Optimizing register bit tx_data_sm_i(8) to a constant 0
@W:CL190 : lda_spi_master.vhd(197) | Optimizing register bit tx_data_sm_i(9) to a constant 0
@W:CL255 : lda_spi_master.vhd(197) | Pruning Register bit 9 of tx_data_sm_i(9 downto 0)
@W:CL255 : lda_spi_master.vhd(197) | Pruning Register bit 8 of tx_data_sm_i(9 downto 0)
@N:CD630 : onewire_iface.vhd(65) | Synthesizing work.onewire_iface.rtl
@W:CD280 : onewire_iface.vhd(106) | Unbound component PULLUP mapped to black box
@N:CD630 : onewire_iface.vhd(106) | Synthesizing work.pullup.syn_black_box
Post processing for work.pullup.syn_black_box
@N:CD630 : onewire_master.vhd(86) | Synthesizing work.onewire_master.rtl
@N:CD231 : onewire_master.vhd(207) | Using onehot encoding for type fsmstate (init="100000")
@W:CD280 : onewire_master.vhd(138) | Unbound component IOBUF mapped to black box
@N:CD630 : crcreg.vhd(33) | Synthesizing work.crcreg.arch1
Post processing for work.crcreg.arch1
@N:CD630 : bytereg.vhd(25) | Synthesizing work.bytereg.arch1
Post processing for work.bytereg.arch1
@N:CD630 : bitreg.vhd(26) | Synthesizing work.bitreg.arch1
Post processing for work.bitreg.arch1
@N:CD630 : jcounter.vhd(25) | Synthesizing work.jcounter.arch1
Post processing for work.jcounter.arch1
@N:CD630 : jcounter.vhd(25) | Synthesizing work.jcounter.arch1
Post processing for work.jcounter.arch1
@N:CD630 : shreg.vhd(25) | Synthesizing work.shreg.arch1
Post processing for work.shreg.arch1
@N:CD630 : shreg.vhd(25) | Synthesizing work.shreg.arch1
Post processing for work.shreg.arch1
@N:CD630 : onewire_master.vhd(138) | Synthesizing work.iobuf.syn_black_box
Post processing for work.iobuf.syn_black_box
Post processing for work.onewire_master.rtl
@N:CD630 : clk_div.vhd(46) | Synthesizing work.clk_divider.rtl
Post processing for work.clk_divider.rtl
Post processing for work.onewire_iface.rtl
@N:CD630 : dcm_block.vhd(27) | Synthesizing work.dcm_block.rtl
@W:CD280 : dcm_block.vhd(82) | Unbound component BUFGMUX mapped to black box
@W:CD280 : dcm_block.vhd(43) | Unbound component DCM mapped to black box
@W:CD326 : dcm_block.vhd(113) | Port clkfx180 of entity work.dcm is unconnected
@W:CD326 : dcm_block.vhd(113) | Port clkfx of entity work.dcm is unconnected
@W:CD326 : dcm_block.vhd(113) | Port clkdv of entity work.dcm is unconnected
@W:CD326 : dcm_block.vhd(113) | Port clk90 of entity work.dcm is unconnected
@W:CD326 : dcm_block.vhd(113) | Port clk2x180 of entity work.dcm is unconnected
@W:CD326 : dcm_block.vhd(113) | Port clk270 of entity work.dcm is unconnected
@W:CD326 : dcm_block.vhd(113) | Port clk180 of entity work.dcm is unconnected
@N:CD630 : dcm_block.vhd(43) | Synthesizing work.dcm.syn_black_box
Post processing for work.dcm.syn_black_box
@W:CD638 : dcm_block.vhd(98) | Signal dcm0_clkin is undriven
@N:CD630 : dcm_block.vhd(82) | Synthesizing work.bufgmux.syn_black_box
Post processing for work.bufgmux.syn_black_box
Post processing for work.dcm_block.rtl
@N:CD630 : startup_fpga.vhd(292) | Synthesizing work.fd.syn_black_box
Post processing for work.fd.syn_black_box
@N:CD630 : debounce.vhd(27) | Synthesizing work.debounce.rtl
Post processing for work.debounce.rtl
Post processing for work.startup_fpga.rtl
@N:CL201 : onewire_master.vhd(583) | Trying to extract state machine for register thisState
Extracted state machine for register thisState
State machine has 6 reachable states with original encodings of:
000001
000010
000100
001000
010000
100000
@W:CL255 : lda_spi_core_master.vhd(138) | Pruning Register bit 9 of spi_buffer_tx(9 downto 0)
@W:CL190 : lda_spi_master.vhd(176) | Optimizing register bit tx_data_i(8) to a constant 0
@W:CL190 : lda_spi_master.vhd(176) | Optimizing register bit tx_data_i(9) to a constant 0
@W:CL255 : lda_spi_master.vhd(176) | Pruning Register bit 9 of tx_data_i(9 downto 0)
@W:CL255 : lda_spi_master.vhd(176) | Pruning Register bit 8 of tx_data_i(9 downto 0)
@N:CL201 : lda_spi_master.vhd(197) | Trying to extract state machine for register spi_state_i
Extracted state machine for register spi_state_i
State machine has 6 reachable states with original encodings of:
000001
000010
000100
001000
010000
100000
@W:CL249 : lda_spi_master.vhd(197) | Initial value is not supported on state machine spi_state_i
@W:CL247 : startup_fpga.vhd(80) | Input port bit 4 of swdip(8 downto 1) is unused
@W:CL159 : startup_fpga.vhd(74) | Input RTC_32KHZ is unused
@W:CL159 : startup_fpga.vhd(81) | Input RESET3_N is unused
@W:CL159 : startup_fpga.vhd(82) | Input RESET4_N is unused
@W:CL158 : startup_fpga.vhd(96) | Inout S2000_INIT_B is unused
@W:CL159 : startup_fpga.vhd(113) | Input EXPANSION_RW is unused
@W:CL159 : startup_fpga.vhd(131) | Input RTC_IRQ0_N is unused
@W:CL159 : startup_fpga.vhd(132) | Input RTC_IRQ1_N is unused
@W:CL159 : startup_fpga.vhd(137) | Input ETH_SD_IN is unused
@W:CL159 : startup_fpga.vhd(138) | Input ETH_INT_N is unused
@W:CL158 : startup_fpga.vhd(140) | Inout MAC_ADDRESS2 is unused
@W:CL159 : startup_fpga.vhd(144) | Input RXD is unused
@W:CL159 : startup_fpga.vhd(146) | Input CTS_N is unused
@W:CL159 : startup_fpga.vhd(147) | Input DSR_N is unused
@W:CL159 : startup_fpga.vhd(148) | Input DCD_N is unused
@W:CL159 : startup_fpga.vhd(150) | Input R_N is unused
@W:CL158 : startup_fpga.vhd(151) | Inout USB_CBUS is unused
@W:CL158 : startup_fpga.vhd(154) | Inout PS2_1_1 is unused
@W:CL158 : startup_fpga.vhd(155) | Inout PS2_1_2 is unused
@W:CL158 : startup_fpga.vhd(156) | Inout PS2_1_5 is unused
@W:CL158 : startup_fpga.vhd(157) | Inout PS2_1_6 is unused
@W:CL158 : startup_fpga.vhd(158) | Inout PS2_2_1 is unused
@W:CL158 : startup_fpga.vhd(161) | Inout PS2_2_6 is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Feb 17 16:38:56 2010
###########################################################]
Synopsys Xilinx Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 15:26:45
Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
Product Version C-2009.06
Reading constraint file: /home/warren/calicedaq/LDA/firmware/source/startup/startup_fpga.sdc
@N:MF249 : | Running in 64-bit mode.
@N:MF257 : | Gated clock conversion enabled
Adding property xc_loc, value "A12", to instance CLOCK1_ENABLE
Adding property syn_pad_type, value "LVCMOS_33", to instance CLOCK1_ENABLE
Adding property xc_loc, value "C8", to instance CLOCK2_ENABLE
Adding property syn_pad_type, value "LVCMOS_33", to instance CLOCK2_ENABLE
Adding property xc_loc, value "N13", to instance EN2
Adding property syn_pad_type, value "LVCMOS_33", to instance EN2
Adding property xc_loc, value "P15", to instance EN3
Adding property syn_pad_type, value "LVCMOS_33", to instance EN3
Adding property xc_loc, value "L16", to instance EN5
Adding property syn_pad_type, value "LVCMOS_33", to instance EN5
Adding property xc_loc, value "L14", to instance EN6
Adding property syn_pad_type, value "LVCMOS_33", to instance EN6
Adding property xc_loc, value "M15", to instance EN7
Adding property syn_pad_type, value "LVCMOS_33", to instance EN7
Adding property xc_loc, value "N16", to instance EN8
Adding property syn_pad_type, value "LVCMOS_33", to instance EN8
Adding property xc_loc, value "L13", to instance EN9
Adding property syn_pad_type, value "LVCMOS_33", to instance EN9
Adding property xc_loc, value "C13", to instance ETH_SCLK
Adding property syn_pad_type, value "LVCMOS_33", to instance ETH_SCLK
Adding property xc_loc, value "A10", to instance ETH_SD_OUT
Adding property syn_pad_type, value "LVCMOS_33", to instance ETH_SD_OUT
Adding property xc_loc, value "E13", to instance MAIN_ON_1V2_N
Adding property syn_pad_type, value "LVCMOS_33", to instance MAIN_ON_1V2_N
Adding property xc_loc, value "F15", to instance MAIN_ON_3V3_N
Adding property syn_pad_type, value "LVCMOS_33", to instance MAIN_ON_3V3_N
Adding property xc_loc, value "A13", to instance SPI_CS_B_N
Adding property syn_pad_type, value "LVCMOS_33", to instance SPI_CS_B_N
Adding property xc_loc, value "C12", to instance SPI_CS_RTC_N
Adding property syn_pad_type, value "LVCMOS_33", to instance SPI_CS_RTC_N
Adding property xc_loc, value "T8", to instance EXPANSION_A_DN
Adding property syn_pad_type, value "LVCMOS_25", to instance EXPANSION_A_DN
Adding property xc_loc, value "N12", to instance PF_ENABLE_N
Adding property syn_pad_type, value "LVCMOS_25", to instance PF_ENABLE_N
Adding property xc_loc, value "B14", to instance SPI_WP
Adding property syn_pad_type, value "LVCMOS_33", to instance SPI_WP
Adding property xc_loc, value "P7", to instance TDO_CONNECTOR
Adding property syn_pad_type, value "LVCMOS_25", to instance TDO_CONNECTOR
Adding property xc_loc, value "R14", to instance SPI_SCLK
Adding property syn_pad_type, value "LVCMOS_25", to instance SPI_SCLK
Adding property xc_loc, value "P10", to instance SPI_SD_MOSI
Adding property syn_pad_type, value "LVCMOS_25", to instance SPI_SD_MOSI
Adding property xc_loc, value "K3", to instance CLOCK3_P
Adding property syn_pad_type, value "LVCMOS_25", to instance CLOCK3_P
Adding property xc_loc, value "A4", to instance RESET_S2000
Adding property syn_pad_type, value "LVCMOS_33", to instance RESET_S2000
Adding property xc_loc, value "A8", to port CLOCK_SOURCE_1400
Adding property syn_pad_type, value "LVCMOS_33", to port CLOCK_SOURCE_1400
Adding property xc_loc, value "P8", to port CLOCK_10MHZ
Adding property syn_pad_type, value "LVCMOS_25", to port CLOCK_10MHZ
Adding property xc_loc, value "C9", to port OSC_25MHZ
Adding property syn_pad_type, value "LVCMOS_33", to port OSC_25MHZ
Adding property xc_loc, value "C10", to port RTC_32KHZ
Adding property syn_pad_type, value "LVCMOS_33", to port RTC_32KHZ
Adding property xc_loc, value "B8", to port CLOCK1
Adding property syn_pad_type, value "LVCMOS_33", to port CLOCK1
Adding property xc_loc, value "D8", to port CLOCK2
Adding property syn_pad_type, value "LVCMOS_33", to port CLOCK2
Adding property xc_loc, value "A12", to port CLOCK1_ENABLE
Adding property syn_pad_type, value "LVCMOS_33", to port CLOCK1_ENABLE
Adding property xc_loc, value "C8", to port CLOCK2_ENABLE
Adding property syn_pad_type, value "LVCMOS_33", to port CLOCK2_ENABLE
Adding property xc_pullup, value 1, to port SWDIP[8:1]
Adding property xc_loc, value "A7", to port RESET3_N
Adding property syn_pad_type, value "LVCMOS_33", to port RESET3_N
Adding property xc_pullup, value 1, to port RESET3_N
Adding property xc_loc, value "A14", to port RESET4_N
Adding property syn_pad_type, value "LVCMOS_33", to port RESET4_N
Adding property xc_pullup, value 1, to port RESET4_N
Adding property xc_loc, value "A9", to port S3_POWER_GOOD1
Adding property syn_pad_type, value "LVCMOS_33", to port S3_POWER_GOOD1
Adding property xc_pullup, value 1, to port S3_POWER_GOOD1
Adding property xc_loc, value "R15", to port S3_POWER_GOOD2
Adding property syn_pad_type, value "LVCMOS_33", to port S3_POWER_GOOD2
Adding property xc_pullup, value 1, to port S3_POWER_GOOD2
Adding property xc_loc, value "N8", to port TDI_CONNECTOR
Adding property syn_pad_type, value "LVCMOS_25", to port TDI_CONNECTOR
Adding property xc_pullup, value 1, to port TDI_CONNECTOR
Adding property xc_loc, value "N2", to port TCK_CONNECTOR
Adding property syn_pad_type, value "LVCMOS_25", to port TCK_CONNECTOR
Adding property xc_pullup, value 1, to port TCK_CONNECTOR
Adding property xc_loc, value "N3", to port TMS_CONNECTOR
Adding property syn_pad_type, value "LVCMOS_25", to port TMS_CONNECTOR
Adding property xc_pullup, value 1, to port TMS_CONNECTOR
Adding property xc_loc, value "P7", to port TDO_CONNECTOR
Adding property syn_pad_type, value "LVCMOS_25", to port TDO_CONNECTOR
Adding property xc_loc, value "M4", to port FPGA_TDI
Adding property syn_pad_type, value "LVCMOS_25", to port FPGA_TDI
Adding property xc_pullup, value 1, to port FPGA_TDI
Adding property xc_loc, value "L3", to port FPGA_TCK
Adding property syn_pad_type, value "LVCMOS_25", to port FPGA_TCK
Adding property xc_pullup, value 1, to port FPGA_TCK
Adding property xc_loc, value "L2", to port FPGA_TMS
Adding property syn_pad_type, value "LVCMOS_25", to port FPGA_TMS
Adding property xc_pullup, value 1, to port FPGA_TMS
Adding property xc_loc, value "M3", to port FPGA_TDO
Adding property syn_pad_type, value "LVCMOS_25", to port FPGA_TDO
Adding property xc_loc, value "P13", to port S2000_INIT_B
Adding property syn_pad_type, value "LVCMOS_25", to port S2000_INIT_B
Adding property xc_pullup, value 1, to port S2000_INIT_B
Adding property xc_loc, value "R11", to port S2000_DONE
Adding property syn_pad_type, value "LVCMOS_25", to port S2000_DONE
Adding property xc_pullup, value 1, to port S2000_DONE
Adding property xc_loc, value "L4", to port S2000_PROG_B
Adding property syn_pad_type, value "LVCMOS_25", to port S2000_PROG_B
Adding property xc_pullup, value 1, to port S2000_PROG_B
Adding property xc_loc, value "R13", to port S2000_SERAL_DIN
Adding property syn_pad_type, value "LVCMOS_25", to port S2000_SERAL_DIN
Adding property xc_loc, value "T10", to port S2000_CCLK
Adding property syn_pad_type, value "LVCMOS_25", to port S2000_CCLK
Adding property xc_loc, value "N12", to port PF_ENABLE_N
Adding property syn_pad_type, value "LVCMOS_25", to port PF_ENABLE_N
Adding property xc_loc, value "K3", to port CLOCK3_P
Adding property syn_pad_type, value "LVCMOS_25", to port CLOCK3_P
Adding property xc_loc, value "K1", to port CLOCK3_N
Adding property syn_pad_type, value "LVCMOS_25", to port CLOCK3_N
Adding property xc_loc, value "H3", to port CLOCK4_P
Adding property syn_pad_type, value "LVCMOS_25", to port CLOCK4_P
Adding property xc_loc, value "J3", to port CLOCK4_N
Adding property syn_pad_type, value "LVCMOS_25", to port CLOCK4_N
Adding property xc_loc, value "T7", to port EXPANSION_RW
Adding property syn_pad_type, value "LVCMOS_25", to port EXPANSION_RW
Adding property xc_loc, value "P12", to port EXPANSION_CS
Adding property syn_pad_type, value "LVCMOS_25", to port EXPANSION_CS
Adding property xc_pulldown, value 1, to port EXPANSION_CS
Adding property xc_loc, value "T8", to port EXPANSION_A_DN
Adding property syn_pad_type, value "LVCMOS_25", to port EXPANSION_A_DN
Adding property xc_loc, value "A4", to port RESET_S2000
Adding property syn_pad_type, value "LVCMOS_33", to port RESET_S2000
Adding property xc_loc, value "A3", to port D_RESET_N
Adding property syn_pad_type, value "LVCMOS_33", to port D_RESET_N
Adding property xc_loc, value "T2", to port SPI_CS_A_N
Adding property syn_pad_type, value "LVCMOS_25", to port SPI_CS_A_N
Adding property xc_loc, value "A13", to port SPI_CS_B_N
Adding property syn_pad_type, value "LVCMOS_33", to port SPI_CS_B_N
Adding property xc_loc, value "R14", to port SPI_SCLK
Adding property syn_pad_type, value "LVCMOS_25", to port SPI_SCLK
Adding property xc_loc, value "P10", to port SPI_SD_MOSI
Adding property syn_pad_type, value "LVCMOS_25", to port SPI_SD_MOSI
Adding property xc_loc, value "T14", to port SPI_SD_OUT
Adding property syn_pad_type, value "LVCMOS_25", to port SPI_SD_OUT
Adding property xc_loc, value "B14", to port SPI_WP
Adding property syn_pad_type, value "LVCMOS_33", to port SPI_WP
Adding property xc_loc, value "C12", to port SPI_CS_RTC_N
Adding property syn_pad_type, value "LVCMOS_33", to port SPI_CS_RTC_N
Adding property xc_loc, value "C11", to port RTC_IRQ0_N
Adding property syn_pad_type, value "LVCMOS_25", to port RTC_IRQ0_N
Adding property xc_loc, value "G4", to port RTC_IRQ1_N
Adding property syn_pad_type, value "LVCMOS_25", to port RTC_IRQ1_N
Adding property xc_loc, value "C13", to port ETH_SCLK
Adding property syn_pad_type, value "LVCMOS_33", to port ETH_SCLK
Adding property xc_loc, value "A10", to port ETH_SD_OUT
Adding property syn_pad_type, value "LVCMOS_33", to port ETH_SD_OUT
Adding property xc_loc, value "A11", to port ETH_SD_IN
Adding property syn_pad_type, value "LVCMOS_33", to port ETH_SD_IN
Adding property xc_loc, value "B12", to port ETH_INT_N
Adding property syn_pad_type, value "LVCMOS_33", to port ETH_INT_N
Adding property xc_loc, value "N14", to port MAC_ADDRESS1
Adding property syn_pad_type, value "LVCMOS_33", to port MAC_ADDRESS1
Adding property xc_loc, value "P16", to port MAC_ADDRESS2
Adding property syn_pad_type, value "LVCMOS_33", to port MAC_ADDRESS2
Adding property xc_loc, value "A5", to port TXD
Adding property syn_pad_type, value "LVCMOS_33", to port TXD
Adding property xc_loc, value "C6", to port RXD
Adding property syn_pad_type, value "LVCMOS_33", to port RXD
Adding property xc_loc, value "P6", to port RTS_N
Adding property syn_pad_type, value "LVCMOS_25", to port RTS_N
Adding property xc_loc, value "D11", to port CTS_N
Adding property syn_pad_type, value "LVCMOS_33", to port CTS_N
Adding property xc_loc, value "D7", to port DSR_N
Adding property syn_pad_type, value "LVCMOS_33", to port DSR_N
Adding property xc_loc, value "B10", to port DCD_N
Adding property syn_pad_type, value "LVCMOS_33", to port DCD_N
Adding property xc_loc, value "J4", to port DTR_N
Adding property syn_pad_type, value "LVCMOS_25", to port DTR_N
Adding property xc_loc, value "E7", to port R_N
Adding property syn_pad_type, value "LVCMOS_33", to port R_N
Adding property xc_loc, value "G16", to port PS2_1_1
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_1
Adding property xc_loc, value "H16", to port PS2_1_2
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_2
Adding property xc_loc, value "G13", to port PS2_1_5
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_5
Adding property xc_loc, value "H15", to port PS2_1_6
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_1_6
Adding property xc_loc, value "F16", to port PS2_2_1
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_1
Adding property xc_loc, value "F13", to port PS2_2_2
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_2
Adding property xc_loc, value "F14", to port PS2_2_5
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_5
Adding property xc_loc, value "G14", to port PS2_2_6
Adding property syn_pad_type, value "LVCMOS_33", to port PS2_2_6
Adding property xc_loc, value "N13", to port EN2
Adding property syn_pad_type, value "LVCMOS_33", to port EN2
Adding property xc_loc, value "P15", to port EN3
Adding property syn_pad_type, value "LVCMOS_33", to port EN3
Adding property xc_loc, value "L16", to port EN5
Adding property syn_pad_type, value "LVCMOS_33", to port EN5
Adding property xc_loc, value "L14", to port EN6
Adding property syn_pad_type, value "LVCMOS_33", to port EN6
Adding property xc_loc, value "M15", to port EN7
Adding property syn_pad_type, value "LVCMOS_33", to port EN7
Adding property xc_loc, value "N16", to port EN8
Adding property syn_pad_type, value "LVCMOS_33", to port EN8
Adding property xc_loc, value "L13", to port EN9
Adding property syn_pad_type, value "LVCMOS_33", to port EN9
Adding property xc_loc, value "F15", to port MAIN_ON_3V3_N
Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_3V3_N
Adding property xc_loc, value "E13", to port MAIN_ON_1V2_N
Adding property syn_pad_type, value "LVCMOS_33", to port MAIN_ON_1V2_N
Adding property xc_loc, value "K14", to port bit SWDIP[1]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[1]
Adding property xc_loc, value "K13", to port bit SWDIP[2]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[2]
Adding property xc_loc, value "K15", to port bit SWDIP[3]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[3]
Adding property xc_loc, value "K16", to port bit SWDIP[4]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[4]
Adding property xc_loc, value "J16", to port bit SWDIP[5]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[5]
Adding property xc_loc, value "J13", to port bit SWDIP[6]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[6]
Adding property xc_loc, value "J12", to port bit SWDIP[7]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[7]
Adding property xc_loc, value "H13", to port bit SWDIP[8]
Adding property syn_pad_type, value "LVCMOS_33", to port bit SWDIP[8]
Adding property xc_loc, value "T9", to port bit S2000_M[0]
Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[0]
Adding property xc_loc, value "P9", to port bit S2000_M[1]
Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[1]
Adding property xc_loc, value "R9", to port bit S2000_M[2]
Adding property syn_pad_type, value "LVCMOS_25", to port bit S2000_M[2]
Adding property xc_loc, value "N9", to port bit EXPANSION_BUS[0]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[0]
Adding property xc_loc, value "N11", to port bit EXPANSION_BUS[1]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[1]
Adding property xc_loc, value "R5", to port bit EXPANSION_BUS[2]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[2]
Adding property xc_loc, value "T5", to port bit EXPANSION_BUS[3]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[3]
Adding property xc_loc, value "T4", to port bit EXPANSION_BUS[4]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[4]
Adding property xc_loc, value "R7", to port bit EXPANSION_BUS[5]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[5]
Adding property xc_loc, value "T6", to port bit EXPANSION_BUS[6]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[6]
Adding property xc_loc, value "P11", to port bit EXPANSION_BUS[7]
Adding property syn_pad_type, value "LVCMOS_25", to port bit EXPANSION_BUS[7]
Adding property xc_loc, value "B4", to port bit LEDS[1]
Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[1]
Adding property xc_loc, value "C4", to port bit LEDS[2]
Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[2]
Adding property xc_loc, value "B3", to port bit LEDS[3]
Adding property syn_pad_type, value "LVCMOS_33", to port bit LEDS[3]
Adding property xc_loc, value "D10", to port bit USB_CBUS[0]
Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[0]
Adding property xc_loc, value "D9", to port bit USB_CBUS[1]
Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[1]
Adding property xc_loc, value "A6", to port bit USB_CBUS[2]
Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[2]
Adding property xc_loc, value "B6", to port bit USB_CBUS[3]
Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[3]
Adding property xc_loc, value "C7", to port bit USB_CBUS[4]
Adding property syn_pad_type, value "LVCMOS_33", to port bit USB_CBUS[4]
Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt]
Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt]
@N: : | Running in logic synthesis mode without enhanced optimization
@W:FX474 : | User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code
@W:MO111 : startup_fpga.vhd(305) | tristate driver TXD_1 on net TXD_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_SERAL_DIN_1 on net S2000_SERAL_DIN_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver S2000_CCLK_1 on net S2000_CCLK_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver RTS_N_1 on net RTS_N_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver D_RESET_N_1 on net D_RESET_N_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver DTR_N_1 on net DTR_N_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_P_1 on net CLOCK4_P_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK4_N_1 on net CLOCK4_N_1 has its enable tied to GND (module startup_fpga)
@W:MO111 : startup_fpga.vhd(305) | tristate driver CLOCK3_N_1 on net CLOCK3_N_1 has its enable tied to GND (module startup_fpga)
Automatic dissolve at startup in view:work.onewire_master(rtl) of crcgen\.crcreg_i(CRCReg)
Automatic dissolve at startup in view:work.onewire_master(rtl) of bytereg_i(ByteReg)
Automatic dissolve at startup in view:work.onewire_master(rtl) of bitreg_i(BitReg)
Automatic dissolve at startup in view:work.onewire_master(rtl) of jcnt2(JCounterZ0)
Automatic dissolve at startup in view:work.onewire_master(rtl) of jcnt1(JCounterZ1)
Automatic dissolve at startup in view:work.onewire_master(rtl) of sr2(SHRegZ0)
Automatic dissolve at startup in view:work.onewire_master(rtl) of sr1(SHRegZ1)
Automatic dissolve at startup in view:work.onewire_iface(rtl) of clkdivider(clk_divider)
Automatic dissolve at startup in view:work.startup_fpga(rtl) of dcm_block_3(dcm_block)
Automatic dissolve at startup in view:work.startup_fpga(rtl) of dcm_block_2(dcm_block)
Automatic dissolve at startup in view:work.startup_fpga(rtl) of dcm_block_1(dcm_block)
Automatic dissolve at startup in view:work.startup_fpga(rtl) of dcm_block_0(dcm_block)
Available hyper_sources - for debug and ip models
None Found
@N:MT204 : | Because following clock(s) are defined in SDC file, Autoconstrain mode is TURNED OFF
OSC_25MHZ
CLOCK_10MHZ
CLOCK1
CLOCK2
one_wire_serial.clkdivider.clk_gen
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 123MB)
Encoding state machine work.onewire_master(rtl)-thisState[0:5]
original code -> new code
000001 -> 000001
000010 -> 000010
000100 -> 000100
001000 -> 001000
010000 -> 010000
100000 -> 100000
Encoding state machine work.lda_spi_master(rtl)-spi_state_i[0:5]
original code -> new code
000001 -> 000001
000010 -> 000010
000100 -> 000100
001000 -> 001000
010000 -> 010000
100000 -> 100000
@N:BN116 : lda_spi_core_master.vhd(138) | Removing sequential instance spi_buffer_tx[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_master.vhd(197) | Removing sequential instance MAIN_SPI_INTERFACE.spi_usable of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_master.vhd(235) | Removing sequential instance MAIN_SPI_INTERFACE.spi_state_i[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(68) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.sclk_rising of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.rx_bit_counter[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.rx_bit_counter[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.rx_bit_counter[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.rx_bit_counter[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.rx_spi_cs of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.spi_buffer_rx[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : lda_spi_core_master.vhd(97) | Removing sequential instance MAIN_SPI_INTERFACE.SPI_Core_Master.rx_data_vld of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:BN116 : onewire_master.vhd(320) | Removing sequential instance one_wire_serial.ow_master_i.data_valid of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 123MB)
#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
======================================================================================
Instance:Pin Generated Clock Optimization Status
======================================================================================
one_wire_serial.ow_master_i.thisState[0]:C Done
one_wire_serial.ow_master_i.thisState[1]:C Done
one_wire_serial.ow_master_i.thisState[2]:C Done
one_wire_serial.ow_master_i.thisState[3]:C Done
one_wire_serial.ow_master_i.thisState[4]:C Done
one_wire_serial.ow_master_i.thisState[5]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.1.othersb.otherff.qt[1]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.3.othersb.otherff.qt[3]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.2.othersb.otherff.qt[2]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.4.othersb.otherff.qt[4]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.5.othersb.otherff.qt[5]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.6.othersb.otherff.qt[6]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.7.othersb.otherff.qt[7]:C Done
one_wire_serial.ow_master_i.sr1.pro1.rArray.0.lsb.lsbff.qt[0]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.1.othersb.otherff.qt[1]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.3.othersb.otherff.qt[3]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.0.lsb.lsbff.qt[0]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.2.othersb.otherff.qt[2]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.4.othersb.otherff.qt[4]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.5.othersb.otherff.qt[5]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.6.othersb.otherff.qt[6]:C Done
one_wire_serial.ow_master_i.sr2.pro1.rArray.7.othersb.otherff.qt[7]:C Done
one_wire_serial.ow_master_i.jcnt1.qi[1]:C Done
one_wire_serial.ow_master_i.jcnt1.qi[0]:C Done
one_wire_serial.ow_master_i.jcnt2.qi[9]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[8]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[7]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[6]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[5]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[4]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[3]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[2]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[1]:C Not Done
one_wire_serial.ow_master_i.jcnt2.qi[0]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.0.lpl.dout[0]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.1.lpl.dout[1]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.2.lpl.dout[2]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.3.lpl.dout[3]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.4.lpl.dout[4]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.5.lpl.dout[5]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.6.lpl.dout[6]:C Not Done
one_wire_serial.ow_master_i.bitreg_i.gen0.7.lpl.dout[7]:C Not Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[7]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[6]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[5]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[4]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[3]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[2]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[1]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.0.lpl.dout[0]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[15]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[14]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[13]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[12]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[11]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[10]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[9]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.1.lpl.dout[8]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[23]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[22]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[21]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[20]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[19]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[18]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[17]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.2.lpl.dout[16]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[31]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[30]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[29]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[28]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[27]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[26]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[25]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.3.lpl.dout[24]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[39]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[38]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[37]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[36]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[35]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[34]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[33]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.4.lpl.dout[32]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[47]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[46]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[45]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[44]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[43]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[42]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[41]:C Done
one_wire_serial.ow_master_i.bytereg_i.gen0.5.lpl.dout[40]:C Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.0.othersb.othersff.qt[0]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.5.othersb.othersff.qt[5]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.4.othersb.othersff.qt[4]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.7.msb.msbff.qt[7]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.6.othersb.othersff.qt[6]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.2.feedbackb.feedbackf.qt[2]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.3.feedbackb.feedbackf.qt[3]:C Not Done
one_wire_serial.ow_master_i.crcgen.crcreg_i.rArray.1.othersb.othersff.qt[1]:C Not Done
one_wire_serial.ow_master_i.din_pp:C Done
one_wire_serial.ow_master_i.crcok_i:C Not Done
##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 123MB)
@N:FX430 : | Found 4 global buffers instantiated by user
Clock Buffers:
Inserting Clock buffer for port CLOCK_SOURCE_1400, Inserting Clock buffer on net one_wire_serial.clk_1MHz, Inserting Clock buffer for port CLOCK_10MHZ, Inserting Clock buffer for port OSC_25MHZ, Inserting Clock buffer for port CLOCK1, Inserting Clock buffer for port CLOCK2,
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Net buffering Report for view:work.startup_fpga(rtl):
No nets needed buffering.
@N:MF322 : | Retiming summary: 0 registers retimed to 0
##### BEGIN RETIMING REPORT #####
Retiming summary : 0 registers retimed to 0
Original and Pipelined registers replaced by retiming :
None
New registers created by retiming :
None
##### END RETIMING REPORT #####
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
@N:FX164 : | The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 123MB)
@W:BN105 : | Cannot apply constraint xc_loc to CSN_ETH
@W:BN105 : | Cannot apply constraint xc_pulldown to S2000_HSWAP_EN
@W:BN105 : | Cannot apply constraint syn_pad_type to S2000_HSWAP_EN
@W:BN105 : | Cannot apply constraint syn_pad_type to CSN_ETH
Writing Analyst data base /home/warren/calicedaq/LDA/firmware/syn/startup/md2_startup/rev_1/md2_startup.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 123MB)
Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/netattr.txt]
C-2009.06
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 123MB)
Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 123MB)
@N:MF276 : | Gated clock conversion enabled, but no gated clocks found in design
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 123MB)
Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 123MB)
@N:MF333 : | Generated clock conversion enabled, but no generated clocks found in design
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 123MB)
Found clock startup_fpga|CLOCK_SOURCE_1400 with period 1000.00ns
Found clock CLOCK_10MHZ with period 100.00ns
Found clock OSC_25MHZ with period 40.00ns
Found clock CLOCK1 with period 20.00ns
Found clock CLOCK2 with period 20.00ns
Found clock startup_fpga|dcm_block_0.DCM0_CLK2X_derived_clock with period 10.00ns
Found clock startup_fpga|dcm_block_0.DCM0_CLK0_derived_clock with period 20.00ns
Found clock startup_fpga|dcm_block_1.DCM0_CLK2X_derived_clock with period 10.00ns
Found clock startup_fpga|dcm_block_1.DCM0_CLK0_derived_clock with period 20.00ns
Found clock startup_fpga|dcm_block_2.DCM0_CLK2X_derived_clock with period 20.00ns
Found clock startup_fpga|dcm_block_2.DCM0_CLK0_derived_clock with period 40.00ns
Found clock startup_fpga|dcm_block_3.DCM0_CLK2X_derived_clock with period 50.00ns
Found clock startup_fpga|dcm_block_3.DCM0_CLK0_derived_clock with period 100.00ns
Found clock one_wire_serial.clkdivider.clk_gen with period 1000.00ns
Found clock onewire_master|jcnt2.jc2_q_inferred_clock[9] with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Feb 17 16:38:59 2010
#
Top view: startup_fpga
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): /home/warren/calicedaq/LDA/firmware/source/startup/startup_fpga.sdc
@N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: 17.660
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------------------
CLOCK1 50.0 MHz 427.4 MHz 20.000 2.340 17.660 declared default_clkgroup_2
CLOCK2 50.0 MHz 427.4 MHz 20.000 2.340 17.660 declared default_clkgroup_3
CLOCK_10MHZ 10.0 MHz 427.4 MHz 100.000 2.340 97.660 declared default_clkgroup_1
OSC_25MHZ 25.0 MHz 427.4 MHz 40.000 2.340 37.660 declared default_clkgroup_0
one_wire_serial.clkdivider.clk_gen 1.0 MHz 140.2 MHz 1000.000 7.133 992.867 declared default_clkgroup_4
startup_fpga|CLOCK_SOURCE_1400 1.0 MHz 153.4 MHz 1000.000 6.517 993.483 inferred Autoconstr_clkgroup_0
=============================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------
OSC_25MHZ OSC_25MHZ | 40.000 37.660 | No paths - | No paths - | No paths -
CLOCK_10MHZ CLOCK_10MHZ | 100.000 97.660 | No paths - | No paths - | No paths -
CLOCK1 CLOCK1 | 20.000 17.660 | No paths - | No paths - | No paths -
CLOCK2 CLOCK2 | 20.000 17.660 | No paths - | No paths - | No paths -
one_wire_serial.clkdivider.clk_gen one_wire_serial.clkdivider.clk_gen | 1000.000 992.867 | No paths - | No paths - | No paths -
one_wire_serial.clkdivider.clk_gen startup_fpga|CLOCK_SOURCE_1400 | Diff grp - | No paths - | No paths - | No paths -
startup_fpga|CLOCK_SOURCE_1400 startup_fpga|CLOCK_SOURCE_1400 | 1000.000 993.483 | No paths - | No paths - | No paths -
================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: CLOCK1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------
dcm_block_0.relock_dcm0\.local_rst_sr[1] CLOCK1 FDC Q local_rst_sr[1] 0.720 17.660
dcm_block_0.relock_dcm0\.local_rst_sr[2] CLOCK1 FDC Q local_rst_sr[2] 0.720 17.660
dcm_block_0.DCM0_LOCKED_DEL CLOCK1 FDC Q DCM0_LOCKED_DEL 0.720 17.710
dcm_block_0.relock_dcm0\.local_rst_sr[3] CLOCK1 FDC Q local_rst_sr[3] 0.720 17.710
dcm_block_0.relock_dcm0\.local_rst_sr[0] CLOCK1 FDP Q local_rst_sr[0] 0.720 18.197
=================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------
dcm_block_0.DCM0_RST CLOCK1 FDCP D N_60_i 19.889 17.660
dcm_block_0.relock_dcm0\.local_rst_sr[0] CLOCK1 FDP D local_rst_sr_2[0] 19.889 17.710
dcm_block_0.relock_dcm0\.local_rst_sr[2] CLOCK1 FDC D local_rst_sr[1] 19.797 18.147
dcm_block_0.relock_dcm0\.local_rst_sr[3] CLOCK1 FDC D local_rst_sr[2] 19.797 18.147
dcm_block_0.relock_dcm0\.local_rst_sr[1] CLOCK1 FDC D local_rst_sr[0] 19.797 18.197
====================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 20.000
- Setup time: 0.111
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 19.889
- Propagation time: 2.229
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 17.660
Number of logic level(s): 1
Starting point: dcm_block_0.relock_dcm0\.local_rst_sr[1] / Q
Ending point: dcm_block_0.DCM0_RST / D
The start point is clocked by CLOCK1 [rising] on pin C
The end point is clocked by CLOCK1 [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
dcm_block_0.relock_dcm0\.local_rst_sr[1] FDC Q Out 0.720 0.720 -
local_rst_sr[1] Net - - 0.930 - 2
dcm_block_0.DCM0_RST_RNO LUT3_L I0 In - 1.650 -
dcm_block_0.DCM0_RST_RNO LUT3_L LO Out 0.579 2.229 -
N_60_i Net - - 0.000 - 1
dcm_block_0.DCM0_RST FDCP D In - 2.229 -
========================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.340 is 1.410(60.3%) logic and 0.930(39.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
====================================
Detailed Report for Clock: CLOCK2
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------
dcm_block_1.relock_dcm0\.local_rst_sr[1] CLOCK2 FDC Q local_rst_sr[1] 0.720 17.660
dcm_block_1.relock_dcm0\.local_rst_sr[2] CLOCK2 FDC Q local_rst_sr[2] 0.720 17.660
dcm_block_1.DCM0_LOCKED_DEL CLOCK2 FDC Q DCM0_LOCKED_DEL 0.720 17.710
dcm_block_1.relock_dcm0\.local_rst_sr[3] CLOCK2 FDC Q local_rst_sr[3] 0.720 17.710
dcm_block_1.relock_dcm0\.local_rst_sr[0] CLOCK2 FDP Q local_rst_sr[0] 0.720 18.197
=================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------
dcm_block_1.DCM0_RST CLOCK2 FDCP D N_59_i 19.889 17.660
dcm_block_1.relock_dcm0\.local_rst_sr[0] CLOCK2 FDP D local_rst_sr_2[0] 19.889 17.710
dcm_block_1.relock_dcm0\.local_rst_sr[2] CLOCK2 FDC D local_rst_sr[1] 19.797 18.147
dcm_block_1.relock_dcm0\.local_rst_sr[3] CLOCK2 FDC D local_rst_sr[2] 19.797 18.147
dcm_block_1.relock_dcm0\.local_rst_sr[1] CLOCK2 FDC D local_rst_sr[0] 19.797 18.197
====================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 20.000
- Setup time: 0.111
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 19.889
- Propagation time: 2.229
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 17.660
Number of logic level(s): 1
Starting point: dcm_block_1.relock_dcm0\.local_rst_sr[1] / Q
Ending point: dcm_block_1.DCM0_RST / D
The start point is clocked by CLOCK2 [rising] on pin C
The end point is clocked by CLOCK2 [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
dcm_block_1.relock_dcm0\.local_rst_sr[1] FDC Q Out 0.720 0.720 -
local_rst_sr[1] Net - - 0.930 - 2
dcm_block_1.DCM0_RST_RNO LUT3_L I0 In - 1.650 -
dcm_block_1.DCM0_RST_RNO LUT3_L LO Out 0.579 2.229 -
N_59_i Net - - 0.000 - 1
dcm_block_1.DCM0_RST FDCP D In - 2.229 -
========================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.340 is 1.410(60.3%) logic and 0.930(39.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
====================================
Detailed Report for Clock: CLOCK_10MHZ
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------
dcm_block_3.relock_dcm0\.local_rst_sr[1] CLOCK_10MHZ FDC Q local_rst_sr[1] 0.720 97.660
dcm_block_3.relock_dcm0\.local_rst_sr[2] CLOCK_10MHZ FDC Q local_rst_sr[2] 0.720 97.660
dcm_block_3.DCM0_LOCKED_DEL CLOCK_10MHZ FDC Q DCM0_LOCKED_DEL 0.720 97.710
dcm_block_3.relock_dcm0\.local_rst_sr[3] CLOCK_10MHZ FDC Q local_rst_sr[3] 0.720 97.710
dcm_block_3.relock_dcm0\.local_rst_sr[0] CLOCK_10MHZ FDP Q local_rst_sr[0] 0.720 98.197
===================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------
dcm_block_3.DCM0_RST CLOCK_10MHZ FDCP D N_57_i 99.889 97.660
dcm_block_3.relock_dcm0\.local_rst_sr[0] CLOCK_10MHZ FDP D local_rst_sr_2[0] 99.889 97.710
dcm_block_3.relock_dcm0\.local_rst_sr[2] CLOCK_10MHZ FDC D local_rst_sr[1] 99.797 98.147
dcm_block_3.relock_dcm0\.local_rst_sr[3] CLOCK_10MHZ FDC D local_rst_sr[2] 99.797 98.147
dcm_block_3.relock_dcm0\.local_rst_sr[1] CLOCK_10MHZ FDC D local_rst_sr[0] 99.797 98.197
======================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 100.000
- Setup time: 0.111
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 99.889
- Propagation time: 2.229
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 97.660
Number of logic level(s): 1
Starting point: dcm_block_3.relock_dcm0\.local_rst_sr[1] / Q
Ending point: dcm_block_3.DCM0_RST / D
The start point is clocked by CLOCK_10MHZ [rising] on pin C
The end point is clocked by CLOCK_10MHZ [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
dcm_block_3.relock_dcm0\.local_rst_sr[1] FDC Q Out 0.720 0.720 -
local_rst_sr[1] Net - - 0.930 - 2
dcm_block_3.DCM0_RST_RNO LUT3_L I0 In - 1.650 -
dcm_block_3.DCM0_RST_RNO LUT3_L LO Out 0.579 2.229 -
N_57_i Net - - 0.000 - 1
dcm_block_3.DCM0_RST FDCP D In - 2.229 -
========================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.340 is 1.410(60.3%) logic and 0.930(39.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
====================================
Detailed Report for Clock: OSC_25MHZ
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------
dcm_block_2.relock_dcm0\.local_rst_sr[1] OSC_25MHZ FDC Q local_rst_sr[1] 0.720 37.660
dcm_block_2.relock_dcm0\.local_rst_sr[2] OSC_25MHZ FDC Q local_rst_sr[2] 0.720 37.660
dcm_block_2.DCM0_LOCKED_DEL OSC_25MHZ FDC Q DCM0_LOCKED_DEL 0.720 37.710
dcm_block_2.relock_dcm0\.local_rst_sr[3] OSC_25MHZ FDC Q local_rst_sr[3] 0.720 37.710
dcm_block_2.relock_dcm0\.local_rst_sr[0] OSC_25MHZ FDP Q local_rst_sr[0] 0.720 38.197
=================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------
dcm_block_2.DCM0_RST OSC_25MHZ FDCP D N_58_i 39.889 37.660
dcm_block_2.relock_dcm0\.local_rst_sr[0] OSC_25MHZ FDP D local_rst_sr_2[0] 39.889 37.710
dcm_block_2.relock_dcm0\.local_rst_sr[2] OSC_25MHZ FDC D local_rst_sr[1] 39.797 38.147
dcm_block_2.relock_dcm0\.local_rst_sr[3] OSC_25MHZ FDC D local_rst_sr[2] 39.797 38.147
dcm_block_2.relock_dcm0\.local_rst_sr[1] OSC_25MHZ FDC D local_rst_sr[0] 39.797 38.197
====================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 40.000
- Setup time: 0.111
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 39.889
- Propagation time: 2.229
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 37.660
Number of logic level(s): 1
Starting point: dcm_block_2.relock_dcm0\.local_rst_sr[1] / Q
Ending point: dcm_block_2.DCM0_RST / D
The start point is clocked by OSC_25MHZ [rising] on pin C
The end point is clocked by OSC_25MHZ [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
dcm_block_2.relock_dcm0\.local_rst_sr[1] FDC Q Out 0.720 0.720 -
local_rst_sr[1] Net - - 0.930 - 2
dcm_block_2.DCM0_RST_RNO LUT3_L I0 In - 1.650 -
dcm_block_2.DCM0_RST_RNO LUT3_L LO Out 0.579 2.229 -
N_58_i Net - - 0.000 - 1
dcm_block_2.DCM0_RST FDCP D In - 2.229 -
========================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 2.340 is 1.410(60.3%) logic and 0.930(39.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
====================================
Detailed Report for Clock: one_wire_serial.clkdivider.clk_gen
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
one_wire_serial.ow_master_i.jcnt1.qi[0] one_wire_serial.clkdivider.clk_gen FDRE Q jc1_q[0] 0.720 992.867
one_wire_serial.ow_master_i.jcnt1.qi[1] one_wire_serial.clkdivider.clk_gen FDRE Q jc1_q[1] 0.720 992.872
one_wire_serial.ow_master_i.sr1.pro1\.rArray\.7\.othersb\.otherff\.qt[7]one_wire_serial.clkdivider.clk_gen FDRE Q sr1_q[7] 0.720 992.927
one_wire_serial.ow_master_i.jcnt2.qi[9] one_wire_serial.clkdivider.clk_gen FDC Q jc2_q_i[9] 0.720 993.031
one_wire_serial.ow_master_i.jcnt2.qi[0] one_wire_serial.clkdivider.clk_gen FDC Q jc2_q[0] 0.720 993.081
one_wire_serial.ow_master_i.sr2.pro1\.rArray\.6\.othersb\.otherff\.qt[6]one_wire_serial.clkdivider.clk_gen FDRE Q sr2_q[6] 0.720 993.537
one_wire_serial.ow_master_i.thisState[3] one_wire_serial.clkdivider.clk_gen FDCE Q thisState[3] 0.720 993.547
one_wire_serial.ow_master_i.jcnt2.qi[3] one_wire_serial.clkdivider.clk_gen FDC Q jc2_q[3] 0.720 993.611
one_wire_serial.ow_master_i.jcnt2.qi[4] one_wire_serial.clkdivider.clk_gen FDC Q jc2_q[4] 0.720 993.611
one_wire_serial.ow_master_i.din_pp one_wire_serial.clkdivider.clk_gen FDPE Q din_pp 0.720 993.637
====================================================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
one_wire_serial.ow_master_i.crcok_i one_wire_serial.clkdivider.clk_gen FDCE CE un5_sr2_q 999.398 993.381
one_wire_serial.ow_master_i.thisState[0] one_wire_serial.clkdivider.clk_gen FDCE D N_174_i 999.889 994.582
one_wire_serial.ow_master_i.thisState[1] one_wire_serial.clkdivider.clk_gen FDCE D N_175_i 999.889 994.662
one_wire_serial.ow_master_i.thisState[2] one_wire_serial.clkdivider.clk_gen FDCE D N_176_i 999.889 996.041
one_wire_serial.ow_master_i.thisState[4] one_wire_serial.clkdivider.clk_gen FDCE D N_177_i 999.889 996.101
one_wire_serial.ow_master_i.crcgen\.crcreg_i.rArray\.2\.feedbackb\.feedbackf\.qt[2]one_wire_serial.clkdivider.clk_gen FDCE D qt_16[2] 999.889 996.201
one_wire_serial.ow_master_i.crcgen\.crcreg_i.rArray\.3\.feedbackb\.feedbackf\.qt[3]one_wire_serial.clkdivider.clk_gen FDCE D qt_23[3] 999.889 996.201
one_wire_serial.ow_master_i.thisState[5] one_wire_serial.clkdivider.clk_gen FDPE D N_178_i 999.889 996.631
one_wire_serial.ow_master_i.crcgen\.crcreg_i.rArray\.7\.msb\.msbff\.qt[7] one_wire_serial.clkdivider.clk_gen FDCE D feedback 999.797 996.688
one_wire_serial.ow_master_i.jcnt1.qi[0] one_wire_serial.clkdivider.clk_gen FDRE D jc1_q_i[1] 999.889 997.555
==============================================================================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 1.026
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 998.974
- Propagation time: 6.107
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 992.867
Number of logic level(s): 3
Starting point: one_wire_serial.ow_master_i.jcnt1.qi[0] / Q
Ending point: one_wire_serial.ow_master_i.jcnt1.qi[0] / R
The start point is clocked by one_wire_serial.clkdivider.clk_gen [rising] on pin C
The end point is clocked by one_wire_serial.clkdivider.clk_gen [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
one_wire_serial.ow_master_i.jcnt1.qi[0] FDRE Q Out 0.720 0.720 -
jc1_q[0] Net - - 1.040 - 9
one_wire_serial.ow_master_i.nextState_0_sqmuxa_1 LUT3 I0 In - 1.760 -
one_wire_serial.ow_master_i.nextState_0_sqmuxa_1 LUT3 O Out 0.579 2.339 -
nextState_0_sqmuxa_1 Net - - 0.930 - 4
one_wire_serial.ow_master_i.thisState_ns_a6[5] LUT3 I0 In - 3.269 -
one_wire_serial.ow_master_i.thisState_ns_a6[5] LUT3 O Out 0.579 3.848 -
un3_sr2_q Net - - 0.880 - 3
one_wire_serial.ow_master_i.jc1_reset_0_1_RNIO8F3 LUT4 I2 In - 4.728 -
one_wire_serial.ow_master_i.jc1_reset_0_1_RNIO8F3 LUT4 O Out 0.579 5.307 -
jc1_reset_0_1_RNIO8F3 Net - - 0.800 - 2
one_wire_serial.ow_master_i.jcnt1.qi[0] FDRE R In - 6.107 -
================================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 7.133 is 3.483(48.8%) logic and 3.650(51.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
====================================
Detailed Report for Clock: startup_fpga|CLOCK_SOURCE_1400
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------------------------------
debounce_reset.gen_slow_clk startup_fpga|CLOCK_SOURCE_1400 SRL16 Q slow_i 3.426 993.483
debounce_reflash.gen_slow_clk startup_fpga|CLOCK_SOURCE_1400 SRL16 Q slow_i 3.426 993.483
MAIN_SPI_INTERFACE.gen_spi_clk startup_fpga|CLOCK_SOURCE_1400 SRL16 Q MAIN_SPI_CLK_i 3.426 994.504
MAIN_SPI_INTERFACE.SPI_Core_Master.tx_bit_counter[0] startup_fpga|CLOCK_SOURCE_1400 FDCE Q tx_bit_counter[0] 0.720 994.650
MAIN_SPI_INTERFACE.SPI_Core_Master.tx_bit_counter[1] startup_fpga|CLOCK_SOURCE_1400 FDCE Q tx_bit_counter[1] 0.720 994.660
one_wire_serial.clkdivider.srl2 startup_fpga|CLOCK_SOURCE_1400 SRL16 Q q2 3.426 994.683
MAIN_SPI_INTERFACE.SPI_Core_Master.tx_bit_counter[2] startup_fpga|CLOCK_SOURCE_1400 FDCE Q tx_bit_counter[2] 0.720 994.700
MAIN_SPI_INTERFACE.SPI_Core_Master.tx_bit_counter[3] startup_fpga|CLOCK_SOURCE_1400 FDCE Q tx_bit_counter[3] 0.720 994.700
MAIN_SPI_INTERFACE.SPI_Core_Master.tx_data_en startup_fpga|CLOCK_SOURCE_1400 FDCE Q tx_data_en_i 0.720 995.062
MAIN_SPI_INTERFACE.tx_data_en_del_i startup_fpga|CLOCK_SOURCE_1400 FDC Q tx_data_en_del_i 0.720 995.102
=======================================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------
debounce_reset.debounced_out startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reflash.debounced_out startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reset.shift_reg[0] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reflash.shift_reg[0] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reflash.shift_reg[1] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reset.shift_reg[1] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reset.shift_reg[2] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reflash.shift_reg[2] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reset.shift_reg[3] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
debounce_reflash.shift_reg[3] startup_fpga|CLOCK_SOURCE_1400 FDE CE un3_del_i 999.398 993.483
=========================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.602
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 999.398
- Propagation time: 5.915
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 993.483
Number of logic level(s): 1
Starting point: debounce_reset.gen_slow_clk / Q
Ending point: debounce_reset.debounced_out / CE
The start point is clocked by startup_fpga|CLOCK_SOURCE_1400 [rising] on pin CLK
The end point is clocked by startup_fpga|CLOCK_SOURCE_1400 [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
debounce_reset.gen_slow_clk SRL16 Q Out 3.426 3.426 -
slow_i Net - - 0.880 - 3
debounce_reset.check_input\.un3_del_i LUT2 I1 In - 4.306 -
debounce_reset.check_input\.un3_del_i LUT2 O Out 0.579 4.885 -
un3_del_i Net - - 1.030 - 9
debounce_reset.debounced_out FDE CE In - 5.915 -
====================================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 6.517 is 4.607(70.7%) logic and 1.910(29.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------
PULLDOWN_EXPANSION_CS System PULLDOWN O EXPANSION_CS 0.000 996.649
=================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------
S2000_ready_sr_i[0] System FDC D EXPANSION_CS_c 999.797 996.649
==============================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.203
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 999.797
- Propagation time: 3.148
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 996.649
Number of logic level(s): 1
Starting point: PULLDOWN_EXPANSION_CS / O
Ending point: S2000_ready_sr_i[0] / D
The start point is clocked by System [rising]
The end point is clocked by startup_fpga|CLOCK_SOURCE_1400 [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------
PULLDOWN_EXPANSION_CS PULLDOWN O Out 0.000 0.000 -
EXPANSION_CS Net - - 0.000 - 1(2)
EXPANSION_CS_ibuf IBUF I In - 0.000 -
EXPANSION_CS_ibuf IBUF O Out 2.438 2.438 -
EXPANSION_CS_c Net - - 0.710 - 1
S2000_ready_sr_i[0] FDC D In - 3.148 -
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 3.351 is 2.641(78.8%) logic and 0.710(21.2%) route.
Fanout format: logic fanout (physical fanout)
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for startup_fpga
Mapping to part: xc3s400aft256-4
Cell usage:
DCM 4 uses
FD 5 uses
FDC 45 uses
FDCE 151 uses
FDCP 4 uses
FDE 18 uses
FDP 6 uses
FDPE 2 uses
FDRE 16 uses
FDS 1 use
FDSE 2 uses
GND 8 uses
MUXF5 14 uses
MUXF6 2 uses
PULLDOWN 1 use
PULLUP 22 uses
VCC 6 uses
LUT1 3 uses
LUT2 52 uses
LUT3 58 uses
LUT4 54 uses
I/O ports: 102
I/O primitives: 70
IBUF 18 uses
IBUFG 5 uses
IOBUF 1 use
OBUF 33 uses
OBUFT 13 uses
BUFG 6 uses
BUFGMUX 4 uses
SRL primitives:
SRL16 5 uses
I/O Register bits: 0
Register bits not including I/Os: 250 (3%)
Global Clock Buffers: 10 of 24 (41%)
Total load per clock:
startup_fpga|CLOCK_SOURCE_1400: 131
CLOCK1: 7
CLOCK2: 7
OSC_25MHZ: 7
CLOCK_10MHZ: 7
one_wire_serial.clkdivider.clk_gen: 100
Mapping Summary:
Total LUTs: 172 (2%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Feb 17 16:38:59 2010
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