#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
#install: /unix/local/synopsys/synplicity/fpga_c200906
#OS: Linux 
#Hostname: pc140.hep.ucl.ac.uk

#Implementation: rev_1

#Wed Jan 13 14:26:38 2010

$ Start of Compile
#Wed Jan 13 14:26:38 2010

$ Running Xilinx xtclsh. See log file:
@N: : xflow.log | 
#Wed Jan 13 14:26:38 2010

Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : hdmi_module_top_level.vhd(4) | Top entity is set to hdmi_module_top_level.
VHDL syntax check successful!
@N:CD630 : hdmi_module_top_level.vhd(4) | Synthesizing work.hdmi_module_top_level.a0 
@W:CD638 : hdmi_module_top_level.vhd(234) | Signal tx7_utp_p is undriven 
@W:CD638 : hdmi_module_top_level.vhd(235) | Signal tx7_utp_n is undriven 
@W:CD638 : hdmi_module_top_level.vhd(236) | Signal tx8_data_p is undriven 
@W:CD638 : hdmi_module_top_level.vhd(237) | Signal tx8_data_n is undriven 
@W:CD638 : hdmi_module_top_level.vhd(238) | Signal clk8_p is undriven 
@W:CD638 : hdmi_module_top_level.vhd(239) | Signal clk8_n is undriven 
@W:CD638 : hdmi_module_top_level.vhd(284) | Signal rx_7 is undriven 
@W:CD638 : hdmi_module_top_level.vhd(285) | Signal rx_8 is undriven 
@N:CD630 : lvds_drivers_receivers.vhd(4) | Synthesizing work.lvds_drivers_receivers.a0 
@W:CD280 : lvds_drivers_receivers.vhd(28) | Unbound component IBUFDS mapped to black box
@N:CD630 : lvds_drivers_receivers.vhd(28) | Synthesizing work.ibufds.syn_black_box 
Post processing for work.ibufds.syn_black_box
@W:CD280 : lvds_drivers_receivers.vhd(35) | Unbound component OBUFDS mapped to black box
@N:CD630 : lvds_drivers_receivers.vhd(35) | Synthesizing work.obufds.syn_black_box 
Post processing for work.obufds.syn_black_box
Post processing for work.lvds_drivers_receivers.a0
@W:CL240 : lvds_drivers_receivers.vhd(11) | RXD_B is not assigned a value (floating) - a simulation mismatch is possible 
Post processing for work.hdmi_module_top_level.a0
@W:CL240 : hdmi_module_top_level.vhd(285) | RX_8 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(284) | RX_7 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(170) | TX8_UTP_N is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(169) | TX8_UTP_P is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(160) | CLK7_N is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(159) | CLK7_P is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(156) | TX7_DATA_N is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : hdmi_module_top_level.vhd(155) | TX7_DATA_P is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL159 : lvds_drivers_receivers.vhd(6) | Input RESET is unused
@W:CL159 : lvds_drivers_receivers.vhd(12) | Input DIR_CONTROL_OP is unused
@W:CL159 : lvds_drivers_receivers.vhd(16) | Input RX_SP_P is unused
@W:CL159 : lvds_drivers_receivers.vhd(17) | Input RX_SP_N is unused
@W:CL159 : hdmi_module_top_level.vhd(11) | Input J1_A3 is unused
@W:CL159 : hdmi_module_top_level.vhd(12) | Input J1_A4 is unused
@W:CL159 : hdmi_module_top_level.vhd(13) | Input J1_A5 is unused
@W:CL159 : hdmi_module_top_level.vhd(14) | Input J1_A6 is unused
@W:CL159 : hdmi_module_top_level.vhd(15) | Input J1_A7 is unused
@W:CL159 : hdmi_module_top_level.vhd(16) | Input J1_A8 is unused
@W:CL159 : hdmi_module_top_level.vhd(17) | Input J1_A9 is unused
@W:CL159 : hdmi_module_top_level.vhd(18) | Input J1_A10 is unused
@W:CL159 : hdmi_module_top_level.vhd(20) | Input J1_A12 is unused
@W:CL159 : hdmi_module_top_level.vhd(22) | Input J1_A14 is unused
@W:CL159 : hdmi_module_top_level.vhd(23) | Input J1_A15 is unused
@W:CL159 : hdmi_module_top_level.vhd(25) | Input J1_A17 is unused
@W:CL159 : hdmi_module_top_level.vhd(26) | Input J1_A18 is unused
@W:CL159 : hdmi_module_top_level.vhd(28) | Input J1_A20 is unused
@W:CL159 : hdmi_module_top_level.vhd(29) | Input J1_A21 is unused
@W:CL159 : hdmi_module_top_level.vhd(31) | Input J1_A23 is unused
@W:CL159 : hdmi_module_top_level.vhd(32) | Input J1_A24 is unused
@W:CL159 : hdmi_module_top_level.vhd(35) | Input J1_A27 is unused
@W:CL159 : hdmi_module_top_level.vhd(36) | Input J1_A28 is unused
@W:CL159 : hdmi_module_top_level.vhd(37) | Input J1_A29 is unused
@W:CL159 : hdmi_module_top_level.vhd(39) | Input J1_A31 is unused
@W:CL159 : hdmi_module_top_level.vhd(40) | Input J1_A32 is unused
@W:CL159 : hdmi_module_top_level.vhd(45) | Input J8_B3 is unused
@W:CL159 : hdmi_module_top_level.vhd(46) | Input J8_B4 is unused
@W:CL159 : hdmi_module_top_level.vhd(47) | Input J8_B5 is unused
@W:CL159 : hdmi_module_top_level.vhd(48) | Input J8_B6 is unused
@W:CL159 : hdmi_module_top_level.vhd(50) | Input J8_B8 is unused
@W:CL159 : hdmi_module_top_level.vhd(52) | Input J8_B10 is unused
@W:CL159 : hdmi_module_top_level.vhd(54) | Input J8_B12 is unused
@W:CL159 : hdmi_module_top_level.vhd(55) | Input J8_B13 is unused
@W:CL159 : hdmi_module_top_level.vhd(56) | Input J8_B14 is unused
@W:CL159 : hdmi_module_top_level.vhd(57) | Input J8_B15 is unused
@W:CL159 : hdmi_module_top_level.vhd(58) | Input J8_B16 is unused
@W:CL159 : hdmi_module_top_level.vhd(59) | Input J8_B17 is unused
@W:CL159 : hdmi_module_top_level.vhd(62) | Input J8_B20 is unused
@W:CL159 : hdmi_module_top_level.vhd(63) | Input J8_B21 is unused
@W:CL159 : hdmi_module_top_level.vhd(64) | Input J8_B22 is unused
@W:CL159 : hdmi_module_top_level.vhd(66) | Input J8_B24 is unused
@W:CL159 : hdmi_module_top_level.vhd(67) | Input J8_B25 is unused
@W:CL159 : hdmi_module_top_level.vhd(68) | Input J8_B26 is unused
@W:CL159 : hdmi_module_top_level.vhd(69) | Input J8_B27 is unused
@W:CL159 : hdmi_module_top_level.vhd(70) | Input J8_B28 is unused
@W:CL159 : hdmi_module_top_level.vhd(71) | Input J8_B29 is unused
@W:CL159 : hdmi_module_top_level.vhd(72) | Input J8_B30 is unused
@W:CL159 : hdmi_module_top_level.vhd(73) | Input J8_B31 is unused
@W:CL159 : hdmi_module_top_level.vhd(74) | Input J8_B32 is unused
@W:CL159 : hdmi_module_top_level.vhd(151) | Input RX7_DATA_P is unused
@W:CL159 : hdmi_module_top_level.vhd(152) | Input RX7_DATA_N is unused
@W:CL159 : hdmi_module_top_level.vhd(153) | Input RX7_SP_P is unused
@W:CL159 : hdmi_module_top_level.vhd(154) | Input RX7_SP_N is unused
@W:CL159 : hdmi_module_top_level.vhd(163) | Input RX8_DATA_P is unused
@W:CL159 : hdmi_module_top_level.vhd(164) | Input RX8_DATA_N is unused
@W:CL159 : hdmi_module_top_level.vhd(165) | Input RX8_SP_P is unused
@W:CL159 : hdmi_module_top_level.vhd(166) | Input RX8_SP_N is unused
@W:CL159 : hdmi_module_top_level.vhd(199) | Input SPARE2 is unused
@W:CL159 : hdmi_module_top_level.vhd(200) | Input SPARE3 is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 13 14:26:39 2010

###########################################################]
perty syn_pad_type, value "LVCMOS25", to port J8_B5
Adding property syn_pad_type, value "LVCMOS25", to port J8_B6
Adding property syn_pad_type, value "LVCMOS25", to port J8_B7
Adding property syn_pad_type, value "LVCMOS25", to port J8_B8
Adding property syn_pad_type, value "LVCMOS25", to port J8_B9
Adding property syn_pad_type, value "LVCMOS25", to port J8_B10
Adding property syn_pad_type, value "LVCMOS25", to port J8_B11
Adding property syn_pad_type, value "LVCMOS25", to port J8_B12
Adding property syn_pad_type, value "LVCMOS25", to port J8_B13
Adding property syn_pad_type, value "LVCMOS25", to port J8_B14
Adding property syn_pad_type, value "LVCMOS25", to port J8_B15
Adding property syn_pad_type, value "LVCMOS25", to port J8_B16
Adding property syn_pad_type, value "LVCMOS25", to port J8_B17
Adding property syn_pad_type, value "LVCMOS25", to port J8_B18
Adding property syn_pad_type, value "LVCMOS25", to port J8_B19
Adding property syn_pad_type, value "LVCMOS25", to port J8_B20
Adding property syn_pad_type, value "LVCMOS25", to port J8_B21
Adding property syn_pad_type, value "LVCMOS25", to port J8_B22
Adding property syn_pad_type, value "LVCMOS25", to port J8_B23
Adding property syn_pad_type, value "LVCMOS25", to port J8_B24
Adding property syn_pad_type, value "LVCMOS25", to port J8_B25
Adding property syn_pad_type, value "LVCMOS25", to port J8_B26
Adding property syn_pad_type, value "LVCMOS25", to port J8_B27
Adding property syn_pad_type, value "LVCMOS25", to port J8_B28
Adding property syn_pad_type, value "LVCMOS25", to port J8_B29
Adding property syn_pad_type, value "LVCMOS25", to port J8_B30
Adding property syn_pad_type, value "LVCMOS25", to port J8_B31
Adding property syn_pad_type, value "LVCMOS25", to port J8_B32
Adding property syn_pad_type, value "LVCMOS25", to port J8_B33
Adding property syn_pad_type, value "LVCMOS25", to port J8_B34
Adding property syn_pad_type, value "LVCMOS25", to port SPARE2
Adding property syn_pad_type, value "LVCMOS25", to port SPARE3
Adding property xc_loc, value "A12", to port bit RESET_N
Adding property xc_loc, value "A11", to port bit J1_A2
Adding property xc_loc, value "AB11", to port bit J1_A3
Adding property xc_loc, value "B10", to port bit J1_A4
Adding property xc_loc, value "C10", to port bit J1_A5
Adding property xc_loc, value "D9", to port bit J1_A6
Adding property xc_loc, value "A9", to port bit J1_A7
Adding property xc_loc, value "B9", to port bit J1_A8
Adding property xc_loc, value "B8", to port bit J1_A9
Adding property xc_loc, value "B6", to port bit J1_A10
Adding property xc_loc, value "C7", to port bit J1_A11
Adding property xc_loc, value "E7", to port bit J1_A12
Adding property xc_loc, value "D7", to port bit J1_A13
Adding property xc_loc, value "AA4", to port bit J1_A14
Adding property xc_loc, value "AB4", to port bit J1_A15
Adding property xc_loc, value "V6", to port bit J1_A16
Adding property xc_loc, value "W6", to port bit J1_A17
Adding property xc_loc, value "AA6", to port bit J1_A18
Adding property xc_loc, value "Y6", to port bit J1_A19
Adding property xc_loc, value "W8", to port bit J1_A20
Adding property xc_loc, value "V8", to port bit J1_A21
Adding property xc_loc, value "V7", to port bit J1_A22
Adding property xc_loc, value "AB8", to port bit J1_A23
Adding property xc_loc, value "AA8", to port bit J1_A24
Adding property xc_loc, value "AA9", to port bit J1_A25
Adding property xc_loc, value "AB9", to port bit J1_A26
Adding property xc_loc, value "Y10", to port bit J1_A27
Adding property xc_loc, value "AB10", to port bit J1_A28
Adding property xc_loc, value "AB10", to port bit J1_A29
Adding property xc_loc, value "Y11", to port bit J1_A30
Adding property xc_loc, value "W11", to port bit J1_A31
Adding property xc_loc, value "AA11", to port bit J1_A32
Adding property xc_loc, value "AB11", to port bit J1_A33
Adding property xc_loc, value "A15", to port bit J8_B2
Adding property xc_loc, value "B15", to port bit J8_B3
Adding property xc_loc, value "B17", to port bit J8_B4
Adding property xc_loc, value "D18", to port bit J8_B5
Adding property xc_loc, value "C18", to port bit J8_B6
Adding property xc_loc, value "A18", to port bit J8_B7
Adding property xc_loc, value "B18", to port bit J8_B8
Adding property xc_loc, value "B19", to port bit J8_B9
Adding property xc_loc, value "F17", to port bit J8_B10
Adding property xc_loc, value "F16", to port bit J8_B11
Adding property xc_loc, value "E13", to port bit J8_B12
Adding property xc_loc, value "U16", to port bit J8_B13
Adding property xc_loc, value "U17", to port bit J8_B14
Adding property xc_loc, value "V17", to port bit J8_B15
Adding property xc_loc, value "V18", to port bit J8_B16
Adding property xc_loc, value "W18", to port bit J8_B17
Adding property xc_loc, value "Y18", to port bit J8_B18
Adding property xc_loc, value "W17", to port bit J8_B19
Adding property xc_loc, value "W19", to port bit J8_B20
Adding property xc_loc, value "Y17", to port bit J8_B21
Adding property xc_loc, value "AA18", to port bit J8_B22
Adding property xc_loc, value "AB18", to port bit J8_B23
Adding property xc_loc, value "Y16", to port bit J8_B24
Adding property xc_loc, value "V16", to port bit J8_B25
Adding property xc_loc, value "AA15", to port bit J8_B26
Adding property xc_loc, value "AB15", to port bit J8_B27
Adding property xc_loc, value "AA17", to port bit J8_B28
Adding property xc_loc, value "AB14", to port bit J8_B29
Adding property xc_loc, value "AA13", to port bit J8_B30
Adding property xc_loc, value "W16", to port bit J8_B31
Adding property xc_loc, value "AB13", to port bit J8_B32
Adding property xc_loc, value "AA12", to port bit J8_B33
Adding property xc_loc, value "AB12", to port bit J8_B34
Adding property xc_loc, value "L2", to port bit RX1_DATA_P
Adding property xc_loc, value "L1", to port bit RX1_DATA_N
Adding property xc_loc, value "L4", to port bit RX1_SP_P
Adding property xc_loc, value "L3", to port bit RX1_SP_N
Adding property xc_loc, value "L6", to port bit TX1_DATA_P
Adding property xc_loc, value "L5", to port bit TX1_DATA_N
Adding property xc_loc, value "M3", to port bit TX1_UTP_P
Adding property xc_loc, value "M4", to port bit TX1_UTP_N
Adding property xc_loc, value "K2", to port bit CLK1_P
Adding property xc_loc, value "K1", to port bit CLK1_N
Adding property xc_loc, value "M5", to port bit RX2_DATA_P
Adding property xc_loc, value "M6", to port bit RX2_DATA_N
Adding property xc_loc, value "V5", to port bit RX2_SP_P
Adding property xc_loc, value "U5", to port bit RX2_SP_N
Adding property xc_loc, value "T5", to port bit TX2_DATA_P
Adding property xc_loc, value "T6", to port bit TX2_DATA_N
Adding property xc_loc, value "U2", to port bit TX2_UTP_P
Adding property xc_loc, value "U3", to port bit TX2_UTP_N
Adding property xc_loc, value "M1", to port bit CLK2_P
Adding property xc_loc, value "M2", to port bit CLK2_N
Adding property xc_loc, value "T4", to port bit RX3_DATA_P
Adding property xc_loc, value "U4", to port bit RX3_DATA_N
Adding property xc_loc, value "T2", to port bit RX3_SP_P
Adding property xc_loc, value "T1", to port bit RX3_SP_N
Adding property xc_loc, value "N3", to port bit TX3_DATA_P
Adding property xc_loc, value "N4", to port bit TX3_DATA_N
Adding property xc_loc, value "V1", to port bit TX3_UTP_P
Adding property xc_loc, value "V2", to port bit TX3_UTP_N
Adding property xc_loc, value "N1", to port bit CLK3_P
Adding property xc_loc, value "N2", to port bit CLK3_N
Adding property xc_loc, value "W1", to port bit RX4_DATA_P
Adding property xc_loc, value "W2", to port bit RX4_DATA_N
Adding property xc_loc, value "AA3", to port bit RX4_SP_P
Adding property xc_loc, value "Y4", to port bit RX4_SP_N
Adding property xc_loc, value "W3", to port bit TX4_DATA_P
Adding property xc_loc, value "W4", to port bit TX4_DATA_N
Adding property xc_loc, value "W5", to port bit TX4_UTP_P
Adding property xc_loc, value "Y5", to port bit TX4_UTP_N
Adding property xc_loc, value "V3", to port bit CLK4_P
Adding property xc_loc, value "V4", to port bit CLK4_N
Adding property xc_loc, value "L22", to port bit RX5_DATA_P
Adding property xc_loc, value "L21", to port bit RX5_DATA_N
Adding property xc_loc, value "N21", to port bit RX5_SP_P
Adding property xc_loc, value "N22", to port bit RX5_SP_N
Adding property xc_loc, value "M17", to port bit TX5_DATA_P
Adding property xc_loc, value "M18", to port bit TX5_DATA_N
Adding property xc_loc, value "M19", to port bit TX5_UTP_P
Adding property xc_loc, value "M20", to port bit TX5_UTP_N
Adding property xc_loc, value "L18", to port bit CLK5_P
Adding property xc_loc, value "L17", to port bit CLK5_N
Adding property xc_loc, value "U20", to port bit RX6_DATA_P
Adding property xc_loc, value "U21", to port bit RX6_DATA_N
Adding property xc_loc, value "W22", to port bit RX6_SP_P
Adding property xc_loc, value "Y22", to port bit RX6_SP_N
Adding property xc_loc, value "T21", to port bit TX6_DATA_P
Adding property xc_loc, value "T22", to port bit TX6_DATA_N
Adding property xc_loc, value "V22", to port bit TX6_UTP_P
Adding property xc_loc, value "V21", to port bit TX6_UTP_N
Adding property xc_loc, value "N19", to port bit CLK6_P
Adding property xc_loc, value "N20", to port bit CLK6_N
Adding property xc_loc, value "G18", to port bit RX7_DATA_P
Adding property xc_loc, value "G17", to port bit RX7_DATA_N
Adding property xc_loc, value "G22", to port bit RX7_SP_P
Adding property xc_loc, value "G21", to port bit RX7_SP_N
Adding property xc_loc, value "G19", to port bit TX7_DATA_P
Adding property xc_loc, value "F19", to port bit TX7_DATA_N
Adding property xc_loc, value "F21", to port bit CLK7_P
Adding property xc_loc, value "F20", to port bit CLK7_N
Adding property xc_loc, value "K20", to port bit RX8_DATA_P
Adding property xc_loc, value "K19", to port bit RX8_DATA_N
Adding property xc_loc, value "K21", to port bit RX8_SP_P
Adding property xc_loc, value "K22", to port bit RX8_SP_N
Adding property xc_loc, value "L20", to port bit TX8_UTP_P
Adding property xc_loc, value "L19", to port bit TX8_UTP_N
Adding property xc_loc, value "E18", to port bit RX9_DATA_P
Adding property xc_loc, value "F18", to port bit RX9_DATA_N
Adding property xc_loc, value "D19", to port bit RX9_SP_P
Adding property xc_loc, value "D20", to port bit RX9_SP_N
Adding property xc_loc, value "E20", to port bit TX9_DATA_P
Adding property xc_loc, value "E19", to port bit TX9_DATA_N
Adding property xc_loc, value "E21", to port bit TX9_UTP_P
Adding property xc_loc, value "E22", to port bit TX9_UTP_N
Adding property xc_loc, value "D21", to port bit CLK9_P
Adding property xc_loc, value "D22", to port bit CLK9_N
Adding property xc_loc, value "K4", to port bit RX10_DATA_P
Adding property xc_loc, value "K3", to port bit RX10_DATA_N
Adding property xc_loc, value "F4", to port bit RX10_SP_P
Adding property xc_loc, value "E3", to port bit RX10_SP_N
Adding property xc_loc, value "G2", to port bit TX10_DATA_P
Adding property xc_loc, value "G1", to port bit TX10_DATA_N
Adding property xc_loc, value "E2", to port bit TX10_UTP_P
Adding property xc_loc, value "E1", to port bit TX10_UTP_N
Adding property xc_loc, value "C1", to port bit CLK10_P
Adding property xc_loc, value "D1", to port bit CLK10_N
Adding property xc_loc, value "B12", to port bit SPARE2
Adding property xc_loc, value "C12", to port bit SPARE3
Reading Xilinx I/O pad type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/x_io_tbl.txt] 
Reading Xilinx Rocket I/O parameter type table from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/gttype.txt] 
@N: :  | Running in logic synthesis mode without enhanced optimization 

Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS10(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS9(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS6(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS5(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS4(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS3(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS2(LVDS_DRIVERS_RECEIVERS)
Automatic dissolve at startup in view:work.hdmi_module_top_level(a0) of LVDS1(LVDS_DRIVERS_RECEIVERS)

Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Autoconstrain Mode is ON 
@N: :  | Only System clock will be Autoconstrained 
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)



#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.hdmi_module_top_level(a0):
No nets needed buffering.

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

@N:FX164 :  | The option to pack flops in the IOB has not been specified  
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Writing Analyst data base /home/warren/calicedaq/LDA/firmware/syn/hdmi/rev_1/lvds_drivers_receivers.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 63MB peak: 67MB)

Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file [/unix/local/synopsys/synplicity/fpga_c200906/lib/xilinx/netattr.txt] 
C-2009.06
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 67MB)

Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 67MB)

@N:MF276 :  | Gated clock conversion enabled, but no gated clocks found in design  
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 67MB)

Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 67MB)

@N:MF333 :  | Generated clock conversion enabled, but no generated clocks found in design  
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 67MB)



##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jan 13 14:26:42 2010
#


Top view:               hdmi_module_top_level
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    /home/warren/calicedaq/LDA/firmware/source/hdmi/hdmi_module_conv.sdc
                       
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for hdmi_module_top_level 

Mapping to part: xc3s400fg456-4
Cell usage:
GND             9 uses
PULLUP          1 use

I/O ports: 162
I/O primitives: 57
IBUF           9 uses
IBUFDS         8 uses
OBUF           16 uses
OBUFDS         24 uses

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)
Total load per clock:

Mapping Summary:
Total  LUTs: 0 (0%)

Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 13 14:26:42 2010

###########################################################]