dif Project Status (01/12/2010 - 14:50:02)
Project File:	dif.ise	Implementation State:	Programming File Generated
Module Name:	diflink_ecaldif	Errors:	No Errors
Target Device:	xc3s1000-4fg320	Warnings:	384 Warnings
Product Version:	ISE 11.4	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	607	15,360	3%
Number used as Flip Flops	594
Number used as Latches	13
Number of 4 input LUTs	1,133	15,360	7%
Number of occupied Slices	740	7,680	9%
Number of Slices containing only related logic	740	740	100%
Number of Slices containing unrelated logic	0	740	0%
Total Number of 4 input LUTs	1,216	15,360	7%
Number used as logic	1,132
Number used as a route-thru	83
Number used as Shift registers	1
Number of bonded IOBs	44	221	19%
IOB Flip Flops	6
IOB Master Pads	4
IOB Slave Pads	4
Number of BUFGMUXs	5	8	62%
Average Fanout of Non-Clock Nets	3.93

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Jan 12 14:43:37 2010	0	372 Warnings	62 Infos
Translation Report	Current	Tue Jan 12 14:49:21 2010	0	0	0
Map Report	Current	Tue Jan 12 14:49:29 2010	0	6 Warnings	2 Infos
Place and Route Report	Current	Tue Jan 12 14:49:43 2010	0	3 Warnings	0
Power Report
Post-PAR Static Timing Report	Current	Tue Jan 12 14:49:46 2010	0	0	2 Infos
Bitgen Report	Current	Tue Jan 12 14:50:01 2010	0	3 Warnings	1 Info

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 01/12/2010 - 14:55:32