startup Project Status
Project File: startup.ise Implementation State: Programming File Generated
Module Name: startup_fpga
  • Errors:
No Errors
Target Device: xc3s400a-4ft256
  • Warnings:
230 Warnings (0 new)
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 249 7,168 3%  
Number of 4 input LUTs 195 7,168 2%  
Number of occupied Slices 224 3,584 6%  
    Number of Slices containing only related logic 224 224 100%  
    Number of Slices containing unrelated logic 0 224 0%  
Total Number of 4 input LUTs 195 7,168 2%  
    Number used as logic 189      
    Number used as Shift registers 6      
Number of bonded IOBs 93 195 47%  
Number of BUFGMUXs 7 24 29%  
Number of DCMs 4 4 100%  
Average Fanout of Non-Clock Nets 2.81      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Feb 17 16:44:44 2010093 Warnings (0 new)10 Infos (0 new)
Translation ReportCurrentWed Feb 17 16:49:39 2010018 Warnings (0 new)0
Map ReportCurrentWed Feb 17 16:49:45 2010047 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentWed Feb 17 16:50:03 2010040 Warnings (0 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Feb 17 16:50:06 2010003 Infos (0 new)
Bitgen ReportCurrentWed Feb 17 16:50:11 2010032 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/02/2010 - 12:25:34