--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: P.20131013
--  \   \         Application: netgen
--  /   /         Filename: cg_eth_1gmac_gmii_axi.vhd
-- /___/   /\     Timestamp: Thu Mar 26 11:59:36 2015
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -w -sim -ofmt vhdl /tmp/_cg/cg_eth_1gmac_gmii_axi.ngc /tmp/_cg/cg_eth_1gmac_gmii_axi.vhd 
-- Device	: 6slx45csg324-2
-- Input file	: /tmp/_cg/cg_eth_1gmac_gmii_axi.ngc
-- Output file	: /tmp/_cg/cg_eth_1gmac_gmii_axi.vhd
-- # of Entities	: 1
-- Design Name	: cg_eth_1gmac_gmii_axi
-- Xilinx	: /unix/local/xilinx/14.7/ISE_DS/ISE/
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------


-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cg_eth_1gmac_gmii_axi is
  port (
    glbl_rstn : in STD_LOGIC := 'X';
    rx_axi_rstn : in STD_LOGIC := 'X';
    tx_axi_rstn : in STD_LOGIC := 'X';
    rx_axi_clk : in STD_LOGIC := 'X';
    tx_axi_clk : in STD_LOGIC := 'X';
    tx_axis_mac_tvalid : in STD_LOGIC := 'X';
    tx_axis_mac_tlast : in STD_LOGIC := 'X';
    pause_req : in STD_LOGIC := 'X';
    gmii_col : in STD_LOGIC := 'X';
    gmii_crs : in STD_LOGIC := 'X';
    gmii_rx_dv : in STD_LOGIC := 'X';
    gmii_rx_er : in STD_LOGIC := 'X';
    rx_reset_out : out STD_LOGIC;
    rx_axis_mac_tvalid : out STD_LOGIC;
    rx_axis_mac_tlast : out STD_LOGIC;
    rx_axis_mac_tuser : out STD_LOGIC;
    rx_statistics_valid : out STD_LOGIC;
    tx_reset_out : out STD_LOGIC;
    tx_axis_mac_tready : out STD_LOGIC;
    tx_retransmit : out STD_LOGIC;
    tx_collision : out STD_LOGIC;
    tx_statistics_valid : out STD_LOGIC;
    speed_is_100 : out STD_LOGIC;
    speed_is_10_100 : out STD_LOGIC;
    gmii_tx_en : out STD_LOGIC;
    gmii_tx_er : out STD_LOGIC;
    tx_axis_mac_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
    tx_axis_mac_tuser : in STD_LOGIC_VECTOR ( 0 downto 0 );
    tx_ifg_delay : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pause_val : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gmii_rxd : in STD_LOGIC_VECTOR ( 7 downto 0 );
    rx_mac_config_vector : in STD_LOGIC_VECTOR ( 79 downto 0 );
    tx_mac_config_vector : in STD_LOGIC_VECTOR ( 79 downto 0 );
    rx_axis_mac_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rx_statistics_vector : out STD_LOGIC_VECTOR ( 27 downto 0 );
    tx_statistics_vector : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gmii_txd : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end cg_eth_1gmac_gmii_axi;

architecture STRUCTURE of cg_eth_1gmac_gmii_axi is
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_in : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_in : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXSTATSADDRESSMATCH_DEL_207 : STD_LOGIC;
  signal NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_235 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_28_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_27_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_26_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_25_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_23_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_22_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_21_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_20_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_19_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_18_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_17_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_16_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_15_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_14_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_13_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_12_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_11_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_0_Q : STD_LOGIC;
  signal NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_273 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_274 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tuser_275 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VALID_276 : STD_LOGIC;
  signal NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4 : STD_LOGIC;
  signal NlwRenamedSig_OI_tx_axis_mac_tready : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_RETRANSMIT_OUT_279 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_COLLISION_OUT_280 : STD_LOGIC;
  signal NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VALID : STD_LOGIC;
  signal NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY : STD_LOGIC;
  signal NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY : STD_LOGIC;
  signal N0 : STD_LOGIC;
  signal NlwRenamedSig_OI_N1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R2_286 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R1_287 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3_288 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3_PWR_21_o_MUX_14_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R2_290 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R1_291 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3_292 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3_PWR_21_o_MUX_14_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_296 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_297 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_298 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_299 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_300 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filter_match_0_301 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1_302 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1_303 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_VLAN_ENABLE_OUT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun_335 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_336 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_345 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_346 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_349 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_371 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_RETRANSMIT_372 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_386 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_In_389 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_In : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_In_391 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_77_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_397 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_EARLY : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_34_o_MUX_273_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_400 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CAPTURE_401 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN_402 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE_403 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_404 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE_405 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_406 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE_407 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_418 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_LENGTH_419 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14922 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14301 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_4_Q_456 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_3_Q_457 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_3_Q_458 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_2_Q_459 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_2_Q_460 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_1_Q_461 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_1_Q_462 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_0_Q_463 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_0_Q_464 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_27_OUT_7_0_cy_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT18 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT17 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT16 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT15 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT14 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT13 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT9 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_BACK_OFF_TIME_REACHED_AND_221_o_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_9_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_8_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_7_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_6_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_5_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_4_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_3_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_2_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_1_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_0_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT9 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT14 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT13 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT9 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_INT_HALF_DUPLEX_AND_398_o_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable21 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_7_1_657 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_6_1_658 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_4_1_659 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_2_1_660 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_0_1_661 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT_2_1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1809_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1764_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1756_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1736_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1728_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1704_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_DONE : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_LATE_COL_SAVED_AND_285_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_EXCESSIVE_COLLISIONS_AND_156_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_CONTROL : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_WFBOT_OR_95_o_678 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_PRE_REG : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_PWR_37_o_MUX_634_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_COF_SEEN_AND_273_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_SCSH_AND_259_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_COF_AND_256_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_PRE_AND_251_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_0_PAD_OR_266_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_TX_FAIL_REG2_OR_181_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0_INT_TX_DA_AND_315_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0_INT_TX_DA_AND_331_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0_INT_TX_DA_AND_299_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0_INT_TX_DA_AND_307_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0_INT_TX_DA_AND_323_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1448 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1454 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1440_738 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1415 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1434_740 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1420_741 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_780 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_GND_37_o_MUX_425_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_11_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_12_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_13_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_14_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_834 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_898 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_899 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_900 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_901 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_902 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_903 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_919 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_920 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_924 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_926 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_927 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_928 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_930 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_933 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_942 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_943 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_ER_IN_965 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN_966 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_CRS_967 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_969 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_999 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_1000 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1017 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_1018 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_1019 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_1020 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_1021 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_1022 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_1023 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1024 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1025 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1045 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1050 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_DELAY_1051 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG2_1052 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG1_1053 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_1054 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_ENABLE_1056 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1057 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1059 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1060 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_bdd6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_bdd6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_bdd2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_2_Q_1082 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_3_Q_1083 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_4_Q_1084 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_6_Q_1086 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_7_Q_1087 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_11_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_Q_1092 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_13_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_Q_1094 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_15_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_16_Q_1096 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_17_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_18_Q_1098 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_19_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_20_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_21_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_22_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_24_Q_1104 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_25_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_26_Q_1106 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_27_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_28_Q_1108 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_29_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_30_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_31_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER9 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_0_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_In : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_In : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_14_1202 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_13_1203 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_2_1206 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_3_1207 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_4_1208 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_5_1209 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_6_1210 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_7_1211 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_8_1212 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_9_1213 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_10_1214 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_11_1215 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_12_1216 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_31_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_30_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_29_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_28_Q_1244 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_27_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_26_Q_1246 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_25_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_24_Q_1248 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_22_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_21_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_20_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_19_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_18_Q_1254 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_17_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_16_Q_1256 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_15_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_Q_1258 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_13_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_Q_1260 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_11_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_7_Q_1265 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_6_Q_1266 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_4_Q_1268 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_3_Q_1269 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_2_Q_1270 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_bdd2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_bdd6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_bdd6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_FRAME_SUCCESS_MUX_1121_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_GND_44_o_MUX_1120_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_RX_DV_REG6_AND_454_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_52_o_RX_ERR_REG6_AND_452_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_11_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_12_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_13_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_14_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1300 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_1302 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_1303 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG_1304 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG_1305 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG_1306 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_ENABLE_HELD_1308 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD_1309 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD_1311 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD_1312 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1313 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1339 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1341 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG3_1344 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1361 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1362 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1363 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR_1364 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR_1365 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1366 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME_1375 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1376 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1377 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1379 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1380 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1381 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1418 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BROADCASTADDRESSMATCH_DELAY : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o_1438 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_463_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_333_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_480_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_474_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_483_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1450 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_Q_1452 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_Q_1453 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_Q_1454 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_Q_1455 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_Q_1456 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_Q_1457 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_Q_1458 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_Q_1459 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_Q_1460 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_0_Q_1461 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_lut_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER14 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER13 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER9 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_PREAMBLE_FIELD_AND_531_o_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_48_o_RXD_7_equal_9_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1_GND_48_o_MUX_1052_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_9_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_10_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_360_o_1536 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_345_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o_1539 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_505_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_56_o_RXD_7_equal_15_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_FIELD_COUNTER_1_AND_506_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_0_GND_48_o_MUX_972_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_1_GND_48_o_MUX_971_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_2_GND_48_o_MUX_970_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_3_GND_48_o_MUX_969_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_4_GND_48_o_MUX_968_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_5_GND_48_o_MUX_967_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_6_GND_48_o_MUX_966_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_7_GND_48_o_MUX_965_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_8_GND_48_o_MUX_964_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_9_GND_48_o_MUX_963_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_GND_48_o_MUX_962_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_DATA_WITH_FCS_MUX_1016_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_56_o_AND_540_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1578 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1581 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1582 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT_1583 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1584 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1585 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1586 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1587 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE_1588 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1589 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1590 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT81_1592 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_548_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_384_o_1608 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_396_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_364_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_49_o_FRAME_COUNTER_7_equal_1_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_8_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_1621 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1622 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1623 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1624 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1625 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_1626 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXTENSION_FIELD_REG_1627 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1630 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1632 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9_1634 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_In_1635 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_In : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_In_1637 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_two_byte_tx_OR_38_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_3_tx_state_3_OR_37_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tlast_tx_mac_tvalid_OR_21_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_PWR_24_o_equal_77_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_75_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_74_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_73_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_tx_enable_reg_AND_28_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_30_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_1650 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_1652 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd5_1657 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_1658 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_1659 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_1660 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_1662 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_1665 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_1666 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_1668 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1690 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_1691 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1696 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_in : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_CONTROL_COMPLETE : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_REQ_LOCAL : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_COMB : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_COMB : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00811 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1777 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1778 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_val : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In_1794 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_Mux_26_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156_1807 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0150_1808 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_38_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_COMB : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1818 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG_1819 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_1837 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_86_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_1905 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3_1906 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_1907 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o12_1908 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT15 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT14 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT13 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT9 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG_1971 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0300_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match_address_match_MUX_1221_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe_2_GND_52_o_MUX_1193_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int_specialpauseaddressmatch_int_MUX_1215_o : STD_LOGIC;

  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int_pauseaddressmatch_int_MUX_1203_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int_broadcastaddressmatch_int_MUX_1185_o : STD_LOGIC;

  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_0_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_1_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_2_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_3_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_4_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_5_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_6_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_rx_data_7_MUX_1177_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_2029 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_2030 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_2031 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_2032 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match_2033 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int_2034 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int_2035 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int_2039 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg2_2048 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg1_2049 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_reg_2050 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_2051 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_2056 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_In : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_next_rx_state_1_OR_9_o_0 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state_1_rx_enable_AND_7_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_NORMAL_COUNT_xor_3_11 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0190_inv : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_GND_43_o_MUX_807_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2_2125 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_2131 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132 : STD_LOGIC;
  signal N2 : STD_LOGIC;
  signal N4 : STD_LOGIC;
  signal N6 : STD_LOGIC;
  signal N8 : STD_LOGIC;
  signal N12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14481_2146 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14482_2147 : STD_LOGIC;
  signal N14 : STD_LOGIC;
  signal N16 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER1_2151 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv1_2152 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv2_2153 : STD_LOGIC;
  signal N20 : STD_LOGIC;
  signal N22 : STD_LOGIC;
  signal N24 : STD_LOGIC;
  signal N26 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14501_2158 : STD_LOGIC;
  signal N30 : STD_LOGIC;
  signal N34 : STD_LOGIC;
  signal N36 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1795_inv1_2162 : STD_LOGIC;
  signal N38 : STD_LOGIC;
  signal N42 : STD_LOGIC;
  signal N44 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o1_2166 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14541_2167 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14542_2168 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14543_2169 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_2170 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_2171 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o1_2173 : STD_LOGIC;
  signal N46 : STD_LOGIC;
  signal N48 : STD_LOGIC;
  signal N50 : STD_LOGIC;
  signal N52 : STD_LOGIC;
  signal N54 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15081_2179 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15082_2180 : STD_LOGIC;
  signal N56 : STD_LOGIC;
  signal N58 : STD_LOGIC;
  signal N60 : STD_LOGIC;
  signal N62 : STD_LOGIC;
  signal N64 : STD_LOGIC;
  signal N66 : STD_LOGIC;
  signal N68 : STD_LOGIC;
  signal N70 : STD_LOGIC;
  signal N72 : STD_LOGIC;
  signal N74 : STD_LOGIC;
  signal N76 : STD_LOGIC;
  signal N78 : STD_LOGIC;
  signal N80 : STD_LOGIC;
  signal N82 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT51_2196 : STD_LOGIC;
  signal N84 : STD_LOGIC;
  signal N86 : STD_LOGIC;
  signal N88 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT28 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT281_2201 : STD_LOGIC;
  signal N92 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_1_2204 : STD_LOGIC;
  signal N94 : STD_LOGIC;
  signal N96 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT28 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT281_2208 : STD_LOGIC;
  signal N98 : STD_LOGIC;
  signal N100 : STD_LOGIC;
  signal N102 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT51_2213 : STD_LOGIC;
  signal N106 : STD_LOGIC;
  signal N108 : STD_LOGIC;
  signal N110 : STD_LOGIC;
  signal N112 : STD_LOGIC;
  signal N114 : STD_LOGIC;
  signal N116 : STD_LOGIC;
  signal N118 : STD_LOGIC;
  signal N120 : STD_LOGIC;
  signal N122 : STD_LOGIC;
  signal N124 : STD_LOGIC;
  signal N126 : STD_LOGIC;
  signal N128 : STD_LOGIC;
  signal N130 : STD_LOGIC;
  signal N132 : STD_LOGIC;
  signal N134 : STD_LOGIC;
  signal N136 : STD_LOGIC;
  signal N140 : STD_LOGIC;
  signal N146 : STD_LOGIC;
  signal N148 : STD_LOGIC;
  signal N152 : STD_LOGIC;
  signal N154 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o11_2236 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o12_2237 : STD_LOGIC;
  signal N158 : STD_LOGIC;
  signal N160 : STD_LOGIC;
  signal N164 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02131_2241 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02132_2242 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02133_2243 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv11_2244 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv12_2245 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv13_2246 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv14_2247 : STD_LOGIC;
  signal N168 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o1_2249 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o2_2250 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT10 : STD_LOGIC;
  signal N172 : STD_LOGIC;
  signal N176 : STD_LOGIC;
  signal N178 : STD_LOGIC;
  signal N180 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o1_2256 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o2_2257 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o3_2258 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o4_2259 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o5_2260 : STD_LOGIC;
  signal N182 : STD_LOGIC;
  signal N184 : STD_LOGIC;
  signal N186 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_1_2265 : STD_LOGIC;
  signal N192 : STD_LOGIC;
  signal N194 : STD_LOGIC;
  signal N196 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1_2269 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In2_2270 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT10 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT101_2272 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT102_2273 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT103_2274 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT71_2276 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT14 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT141_2278 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT12 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT121_2280 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT31_2282 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT32_2283 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT51_2285 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT52_2286 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT53_2287 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT16 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT161_2289 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT162_2290 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT163_2291 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT19 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT191_2293 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT192_2294 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT193_2295 : STD_LOGIC;
  signal N200 : STD_LOGIC;
  signal N202 : STD_LOGIC;
  signal N204 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o11_2300 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_Q : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_1_2302 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT7 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT71_2304 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT6 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT61_2306 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT5 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT51_2308 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT4 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT41_2310 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT3 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT31_2312 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT2 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT21_2314 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT11_2316 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb81_2318 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o8 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o81_2320 : STD_LOGIC;
  signal N206 : STD_LOGIC;
  signal N208 : STD_LOGIC;
  signal N210 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_glue_set_2324 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_glue_rst_2325 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_glue_rst_2326 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_glue_set_2327 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set_2328 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set_2329 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set_2330 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set_2331 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set_2332 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set_2333 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set_2334 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set_2335 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set_2336 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set_2337 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set_2338 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set_2339 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set_2340 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set_2341 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_glue_set_2342 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_glue_set_2343 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_ce_2344 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_set_2345 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_glue_rst_2346 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_glue_rst_2347 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_glue_set_2348 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_glue_set_2349 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_glue_set_2350 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_glue_set_2351 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_glue_set_2352 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_glue_set_2353 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_glue_rst_2354 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_glue_set_2355 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_glue_set_2357 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_glue_set_2358 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_glue_set_2359 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_glue_set_2360 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_ce_2361 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_set_2362 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_glue_set_2363 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_glue_set_2364 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst_2365 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_glue_set_2366 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_glue_set_2367 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_glue_set_2368 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_glue_set_2369 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_glue_set_2370 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_glue_set_2371 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_glue_set_2372 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_glue_set_2373 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_glue_set_2374 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_glue_set_2375 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_glue_set_2376 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_glue_set_2377 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_glue_set_2378 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_glue_rst_2379 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_glue_set_2380 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_0_glue_set_2381 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set_2382 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_2383 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_2384 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_2385 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_glue_set_2386 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_glue_set_2387 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_glue_set_2388 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_glue_set_2389 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_glue_set_2390 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_glue_set_2391 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_glue_set_2392 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_glue_set_2393 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_glue_set_2394 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_glue_set : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun_glue_set : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set_2397 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_2398 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set_2399 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_0_glue_rst_2400 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_glue_rst_2401 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_1_glue_rst_2402 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set_2403 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set_2404 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set_2405 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_glue_set_2406 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_glue_set_2407 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_glue_set_2408 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_glue_set_2409 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_glue_set_2410 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_7_glue_set_2411 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_6_glue_set_2412 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_5_glue_set_2413 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_4_glue_set_2414 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_3_glue_set_2415 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_2_glue_set_2416 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_1_glue_set_2417 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_0_glue_set_2418 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_glue_set_2419 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_8_rt_2420 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_7_rt_2421 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_6_rt_2422 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_5_rt_2423 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_4_rt_2424 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_3_rt_2425 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_2_rt_2426 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_1_rt_2427 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_2428 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_2429 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_2430 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_2431 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_2432 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_2433 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_2434 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_2435 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_2436 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_2437 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_2438 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_2439 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_2440 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_rt_2441 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_rt_2442 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_rt_2443 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_rt_2444 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_rt_2445 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_rt_2446 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_rt_2447 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_rt_2448 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_rt_2449 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_9_rt_2450 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt_2451 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_10_rt_2452 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot_2453 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot_2457 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_rstpot_2458 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_rstpot_2459 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot_2460 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot_2461 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_2462 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot_2463 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot_2464 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_rstpot_2465 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_rstpot_2467 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot_2468 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_rstpot_2469 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_rstpot_2470 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_rstpot_2471 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_rstpot_2472 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_rstpot_2473 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_rstpot_2474 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_rstpot_2475 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_rstpot : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_rstpot : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot_2478 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_rstpot_2479 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_rstpot_2480 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_2481 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_rstpot1_2482 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1_2483 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_rstpot1_2484 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_rstpot1_2485 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_rstpot1_2486 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_rstpot1_2487 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_rstpot1_2488 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot1_2489 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot1_2490 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot1_2491 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_rstpot1_2492 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1_2493 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1_2494 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1_2495 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_2496 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_2497 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1_2498 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_2499 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_2500 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1_2501 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_2502 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1_2503 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1_2504 : STD_LOGIC;
  signal N212 : STD_LOGIC;
  signal N213 : STD_LOGIC;
  signal N218 : STD_LOGIC;
  signal N220 : STD_LOGIC;
  signal N222 : STD_LOGIC;
  signal N224 : STD_LOGIC;
  signal N228 : STD_LOGIC;
  signal N233 : STD_LOGIC;
  signal N234 : STD_LOGIC;
  signal N236 : STD_LOGIC;
  signal N237 : STD_LOGIC;
  signal N239 : STD_LOGIC;
  signal N241 : STD_LOGIC;
  signal N243 : STD_LOGIC;
  signal N245 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_rstpot_2520 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_0_rstpot_2521 : STD_LOGIC;
  signal N249 : STD_LOGIC;
  signal N251 : STD_LOGIC;
  signal N253 : STD_LOGIC;
  signal N257 : STD_LOGIC;
  signal N259 : STD_LOGIC;
  signal N261 : STD_LOGIC;
  signal N262 : STD_LOGIC;
  signal N264 : STD_LOGIC;
  signal N265 : STD_LOGIC;
  signal N266 : STD_LOGIC;
  signal N272 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_4_rstpot_2533 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_3_rstpot_2534 : STD_LOGIC;
  signal N274 : STD_LOGIC;
  signal N276 : STD_LOGIC;
  signal N278 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_1_rstpot_2538 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_0_rstpot_2539 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut_2540 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_l1 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut1_2542 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_2_rstpot_2543 : STD_LOGIC;
  signal N295 : STD_LOGIC;
  signal N303 : STD_LOGIC;
  signal N305 : STD_LOGIC;
  signal N307 : STD_LOGIC;
  signal N309 : STD_LOGIC;
  signal N312 : STD_LOGIC;
  signal N316 : STD_LOGIC;
  signal N320 : STD_LOGIC;
  signal N328 : STD_LOGIC;
  signal N332 : STD_LOGIC;
  signal N333 : STD_LOGIC;
  signal N334 : STD_LOGIC;
  signal N336 : STD_LOGIC;
  signal N338 : STD_LOGIC;
  signal N340 : STD_LOGIC;
  signal N344 : STD_LOGIC;
  signal N346 : STD_LOGIC;
  signal N348 : STD_LOGIC;
  signal N350 : STD_LOGIC;
  signal N352 : STD_LOGIC;
  signal N354 : STD_LOGIC;
  signal N356 : STD_LOGIC;
  signal N358 : STD_LOGIC;
  signal N360 : STD_LOGIC;
  signal N362 : STD_LOGIC;
  signal N364 : STD_LOGIC;
  signal N366 : STD_LOGIC;
  signal N368 : STD_LOGIC;
  signal N370 : STD_LOGIC;
  signal N372 : STD_LOGIC;
  signal N374 : STD_LOGIC;
  signal N376 : STD_LOGIC;
  signal N378 : STD_LOGIC;
  signal N380 : STD_LOGIC;
  signal N382 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_1_2579 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1_2580 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_0_dpot_2582 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_1_dpot_2583 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_2_dpot_2584 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_3_dpot_2585 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_4_dpot_2586 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_5_dpot_2587 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_6_dpot_2588 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_7_dpot_2589 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_8_dpot_2590 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_9_dpot_2591 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_10_dpot_2592 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_11_dpot_2593 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_dpot_2594 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1_2595 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1_2596 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1_2597 : STD_LOGIC;
  signal N384 : STD_LOGIC;
  signal N385 : STD_LOGIC;
  signal N386 : STD_LOGIC;
  signal N387 : STD_LOGIC;
  signal N388 : STD_LOGIC;
  signal N389 : STD_LOGIC;
  signal N390 : STD_LOGIC;
  signal N391 : STD_LOGIC;
  signal N392 : STD_LOGIC;
  signal N393 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_2608 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131_2609 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mshreg_STATISTICS_VECTOR_22_2610 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift1_2611 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift2_2612 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift3_2613 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift4_2614 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift5_2615 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift6_2616 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift7_2617 : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311_2618 : STD_LOGIC;
  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_delay_rx_data_valid_Q15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_7_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_6_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_5_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_4_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_3_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_2_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_1_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_0_header_field_dist_ram_SPO_UNCONNECTED : STD_LOGIC;

  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_Q15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mshreg_STATISTICS_VECTOR_22_Q15_UNCONNECTED : STD_LOGIC;
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2 : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0 : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_REG : STD_LOGIC_VECTOR ( 9 downto 9 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_in <= rx_mac_config_vector(11);
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_in <= rx_mac_config_vector(6);
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in <= rx_mac_config_vector(5);
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in <= tx_mac_config_vector(6);
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in <= tx_mac_config_vector(5);
  rx_axis_mac_tdata(7) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(7);
  rx_axis_mac_tdata(6) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(6);
  rx_axis_mac_tdata(5) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(5);
  rx_axis_mac_tdata(4) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(4);
  rx_axis_mac_tdata(3) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(3);
  rx_axis_mac_tdata(2) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(2);
  rx_axis_mac_tdata(1) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(1);
  rx_axis_mac_tdata(0) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(0);
  rx_statistics_vector(27) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXSTATSADDRESSMATCH_DEL_207;
  rx_statistics_vector(26) <= NlwRenamedSig_OI_N1;
  rx_statistics_vector(25) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(23);
  rx_statistics_vector(22) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(22);
  rx_statistics_vector(21) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(21);
  rx_statistics_vector(20) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(20);
  rx_statistics_vector(19) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(19);
  rx_statistics_vector(18) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(18);
  rx_statistics_vector(17) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(17);
  rx_statistics_vector(16) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(16);
  rx_statistics_vector(15) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(15);
  rx_statistics_vector(14) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(14);
  rx_statistics_vector(13) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(13);
  rx_statistics_vector(12) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(12);
  rx_statistics_vector(11) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(11);
  rx_statistics_vector(10) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(10);
  rx_statistics_vector(9) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(9);
  rx_statistics_vector(8) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(8);
  rx_statistics_vector(7) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(7);
  rx_statistics_vector(6) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(6);
  rx_statistics_vector(5) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(5);
  rx_statistics_vector(4) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(4);
  rx_statistics_vector(3) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(3);
  rx_statistics_vector(2) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(2);
  rx_statistics_vector(1) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(1);
  rx_statistics_vector(0) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(0);
  tx_statistics_vector(31) <= NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0;
  tx_statistics_vector(30) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_235;
  tx_statistics_vector(29) <= NlwRenamedSig_OI_N1;
  tx_statistics_vector(28) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_28_Q;
  tx_statistics_vector(27) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_27_Q;
  tx_statistics_vector(26) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_26_Q;
  tx_statistics_vector(25) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_25_Q;
  tx_statistics_vector(24) <= NlwRenamedSig_OI_N1;
  tx_statistics_vector(23) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_23_Q;
  tx_statistics_vector(22) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_22_Q;
  tx_statistics_vector(21) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_21_Q;
  tx_statistics_vector(20) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_20_Q;
  tx_statistics_vector(19) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_19_Q;
  tx_statistics_vector(18) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_18_Q;
  tx_statistics_vector(17) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_17_Q;
  tx_statistics_vector(16) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_16_Q;
  tx_statistics_vector(15) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_15_Q;
  tx_statistics_vector(14) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_14_Q;
  tx_statistics_vector(13) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_13_Q;
  tx_statistics_vector(12) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_12_Q;
  tx_statistics_vector(11) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_11_Q;
  tx_statistics_vector(10) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_10_Q;
  tx_statistics_vector(9) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_9_Q;
  tx_statistics_vector(8) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_8_Q;
  tx_statistics_vector(7) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_7_Q;
  tx_statistics_vector(6) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_6_Q;
  tx_statistics_vector(5) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_5_Q;
  tx_statistics_vector(4) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_4_Q;
  tx_statistics_vector(3) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_3_Q;
  tx_statistics_vector(2) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_Q;
  tx_statistics_vector(1) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_1_Q;
  tx_statistics_vector(0) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_0_Q;
  gmii_txd(7) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(7);
  gmii_txd(6) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(6);
  gmii_txd(5) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(5);
  gmii_txd(4) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(4);
  gmii_txd(3) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(3);
  gmii_txd(2) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(2);
  gmii_txd(1) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(1);
  gmii_txd(0) <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(0);
  rx_reset_out <= NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4;
  rx_axis_mac_tvalid <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_273;
  rx_axis_mac_tlast <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_274;
  rx_axis_mac_tuser <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tuser_275;
  rx_statistics_valid <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VALID_276;
  tx_reset_out <= NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4;
  tx_axis_mac_tready <= NlwRenamedSig_OI_tx_axis_mac_tready;
  tx_retransmit <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_RETRANSMIT_OUT_279;
  tx_collision <= U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_COLLISION_OUT_280;
  tx_statistics_valid <= NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VALID;
  speed_is_100 <= NlwRenamedSig_OI_N1;
  speed_is_10_100 <= NlwRenamedSig_OI_N1;
  gmii_tx_en <= NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY;
  gmii_tx_er <= NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY;
  XST_VCC : VCC
    port map (
      P => N0
    );
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_N1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R1 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => rx_axi_clk,
      D => NlwRenamedSig_OI_N1,
      PRE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R1_287
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R2 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R1_287,
      PRE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R2_286
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R1 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => tx_axi_clk,
      D => NlwRenamedSig_OI_N1,
      PRE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R1_291
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R2 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R1_291,
      PRE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R2_290
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXSTATSADDRESSMATCH_DEL : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_296,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXSTATSADDRESSMATCH_DEL_207
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_BYTECNTSRL : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_N1,
      A1 => N0,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_EARLY
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT_3 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT3,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT_2 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT2,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT1,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_In_389,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_386
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_In_391,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_In,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_34_o_MUX_273_o,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_397
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => tx_mac_config_vector(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN_402
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_VLAN_ENABLE_OUT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE_403
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => tx_mac_config_vector(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_404
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => tx_mac_config_vector(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE_405
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_406
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_77_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE_407
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_9_rt_2450,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_9_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_8_rt_2420,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_8_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(7),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_8_rt_2420,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_7_rt_2421,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_7_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(6),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_7_rt_2421,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_6_rt_2422,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_6_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(5),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_6_rt_2422,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_5_rt_2423,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_5_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(4),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_5_rt_2423,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_4_rt_2424,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_4_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(3),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_4_rt_2424,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_3_rt_2425,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_3_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(2),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_3_rt_2425,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_2_rt_2426,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_2_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(1),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_2_rt_2426,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_1_rt_2427,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_1_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(0),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_1_rt_2427,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_N1,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_0_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_N1,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(13),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt_2451,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_13_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(12),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_2428,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(12),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_2428,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_12_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(11),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_2429,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(11),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_2429,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_11_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(10),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_2430,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(10),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_2430,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_2431,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(9),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_2431,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_2432,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(8),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_2432,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_2433,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(7),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_2433,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_2434,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(6),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_2434,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_2435,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(5),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_2435,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_2436,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(4),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_2436,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_2437,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(3),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_2437,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_2438,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(2),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_2438,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_2439,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(1),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_2439,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_2440,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(0),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_2440,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_N1,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_N1,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_3_Q_457,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_4_Q_456,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(12),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(13),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_4_Q_456
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_2_Q_459,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_3_Q_458,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_3_Q_457
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(10),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_3_Q_458
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_1_Q_461,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_2_Q_460,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_2_Q_459
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_2_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_2_Q_460
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_0_Q_463,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_1_Q_462,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_1_Q_461
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_1_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_927,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_928,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_1_Q_462
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_0_Q_464,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_cy_0_Q_463
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_0_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_926,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcompar_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_lut_0_Q_464
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(0),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_17 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT17,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_16 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT16,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT18,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(18)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT15,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT14,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT13,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT12,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT10,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT9,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT11,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_8 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT8,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_7 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT7,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_6 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT6,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_5 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT5,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_3 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT3,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_2 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT2,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_4 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT4,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT1,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_9_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_8_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_6_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_5_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_7_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_4_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_3_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_2_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_1_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT10,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result_0_1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT9,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT8,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT7,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT6,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT4,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT3,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT5,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT2,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT1,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(14),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(12),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(11),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(13),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(10),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(9),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(8),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(7),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(6),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(5),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(4),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(3),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(1),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_14 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT14,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT1,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT13,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT12,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_11 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT11,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT10,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_8 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT8,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_7 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT7,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_9 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT9,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_6 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT6,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_5 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT5,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT4,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_3 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT3,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT_2 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT2,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT1,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT_2 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT2,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT1,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT_5 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT5,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT_4 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT4,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT_3 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT3,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT_2 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT2,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT1,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_18_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(17),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(18),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT18
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_17_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(16),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(17),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT17
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_17_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(16),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(17),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_16_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(15),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(16),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT16
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_16_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(15),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(16),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_15_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(14),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(15),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT15
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_15_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(14),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(15),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_14_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(13),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT14
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_14_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(13),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_13_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(12),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT13
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_13_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(12),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_12_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(11),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_12_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(11),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_11_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(10),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_11_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(10),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_10_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(9),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT9
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(8),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(7),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(6),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(5),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(4),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(3),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(2),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(1),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(0),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_xor_0_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_BACK_OFF_TIME_REACHED_AND_221_o_inv,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy_0_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_BACK_OFF_TIME_REACHED_AND_221_o_inv,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT9
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(8),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(7),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(6),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(5),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(4),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(3),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(2),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(1),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(0),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_xor_0_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o_inv,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy_0_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o_inv,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_14_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(13),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT14
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_13_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(12),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT13
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_13_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(12),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_12_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(11),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_12_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(11),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_11_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(10),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_11_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(10),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_10_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(9),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT9
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(8),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(7),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(6),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(5),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(4),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(3),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(2),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(1),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(0),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_xor_0_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_INT_HALF_DUPLEX_AND_398_o_inv,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy_0_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_INT_HALF_DUPLEX_AND_398_o_inv,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_1018
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_7_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_6_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_5_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_4_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_3_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_2_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_1_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_0_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_28 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_28_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_27 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_27_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_26 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_26_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_25 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_25_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_23 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_903,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_23_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_22 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_902,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_22_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_21 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_899,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_21_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_20 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_834,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_20_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_19 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_999,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_19_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_18 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(13),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_18_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_17 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(12),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_17_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_16 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(11),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_16_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(10),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_15_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_14_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_13_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_12_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_11_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_1000,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_920,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_919,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(7),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(6),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(5),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(4),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(3),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(2),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(1),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(0),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_7_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_6_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_5_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_4_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_3_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_2_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_1_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_0_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_14_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_13 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_13_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_12 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_12_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_11 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_11_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_10 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_10_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_9 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_9_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_8 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_8_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_7 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_7_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_6 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_6_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_5 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_5_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_4 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_4_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_3 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_3_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_2 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_1 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_1_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_0 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_0_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_7_1_657,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_6_1_658,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_5_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable21,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_4_1_659,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_3_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable21,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_2_1_660,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_1_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable21,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_0_1_661,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT(7),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT(6),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT(5),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG1_1053,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG2_1052
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT_2_1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(1),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(0),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_969
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1045,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1025
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG1_1053
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_LENGTH : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_LENGTH_419
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_7_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_6_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_5_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_4_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_3_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_2_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_1_Q,
      R => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_0_Q,
      S => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_GND_37_o_MUX_425_o,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_780
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS_3 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(3),
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS_2 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(2),
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS_1 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(1),
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS_0 : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(0),
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ATTEMPTS(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRC_MODE_407,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_ER_IN : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_ER_IN_965
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN_966
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VALID : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VALID
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_CRS : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_397,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_CRS_967
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_VLAN_999
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_CONTROL,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_CONTROL_1000
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0_INT_TX_DA_AND_323_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_1020
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0_INT_TX_DA_AND_315_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_1021
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0_INT_TX_DA_AND_331_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_1019
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0_INT_TX_DA_AND_307_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_1022
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_4_Q,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0_INT_TX_DA_AND_299_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_1023
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_RETRANSMIT : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_LATE_COL_SAVED_AND_285_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_RETRANSMIT_372
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_COF_SEEN_AND_273_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1024
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_0_PAD_OR_266_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_SCSH_AND_259_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1045
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_COF_AND_256_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_PRE_AND_251_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_418
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_PRE_REG,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_DONE,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1050
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_DELAY : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_TX_FAIL_REG2_OR_181_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_DELAY_1051
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_ENABLE : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_mac_config_vector(14),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_ENABLE_1056
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_IFG_DEL_EN_402,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1057
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_VLAN_ENABLE_403,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1059
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_JUMBO_ENABLE_405,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1060
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      D => tx_ifg_delay(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_31 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_31_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_30 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_30_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_29 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_29_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_28 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_28_Q_1108,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_27 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_27_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_26 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_26_Q_1106,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_25 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_25_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_24 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_24_Q_1104,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(23)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_22 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_22_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(22)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_21 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_21_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(21)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_20 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_20_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(20)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_19 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_19_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(19)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_18 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_18_Q_1098,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(18)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_17 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_17_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_16 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_16_Q_1096,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_15_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_Q_1094,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_13_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_Q_1092,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_11_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_10_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_9_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_8_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_7_Q_1087,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_6_Q_1086,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_5_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_4_Q_1084,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_3_Q_1083,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_2_Q_1082,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_1_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_0_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_In,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_In,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_dpot_2594,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_11 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_11_dpot_2593,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_10 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_10_dpot_2592,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_9 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_9_dpot_2591,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_8 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_8_dpot_2590,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_7 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_7_dpot_2589,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_6 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_6_dpot_2588,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_5 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_5_dpot_2587,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_4 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_4_dpot_2586,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_3 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_3_dpot_2585,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_2 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_2_dpot_2584,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_1 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_1_dpot_2583,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_0 : FDE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_0_dpot_2582,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_12_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(11),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_11_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(10),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_11_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(10),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_10_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(9),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER9
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(8),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(7),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(6),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(5),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(4),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(3),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(2),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(1),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(0),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_xor_0_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_0_inv,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy_0_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_0_inv,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_14_1202,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_12 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_11_1215,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_12_1216
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_11 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_10_1214,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_11_1215
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_10 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_9_1213,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_10_1214
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_8_1212,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_9_1213
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_7_1211,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_8_1212
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_6_1210,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_7_1211
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_5_1209,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_6_1210
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_4_1208,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_5_1209
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_3_1207,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_4_1208
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_2_1206,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_3_1207
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_2_1206
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_13 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_12_1216,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_13_1203
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_14 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_13_1203,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_14_1202
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_0_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_1_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_2_Q_1270,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_3_Q_1269,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_4_Q_1268,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_5_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_6_Q_1266,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_7_Q_1265,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_8 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_8_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_9 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_9_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_10 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_10_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_11 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_11_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_12 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_Q_1260,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_13 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_13_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_14 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_Q_1258,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_15 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_15_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_16 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_16_Q_1256,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_17 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_17_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_18 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_18_Q_1254,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(18)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_19 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_19_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(19)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_20 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_20_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(20)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_21 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_21_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(21)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_22 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_22_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(22)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(23)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_24 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_24_Q_1248,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_25 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_25_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_26 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_26_Q_1246,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_27 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_27_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_28 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_28_Q_1244,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_29 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_29_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_30 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_30_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_31 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_31_Q,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RX_ERR : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1341,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RX_DV2 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_N1,
      A1 => N0,
      A2 => NlwRenamedSig_OI_N1,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG3_1344,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RX_DV1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => NlwRenamedSig_OI_N1,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_0_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_1_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_2_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_3_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_4_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_5_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_6_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_RXD_BUS_7_DELAY_RXD : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DELAY_BROADCASTADDRESSMATCH : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_299,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BROADCASTADDRESSMATCH_DELAY
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_FRAME_SUCCESS_MUX_1121_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_GND_44_o_MUX_1120_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_23 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1363,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(23)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_21 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1376,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(21)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_20 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR_1364,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(20)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_19 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_345,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(19)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_18 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(13),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(18)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_17 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(12),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_16 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(11),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_15 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(10),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_14 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(9),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_13 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(8),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_12 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_11 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_10 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME_1375,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BROADCASTADDRESSMATCH_DELAY,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR_1365,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1361,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1362,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VALID : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1366,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VALID_276
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG8(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1339
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG3_1344
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_14_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_13 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_13_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_12 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_12_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_11 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_11_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_10 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_10_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_9 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_9_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_8 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_8_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_7 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_7_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_6 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_6_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_5 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_5_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_4 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_4_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_3 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_3_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_2 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_1 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_1_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_0 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_0_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG_1304
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_RX_DV_REG6_AND_454_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG_1306
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_52_o_RX_ERR_REG6_AND_452_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG_1305
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_ENABLE_HELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      D => rx_mac_config_vector(14),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_ENABLE_HELD_1308
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      D => rx_mac_config_vector(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD_1309
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      D => rx_mac_config_vector(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      D => rx_mac_config_vector(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD_1311
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      D => rx_mac_config_vector(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1313
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => rx_mac_config_vector(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      D => rx_mac_config_vector(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD_1312
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1_302,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1341
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1_303,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_5_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_4 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_4_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_3 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_3_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_2 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_1 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_1_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_0 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_0_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_333_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_480_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_483_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_474_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o_1438,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_463_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1450
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_Q_1452,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_10_rt_2452,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_Q_1453,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_rt_2441,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_Q_1453,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_rt_2441,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_Q_1452
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_Q_1454,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_rt_2442,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_Q_1454,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_rt_2442,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_Q_1453
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_Q_1455,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_rt_2443,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_Q_1455,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_rt_2443,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_Q_1454
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_Q_1456,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_rt_2444,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_Q_1456,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_rt_2444,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_Q_1455
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_Q_1457,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_rt_2445,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_Q_1457,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_rt_2445,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_Q_1456
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_Q_1458,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_rt_2446,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_Q_1458,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_rt_2446,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_Q_1457
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_Q_1459,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_rt_2447,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_Q_1459,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_rt_2447,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_Q_1458
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_Q_1460,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_rt_2448,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_Q_1460,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_rt_2448,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_Q_1459
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_0_Q_1461,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_rt_2449,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_0_Q_1461,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_rt_2449,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_Q_1460
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_N1,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_lut_0_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_N1,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_lut_0_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_0_Q_1461
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_14 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER14,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_13 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER13,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_12 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER12,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_11 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER11,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_10 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER10,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_9 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER9,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_8 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER8,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER7,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER6,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER5,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER4,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER3,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_14_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(13),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER14
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_13_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(12),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER13
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_13_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(12),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_12_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(11),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_12_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(11),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_11_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(10),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_11_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(10),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_10_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(9),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER9
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(8),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(7),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(6),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(5),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(4),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(3),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(2),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(1),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(0),
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_xor_0_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_PREAMBLE_FIELD_AND_531_o_inv,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy_0_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_PREAMBLE_FIELD_AND_531_o_inv,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT_1583,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_346
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1376
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1584,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_INT_1583
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_10 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_10_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_9 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_9_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_8 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_8_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_7 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_7_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_6 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_6_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_5 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_5_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_4 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_4_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_3 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_3_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_2 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_2_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_1 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_1_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_0 : FDSE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_0_Q,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1578,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_345
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1_GND_48_o_MUX_1052_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_56_o_AND_540_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1581,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_FRAME_1375
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_GND_48_o_MUX_962_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_9 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_9_GND_48_o_MUX_963_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_8 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_8_GND_48_o_MUX_964_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_7_GND_48_o_MUX_965_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_6_GND_48_o_MUX_966_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_5_GND_48_o_MUX_967_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_4_GND_48_o_MUX_968_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_3_GND_48_o_MUX_969_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_2_GND_48_o_MUX_970_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_1_GND_48_o_MUX_971_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_0_GND_48_o_MUX_972_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_13 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_12 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_11 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_10 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_9 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_8 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_7 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_6 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_5 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_4 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_3 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_2 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_1 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH_0 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_STATISTICS_LENGTH(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_345_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1582
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_56_o_RXD_7_equal_15_o,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1585
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_DATA_WITH_FCS_MUX_1016_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1379
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_360_o_1536,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1586
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o_1539,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE_1588
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_505_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1589
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_48_o_RXD_7_equal_9_o,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1590
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_REG_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_REG(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_8 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_8_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_7 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_7_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_6 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_6_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_5 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_5_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_4 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_4_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_3 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_3_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_2 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_1 : FDE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_1_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1622,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_OUT_OF_BOUNDS_ERR_1364
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME : FDSE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_548_o,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1623
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_396_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ERR_1365
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_384_o_1608,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1624
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXTENSION_FIELD_REG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXTENSION_FIELD_REG_1627
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1630
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_364_o,
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_49_o_FRAME_COUNTER_7_equal_1_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1632
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_75_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_PWR_24_o_equal_77_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd5 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_74_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd5_1657
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_In_1635,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_1650
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_In,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_In_1637,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_30_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9_1634
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_tx_enable_reg_AND_28_o,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_73_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_1652
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_7_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_6_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_5_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_4_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_3_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_2_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_1_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_0_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => N0,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => NlwRenamedSig_OI_tx_axis_mac_tready,
      D => tx_axis_mac_tdata(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_in,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_in,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_in,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_COMB,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_COMB,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun_335,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_1691
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_COLLISION_OUT : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_371,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_COLLISION_OUT_280
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_RETRANSMIT_OUT : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_RETRANSMIT_372,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_RETRANSMIT_OUT_279
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_349,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(0),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(4),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(3),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(1),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(2),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_15 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(0),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_14 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(1),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_13 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(2),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_12 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(3),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_11 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(4),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_10 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(5),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_9 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(6),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_8 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(7),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(8),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(9),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(10),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(11),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(12),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(13),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(14),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(15),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_ACK_OUT : MUXF5
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN,
      I1 => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_COMB
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result(3),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result(2),
      R => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_val,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In_1794,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_7_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_6_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_5_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_4_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_3_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_2_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_1_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_0_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_Mux_26_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_COMB,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG : FDSE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_38_o,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG_1819
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_1837
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_336,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(15),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(14),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(13),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(12),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(11),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(10),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => pause_req,
      D => pause_val(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_47 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(79),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(47)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_46 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(78),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(46)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_45 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(77),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(45)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_44 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(76),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(44)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_43 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(75),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(43)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_42 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(74),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(42)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_41 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(73),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(41)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_40 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(72),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(40)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_39 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(71),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(39)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_38 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(70),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(38)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_37 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(69),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(37)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_36 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(68),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(36)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_35 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(67),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(35)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_34 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(66),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(34)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_33 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(65),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(33)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_32 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(64),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(32)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_31 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(63),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(31)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_30 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(62),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(30)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_29 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(61),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(29)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_28 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(60),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(28)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_27 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(59),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(27)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_26 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(58),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(26)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_25 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(57),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(25)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_24 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(56),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(24)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_23 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(55),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(23)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_22 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(54),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(22)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_21 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(53),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(21)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_20 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(52),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(20)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_19 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(51),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(19)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_18 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(50),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(18)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_17 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(49),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_16 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(48),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(47),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(46),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(45),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(44),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(43),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(42),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(41),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(40),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(39),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(38),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(37),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(36),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(35),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(34),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(33),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv,
      D => tx_mac_config_vector(32),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_1907,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3_1906
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_1905,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_1907
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_REQ_LOCAL,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_TO_TX : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_86_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_in
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_1905
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_15 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(15),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_14 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(14),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_13 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(13),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_12 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(12),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_11 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(11),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_10 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(10),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_9 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(9),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_8 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(8),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_7 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_6 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA5,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA4,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA3,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT15,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_14 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT14,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT13,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_12 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT12,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_11 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT11,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_10 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT10,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_9 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT9,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_8 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT8,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT7,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT6,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT5,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT4,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT3,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_15_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(14),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(15),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT15
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_14_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(13),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT14
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_14_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(13),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_13_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(12),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT13
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_13_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(12),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_12_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(11),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_12_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(11),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_11_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(10),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_11_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(10),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_10_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(9),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_10_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(9),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_9_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(8),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT9
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_9_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(8),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_8_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(7),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_8_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(7),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_7_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(6),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_7_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(6),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_6_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(5),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_6_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(5),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_5_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(4),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_5_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(4),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_4_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(3),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_4_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(3),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_3_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(2),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_3_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(2),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_2_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(1),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_2_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(1),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_1_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(0),
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_1_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(0),
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_xor_0_Q : XORCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o12_1908,
      LI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy_0_Q : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o12_1908,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_cy(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_in,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG_1971
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1 : FDR
    port map (
      C => rx_axi_clk,
      D => gmii_rx_er,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_ER_REG1_302
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1 : FDR
    port map (
      C => rx_axi_clk,
      D => gmii_rx_dv,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RX_DV_REG1_303
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => gmii_rxd(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_RX_GEN_RXD_REG1(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_7_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"06"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_6_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_5_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_4_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_3_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_2_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_1_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_address_0_LUT3_special_pause_inst : LUT3
    generic map(
      INIT => X"21"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_delay_rx_data_valid : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16,
      Q15 => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_delay_rx_data_valid_Q15_UNCONNECTED
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_7_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(7),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_7_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_6_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(6),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_6_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_5_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(5),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_5_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_4_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(4),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_4_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_3_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(3),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_3_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_2_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(2),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_2_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_1_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(1),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_1_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_0_header_field_dist_ram : RAM64X1D
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      A1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      A2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      A3 => NlwRenamedSig_OI_N1,
      A4 => NlwRenamedSig_OI_N1,
      A5 => NlwRenamedSig_OI_N1,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(0),
      DPRA0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      DPRA1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      DPRA2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      DPRA3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      DPRA4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      DPRA5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      WCLK => rx_axi_clk,
      WE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052,
      SPO => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_byte_wide_ram_0_header_field_dist_ram_SPO_UNCONNECTED,
      DPO => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0300_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0300_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0300_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter_5 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter5,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter_4 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter4,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter_3 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter3,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter_2 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter_1 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => NlwRenamedSig_OI_N1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_in,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync1,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int_2035,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_298
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int_pauseaddressmatch_int_MUX_1203_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int_2035
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_2051
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int_2034,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_297
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv,
      D =>
U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int_specialpauseaddressmatch_int_MUX_1215_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int_2034
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe_2_GND_52_o_MUX_1193_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_2052
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int_2039,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_299
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int_broadcastaddressmatch_int_MUX_1185_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int_2039
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_reg : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_reg_2050
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg2 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg1_2049,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg2_2048
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe_2 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe_1 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe_0 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filter_match_0 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_2032,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filter_match_0_301
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_7 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_7_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_6 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_6_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_5 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_5_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_4 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_4_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_3 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_3_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_2 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_2_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_1 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_1_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data_0 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_0_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_wr_data(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match : FDRE
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match_address_match_MUX_1221_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match_2033
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg1 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg1_2049
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_rx_data_7_MUX_1177_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_2056
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_In,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0_0 : FDRE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tdata(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tuser : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state_1_rx_enable_AND_7_o,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tuser_275
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_7 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(7),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_6 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(6),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_5 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(5),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_4 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(4),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_3 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(3),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_2 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(2),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_1 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(1),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg_0 : FDE
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_INT(0),
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_data_reg(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0190_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT2,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0190_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT1,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0190_inv,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2_2125
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1 : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_GND_43_o_MUX_807_o,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(7),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(6),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(5),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(4),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(3),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(2),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(1),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1_0 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(0),
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_2131
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_Mmux_R3_PWR_21_o_MUX_14_o11 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R2_286,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3_288,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3_PWR_21_o_MUX_14_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_Mmux_R3_PWR_21_o_MUX_14_o11 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R2_290,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3_292,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3_PWR_21_o_MUX_14_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH1 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => tx_axi_rstn,
      I1 => glbl_rstn,
      I2 => tx_mac_config_vector(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_RST_ASYNCH
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH1 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => rx_axi_rstn,
      I1 => glbl_rstn,
      I2 => rx_mac_config_vector(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_RX_RST_ASYNCH
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_Mmux_INT_CRS_GND_34_o_MUX_273_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => gmii_crs,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_GND_34_o_MUX_273_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT_xor_2_11 : LUT5
    generic map(
      INIT => X"A9FFA9A9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT_xor_3_11 : LUT6
    generic map(
      INIT => X"FE010000FE01FE01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_In1 : LUT6
    generic map(
      INIT => X"FF7FFF2A2A7F2A2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_397,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_386,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_418,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_In
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT_xor_1_11 : LUT4
    generic map(
      INIT => X"B00B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT_xor_0_11 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_Mcount_IFG_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_77_o1 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => tx_mac_config_vector(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CRC_MODE_INV_77_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_3_11 : LUT6
    generic map(
      INIT => X"FFFFFFFFAAA9FFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_2_11 : LUT5
    generic map(
      INIT => X"FFFFA9FF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_1_11 : LUT4
    generic map(
      INIT => X"FDDF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv1 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1682_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_0_11 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable121 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1756_inv1 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1756_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_12_OUT_7_0_xor_7_11 : LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_12_OUT_7_0_xor_6_11 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1736_inv1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1736_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_12_OUT_7_0_xor_5_11 : LUT3
    generic map(
      INIT => X"A9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_DONE1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_DONE
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_27_OUT_7_0_cy_5_11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_27_OUT_7_0_cy_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_ACK1 : LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_ACK_IN
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1728_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1728_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable211 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1050,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable21
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_DONE_1050,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_7_1_657
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_EXCESSIVE_COLLISIONS_AND_156_o1 : LUT5
    generic map(
      INIT => X"11001000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_EXCESSIVE_COLLISIONS_AND_156_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_REG_COL_GND_37_o_MUX_425_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => gmii_col,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_GND_37_o_MUX_425_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o12 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o111 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT_xor_2_11 : LUT4
    generic map(
      INIT => X"A9FF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1873_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv1 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1883_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1809_inv1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_371,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1809_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val1 : LUT4
    generic map(
      INIT => X"FF57"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN_966,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_ER_IN_965,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_val
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL1 : LUT4
    generic map(
      INIT => X"0E00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_933,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_780,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1704_inv1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1704_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT71 : LUT6
    generic map(
      INIT => X"0000CC3300000A0A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_27_OUT_7_0_cy_5_Q,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EN1 : LUT6
    generic map(
      INIT => X"00FF00FF00AF00AE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_PIPE_1025,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CR178124_FIX_1024,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1_2595,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_6_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_6_1_658
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_4_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_4_1_659
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_2_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_2_1_660
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_0_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_0_1_661
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst11 : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n143011 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_930,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14301
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT11 : LUT5
    generic map(
      INIT => X"FF33FF0A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_val
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux1311 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux1211 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(8),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux11111 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux1011 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux811 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux711 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux911 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux611 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux511 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux311 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(12),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux211 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(11),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux411 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(13),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux1111 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(10),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_mux141 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_2(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BYTE_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT21 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT31 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT41 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT51 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT61 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT71 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_3_7_GND_37_o_mux_95_OUT81 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_7_GND_37_o_mux_95_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_0_7_GND_37_o_mux_77_OUT21 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_0_7_GND_37_o_mux_77_OUT41 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_0_7_GND_37_o_mux_77_OUT61 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_7_GND_37_o_mux_77_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT16 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(16),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT21 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(26),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT31 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(27),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_11_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT41 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(28),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_12_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT51 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(29),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_13_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT61 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(30),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_14_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT71 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(17),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT81 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(18),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT91 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(19),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT101 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(20),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT111 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(21),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT121 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(22),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT131 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(23),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT141 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => tx_mac_config_vector(24),
      I2 => tx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT151 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => tx_mac_config_vector(25),
      I1 => tx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH_14_GND_37_o_mux_7_OUT_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_BACK_OFF_TIME_REACHED_AND_221_o_inv1 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_BACK_OFF_TIME_REACHED_AND_221_o_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"D7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_JAM_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_INT_HALF_DUPLEX_AND_398_o_inv1 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_INT_HALF_DUPLEX_AND_398_o_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"D7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_CRC_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"D7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_PRE_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable321 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1045,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable32
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1561_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o1 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_969,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1_2595,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_MIFG_OR_276_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1_2596,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_COF_SEEN_AND_273_o1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_COF_SEEN_AND_273_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_SCSH_AND_259_o1 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_SCSH_AND_259_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_COF_AND_256_o1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_COF_AND_256_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_PRE_AND_251_o1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_PRE_AND_251_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST1 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE0_MATCH_1023,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE1_MATCH_1022,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE2_MATCH_1021,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE3_MATCH_1020,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE4_MATCH_1019,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1017,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_0_PAD_OR_266_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PAD_1045,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_PIPE_0_PAD_OR_266_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_TX_FAIL_REG2_OR_181_o1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG1_1053,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_REG2_1052,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_TX_FAIL_REG2_OR_181_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURSTING1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_21_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(13),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_21_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_31_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(23),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_31_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_41 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_bdd6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_41 : LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_bdd6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_20_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(12),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_20_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_22_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(14),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_22_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_21 : LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_bdd2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_17_1 : LUT5
    generic map(
      INIT => X"D7287D82"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_bdd6,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_17_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_1 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(15),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_bdd2,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_29_1 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(21),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_29_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT13 : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT111 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(11),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_19_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT181 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(17),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_25_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT241 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(22),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_30_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_In1 : LUT6
    generic map(
      INIT => X"FF04FF0004040000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_LENGTH_419,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_In
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_In1 : LUT6
    generic map(
      INIT => X"0000100044445444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_406,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_In
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_2_11 : LUT4
    generic map(
      INIT => X"2AAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_3_11 : LUT5
    generic map(
      INIT => X"222AAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_1_11 : LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_4_11 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_5_11 : LUT5
    generic map(
      INIT => X"0222AAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_6_11 : LUT4
    generic map(
      INIT => X"02AA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_7_11 : LUT5
    generic map(
      INIT => X"0002AAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Mmux_BACKOFF_VALUE_9_11 : LUT5
    generic map(
      INIT => X"02222222"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT241 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(22),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_30_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT181 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(17),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_25_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT111 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(11),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_19_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT11 : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_29_1 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(21),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_29_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_1 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(15),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_bdd2,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_17_1 : LUT5
    generic map(
      INIT => X"D7287D82"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_bdd6,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_17_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_21 : LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_bdd2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_22_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(14),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_22_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_20_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(12),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_20_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_41 : LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_bdd6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_41 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_bdd6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_31_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(23),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_31_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_21_1 : LUT4
    generic map(
      INIT => X"6CC6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(13),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_21_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG11 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv11 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_n0251_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_GND_44_o_FRAME_SUCCESS_MUX_1121_o11 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1300,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1362,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_1303,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1361,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_FRAME_SUCCESS_MUX_1121_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_GND_44_o_GND_44_o_MUX_1120_o11 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1300,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_1303,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1362,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_GND_44_o_MUX_1120_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT16 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(16),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT21 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(26),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT31 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(27),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_11_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT41 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(28),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_12_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT51 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(29),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_13_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT61 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(30),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_14_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT71 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(17),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT81 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(18),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT91 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(19),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT101 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(20),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT111 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(21),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT121 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(22),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT131 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(23),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT141 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => rx_mac_config_vector(24),
      I2 => rx_mac_config_vector(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mmux_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT151 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => rx_mac_config_vector(25),
      I1 => rx_mac_config_vector(14),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD_14_GND_44_o_mux_5_OUT_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_480_o1 : LUT5
    generic map(
      INIT => X"44444000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_LEN_FIELD_AND_480_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_483_o1 : LUT5
    generic map(
      INIT => X"44444000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DAT_FIELD_AND_483_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_474_o1 : LUT6
    generic map(
      INIT => X"4444444440004040"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_DEST_ADDRESS_FIELD_AND_474_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT31 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT41 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT51 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT61 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_333_o1 : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1418,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_END_DATA_OR_333_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable3 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_NO_FCS_DATA_WITH_FCS_MUX_1016_o11 : LUT6
    generic map(
      INIT => X"8888888D88888888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_CRC_MODE_HELD_1311,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1587,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1589,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1586,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_DATA_WITH_FCS_MUX_1016_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_48_o_RXD_7_equal_9_o_7_1 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_48_o_RXD_7_equal_9_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_56_o_RXD_7_equal_15_o_7_1 : LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PWR_56_o_RXD_7_equal_15_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o11 : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_0_GND_48_o_MUX_972_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_0_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_0_GND_48_o_MUX_972_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_1_GND_48_o_MUX_971_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_1_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_1_GND_48_o_MUX_971_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_3_GND_48_o_MUX_969_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_3_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_3_GND_48_o_MUX_969_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_4_GND_48_o_MUX_968_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_4_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_4_GND_48_o_MUX_968_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_2_GND_48_o_MUX_970_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_2_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_2_GND_48_o_MUX_970_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_5_GND_48_o_MUX_967_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_5_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_5_GND_48_o_MUX_967_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_6_GND_48_o_MUX_966_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_6_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_6_GND_48_o_MUX_966_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_8_GND_48_o_MUX_964_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_8_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_8_GND_48_o_MUX_964_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_9_GND_48_o_MUX_963_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_9_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_9_GND_48_o_MUX_963_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_7_GND_48_o_MUX_965_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_7_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_7_GND_48_o_MUX_965_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_DATA_COUNTER_10_GND_48_o_MUX_962_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_14_GND_48_o_add_6_OUT_10_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER_10_GND_48_o_MUX_962_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv1 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0321_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1582,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_FRAME_COUNTER_14_AND_533_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_FIELD_COUNTER_1_AND_506_o1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_FIELD_COUNTER_1_AND_506_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT811 : LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT81_1592
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_548_o1 : LUT4
    generic map(
      INIT => X"7770"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1623,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_END_OF_FRAME_SFD_FLAG_AND_548_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT4111 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Reset_OR_DriverANDClockEnable
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_396_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1624,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1625,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_CRC_ENGINE_ERR_OR_396_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_364_o1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1632,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_EXCEEDED_MIN_LEN_OR_364_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tlast_tx_mac_tready_int_AND_22_o1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I2 => tx_axis_mac_tlast,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_glue_set
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_In1 : LUT6
    generic map(
      INIT => X"4444F5F4F5F4F5F4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_1652,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      I4 => tx_axis_mac_tlast,
      I5 => tx_axis_mac_tuser(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_In
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_In1 : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9_1634,
      I1 => tx_axis_mac_tlast,
      I2 => tx_axis_mac_tuser(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_73_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9_In1 : LUT5
    generic map(
      INIT => X"00000200"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663,
      I2 => tx_axis_mac_tuser(0),
      I3 => tx_axis_mac_tvalid,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_1668,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_30_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_two_byte_tx_OR_38_o1 : LUT6
    generic map(
      INIT => X"8888800080008000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_1665,
      I1 => tx_axis_mac_tvalid,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_3_tx_state_3_OR_37_o,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_two_byte_tx_OR_38_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd5_In1 : LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I1 => tx_axis_mac_tuser(0),
      I2 => tx_axis_mac_tlast,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_74_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT81 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(0),
      I2 => tx_axis_mac_tdata(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT71 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(1),
      I2 => tx_axis_mac_tdata(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT61 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(2),
      I2 => tx_axis_mac_tdata(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT51 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(3),
      I2 => tx_axis_mac_tdata(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT41 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(4),
      I2 => tx_axis_mac_tdata(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(5),
      I2 => tx_axis_mac_tdata(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT21 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(6),
      I2 => tx_axis_mac_tdata(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT12 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_hold(7),
      I2 => tx_axis_mac_tdata(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_7_tx_mac_tdata_7_mux_66_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT111 : LUT5
    generic map(
      INIT => X"FFFFFFF8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_Mmux_tx_data_7_tx_mac_tdata_7_mux_66_OUT11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv1 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_n0280_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_In1 : LUT4
    generic map(
      INIT => X"BA10"
    )
    port map (
      I0 => tx_axis_mac_tvalid,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_GND_25_o_equal_75_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_tx_state_3_tx_state_3_OR_37_o1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_1652,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_3_tx_state_3_OR_37_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_int1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      O => NlwRenamedSig_OI_tx_axis_mac_tready
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tlast_tx_mac_tvalid_OR_21_o1 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => tx_axis_mac_tlast,
      I1 => tx_axis_mac_tvalid,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tlast_tx_mac_tvalid_OR_21_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_VLAN_ENABLE_OUT1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => tx_mac_config_vector(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_VLAN_ENABLE_OUT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result_3_1 : LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result_4_1 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n008111 : LUT6
    generic map(
      INIT => X"0000000000400000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00811
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00811,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0100_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_xor_2_11 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_GOOD_FRAME_OUT11 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_346,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1696,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1777,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_COMB
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv1 : LUT6
    generic map(
      INIT => X"AAAAAAAAA8AAAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_349,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0127_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_BAD_FRAME_OUT11 : LUT5
    generic map(
      INIT => X"FFFF2000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1777,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_346,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1696,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_COMB
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_val
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv11 : LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(2),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0123_inv1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010517 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(15),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010521 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010531 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010541 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010551 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010561 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010571 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010581 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n010591 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105101 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105111 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105121 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105131 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105141 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105151 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mmux_n0105161 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_VALUE(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n0105(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1777,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_345,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      O => rx_statistics_vector(24)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_346,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1696,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1778,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_REQ_LOCAL
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_3_11 : LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_xor_2_11 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o111 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11 : LUT6
    generic map(
      INIT => X"5557555755575556"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_REG_1819,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_Mux_26_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_AVAIL_OUT11 : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_UNDERRUN_OUT11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1_2580,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_1691,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT11 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT21 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT41 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT51 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT61 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT71 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_OUT81 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_INT(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_CONTROL(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_OUT(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0172_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_CONTROL_COMPLETE_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_CONTROL_COMPLETE
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_86_o1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN2_1907,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN3_1906,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_1905,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_GOOD_FRAME_IN1_GOOD_FRAME_IN3_OR_86_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_3_11 : LUT6
    generic map(
      INIT => X"7F807F8000007F80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_2_11 : LUT5
    generic map(
      INIT => X"78780078"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_1_11 : LUT4
    generic map(
      INIT => X"6606"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_0_11 : LUT3
    generic map(
      INIT => X"51"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o121 : LUT3
    generic map(
      INIT => X"20"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o12_1908
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_xor_2_11 : LUT6
    generic map(
      INIT => X"7878780078007878"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_pipe_2_GND_52_o_MUX_1193_o11 : LUT6
    generic map(
      INIT => X"00EB00EB00EBEBEB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_pipe_2_GND_52_o_MUX_1193_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_address_match_address_match_MUX_1221_o11 : LUT6
    generic map(
      INIT => X"FFFE0000FFFEFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_2031,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_2030,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_2032,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_2029,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match_address_match_MUX_1221_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv1 : LUT6
    generic map(
      INIT => X"5555000055570003"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0297_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_specialpauseaddressmatch_int_specialpauseaddressmatch_int_MUX_1215_o11 :
LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_2029,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      O =>
U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_int_specialpauseaddressmatch_int_MUX_1215_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_pauseaddressmatch_int_pauseaddressmatch_int_MUX_1203_o11 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_2030,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_int_pauseaddressmatch_int_MUX_1203_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_broadcastaddressmatch_int_broadcastaddressmatch_int_MUX_1185_o11 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_2031,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_int_broadcastaddressmatch_int_MUX_1185_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_5_11 : LUT6
    generic map(
      INIT => X"F0780000F078F078"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv1 : LUT6
    generic map(
      INIT => X"FFFFFF007F7FFF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0294_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0300_inv1 : LUT6
    generic map(
      INIT => X"00FF0FFF66FF6FFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_DATA_VALID_EARLY,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_n0300_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_111 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_Mmux_next_rx_state11 : LUT6
    generic map(
      INIT => X"BBBABBBABBBAB990"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"040404AE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_In
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_rx_state_1_GND_24_o_equal_28_o1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_GND_24_o_equal_28_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET1 : LUT6
    generic map(
      INIT => X"000000000000000E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_DELAY_SHIFT_REG(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv1,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_12 : LUT4
    generic map(
      INIT => X"FFA9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT_xor_2_11 : LUT5
    generic map(
      INIT => X"A9FFA9A9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_1_11 : LUT3
    generic map(
      INIT => X"41"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_11,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_111 : LUT6
    generic map(
      INIT => X"0000200000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2_2125,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_2131,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv11 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_NORMAL_COUNT_xor_3_111 : LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2_2125,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_NORMAL_COUNT_xor_3_11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_0_11 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0190_inv1 : LUT5
    generic map(
      INIT => X"FFFFFFBA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0190_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT_xor_1_11 : LUT4
    generic map(
      INIT => X"9F99"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT_xor_0_11 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_PREAMBLE_COUNT
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_COL_REG1_GND_43_o_MUX_807_o11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => gmii_col,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_GND_43_o_MUX_807_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_In_SW0 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(2),
      O => N2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_In : LUT6
    generic map(
      INIT => X"CCDCCCCC00100000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_386,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(3),
      I4 => N2,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_418,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_In_389
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_In_SW0 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(2),
      O => N4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_In : LUT6
    generic map(
      INIT => X"AAAAA888FAAAFAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      I1 => N4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_CRS_397,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_IFG_COUNT(3),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_In_391
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_4_1_SW0 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0),
      O => N6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_4_1 : LUT6
    generic map(
      INIT => X"FFFFA9AAFFFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I3 => N6,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_5_1_SW0 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(0),
      O => N8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT_xor_5_1 : LUT6
    generic map(
      INIT => X"FFFFA9AAFFFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      I3 => N8,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_ATTEMPT_COUNT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_SW0 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      O => N12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o : LUT6
    generic map(
      INIT => X"0054005500000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_DELAY_1051,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I4 => N12,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14481 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14481_2146
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14482 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14482_2147
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14483 : LUT6
    generic map(
      INIT => X"ECA00000A0A00000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14482_2147,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14481_2146,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1448
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1434_SW0 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      O => N14
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1434 : LUT6
    generic map(
      INIT => X"5777022202220222"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => N14,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_930,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1434_740
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1438_SW0 : LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      O => N16
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER1 : LUT5
    generic map(
      INIT => X"FF01FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_1_2579,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_RETRANSMIT_372,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER2 : LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER1_2151
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER3 : LUT6
    generic map(
      INIT => X"FFFFFFFF88F80000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1_2595,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER1_2151,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(8),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(3),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv1_2152
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv2 : LUT6
    generic map(
      INIT => X"5555555544404040"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_898,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv1_2152,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv2_2153
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT6_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      O => N20
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT6 : LUT6
    generic map(
      INIT => X"0000CC3300000A0A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => N20,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT5_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      O => N22
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT5 : LUT6
    generic map(
      INIT => X"0000CC3300000A0A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => N22,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT4_SW0 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      O => N24
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT4 : LUT6
    generic map(
      INIT => X"0000FF000000CACA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => N24,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT3_SW0 : LUT3
    generic map(
      INIT => X"A9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      O => N26
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT3 : LUT6
    generic map(
      INIT => X"FFFFFF00FFFFCACA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => N26,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14501 : LUT6
    generic map(
      INIT => X"0C0FFFFF8CAFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14501_2158
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT8_SW0 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(7),
      O => N30
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT8 : LUT6
    generic map(
      INIT => X"00A900A900FF0000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Msub_GND_37_o_GND_37_o_sub_27_OUT_7_0_cy_5_Q,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I4 => N30,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1466_SW0 : LUT5
    generic map(
      INIT => X"AAAA0888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_ER_IN_965,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_1054,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN_966,
      O => N34
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1527_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      O => N36
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1795_inv1 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(9),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1795_inv1_2162
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT2_SW0 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      O => N38
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_IFG_COUNT_7_GND_37_o_mux_33_OUT2 : LUT6
    generic map(
      INIT => X"0000FF0000003A3A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_DELAY_HELD(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I3 => N38,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_TX_FAIL_DELAY_AND_215_o_679,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT_7_GND_37_o_mux_33_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1440_SW0 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      O => N42
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1440 : LUT6
    generic map(
      INIT => X"3000770000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I4 => N42,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1440_738
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1420_SW0 : LUT3
    generic map(
      INIT => X"B3"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_924,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => N44
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1420 : LUT6
    generic map(
      INIT => X"A0A00000A0A80000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_404,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      I5 => N44,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1420_741
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o2 : LUT6
    generic map(
      INIT => X"1111111110101110"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_969,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_898,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o1_2166,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14541 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14541_2167
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14542 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14542_2168
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14543 : LUT6
    generic map(
      INIT => X"EF0FEA0AE000E000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14543_2169
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14544 : LUT6
    generic map(
      INIT => X"FFFF0000C4C00000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14543_2169,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14541_2167,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14542_2168,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1454
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(13),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(12),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(15),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(7),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_2170
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_2171
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN13 : LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_2171,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_2170,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o1 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(18),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(17),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(16),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o2 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(15),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(13),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(12),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(11),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o1_2173
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o3 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT_18_INT_SPEED_IS_10_100_AND_224_o1_2173,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_PRE_REG
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0_INT_TX_DA_AND_315_o_0_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(7),
      O => N46
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0_INT_TX_DA_AND_315_o_0_Q : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2(3),
      I5 => N46,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_2_0_INT_TX_DA_AND_315_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0_INT_TX_DA_AND_331_o_0_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(7),
      O => N48
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0_INT_TX_DA_AND_331_o_0_Q : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0(3),
      I5 => N48,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0_INT_TX_DA_AND_331_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0_INT_TX_DA_AND_299_o_0_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(7),
      O => N50
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0_INT_TX_DA_AND_299_o_0_Q : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4(3),
      I5 => N50,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_4_0_INT_TX_DA_AND_299_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0_INT_TX_DA_AND_307_o_0_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      O => N52
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0_INT_TX_DA_AND_307_o_0_Q : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I5 => N52,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3_0_INT_TX_DA_AND_307_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0_INT_TX_DA_AND_323_o_0_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7),
      O => N54
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0_INT_TX_DA_AND_323_o_0_Q : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3),
      I5 => N54,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1_0_INT_TX_DA_AND_323_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15081 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(5),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15081_2179
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15082 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(14),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(13),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15082_2180
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_SW0 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      O => N56
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_bdd6,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N56,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_Q_1092
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_26_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      O => N58
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_26_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(18),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N58,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_26_Q_1106
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_2_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      O => N60
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_2_Q : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_23_bdd2,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I5 => N60,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_2_Q_1082
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_4_SW0 : LUT4
    generic map(
      INIT => X"9669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      O => N62
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_4_Q : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I5 => N62,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_4_Q_1084
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_6_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      O => N64
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_6_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_12_bdd6,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N64,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_6_Q_1086
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_7_SW0 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => N66
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_7_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N66,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_7_Q_1087
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_16_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => N68
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_16_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(8),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N68,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_16_Q_1096
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_18_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      O => N70
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_18_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(10),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N70,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_18_Q_1098
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_24_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      O => N72
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_24_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(16),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N72,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_24_Q_1104
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_28_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      O => N74
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_28_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(20),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => N74,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_28_Q_1108
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_3_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      O => N76
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_3_Q : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I5 => N76,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_3_Q_1083
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      O => N78
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_Q : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(6),
      I5 => N78,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_14_Q_1094
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT2_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => N80
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT2 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(2),
      I5 => N80,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT3_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      O => N82
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT3 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(3),
      I5 => N82,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_11_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT51 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT52 : LUT6
    generic map(
      INIT => X"6996966996696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT51_2196
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT53 : LUT5
    generic map(
      INIT => X"69FF6900"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT51_2196,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT5,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_13_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT7_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => N84
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT7 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(7),
      I5 => N84,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_15_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT12_SW0 : LUT4
    generic map(
      INIT => X"9669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      O => N86
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT12 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I5 => N86,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT20_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => N88
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT20 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(19),
      I5 => N88,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_27_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT281 : LUT6
    generic map(
      INIT => X"6996966996696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT28
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT282 : LUT6
    generic map(
      INIT => X"6996966996696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT281_2201
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT283 : LUT6
    generic map(
      INIT => X"6996FFFF69960000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT281_2201,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT28,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT31 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(0),
      I5 => N82,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT32_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => N92
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_Mmux_CALC_23_CALC_23_mux_3_OUT32 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COMPUTE_1043,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(1),
      I5 => N92,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC_23_CALC_23_mux_3_OUT_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_1 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_2 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(8),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(10),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_1_2204
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_3 : LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_1_2204,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o_12_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT32_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => N94
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT32 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(1),
      I5 => N94,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT31_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      O => N96
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT31 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(0),
      I5 => N96,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT281 : LUT6
    generic map(
      INIT => X"6996966996696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT28
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT282 : LUT6
    generic map(
      INIT => X"6996966996696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT281_2208
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT283 : LUT6
    generic map(
      INIT => X"6996FFFF69960000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT281_2208,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT28,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT20_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => N98
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT20 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(19),
      I5 => N98,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_27_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT12_SW0 : LUT4
    generic map(
      INIT => X"9669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      O => N100
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT12 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I5 => N100,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT7_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => N102
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT7 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(7),
      I5 => N102,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_15_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT51 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT52 : LUT6
    generic map(
      INIT => X"6996966996696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT51_2213
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT53 : LUT5
    generic map(
      INIT => X"69FF6900"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT51_2213,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT5,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_13_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT3 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(3),
      I5 => N96,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_11_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT2_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => N106
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_Mmux_CALC_23_CALC_23_mux_3_OUT2 : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(2),
      I5 => N106,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      O => N108
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_Q : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(6),
      I5 => N108,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_Q_1258
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_3_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      O => N110
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_3_Q : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I5 => N110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_3_Q_1269
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_28_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      O => N112
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_28_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(20),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N112,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_28_Q_1244
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_24_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      O => N114
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_24_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(16),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N114,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_24_Q_1248
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_18_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      O => N116
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_18_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(10),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N116,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_18_Q_1254
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_16_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => N118
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_16_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(8),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N118,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_16_Q_1256
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_7_SW0 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      O => N120
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_7_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N120,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_7_Q_1265
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_6_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      O => N122
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_6_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_bdd6,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N122,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_6_Q_1266
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_4_SW0 : LUT4
    generic map(
      INIT => X"9669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      O => N124
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_4_Q : LUT6
    generic map(
      INIT => X"D77D28827DD78228"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I5 => N124,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_4_Q_1268
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_2_SW0 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      O => N126
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_2_Q : LUT6
    generic map(
      INIT => X"E44E4EE44EE4E44E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_23_bdd2,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I5 => N126,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_2_Q_1270
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_26_SW0 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      O => N128
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_26_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_14_bdd6,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(18),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N128,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_26_Q_1246
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_SW0 : LUT6
    generic map(
      INIT => X"9669699669969669"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      O => N130
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_Q : LUT6
    generic map(
      INIT => X"6996FF009669FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_bdd6,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I5 => N130,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC_23_CALC_23_mux_3_OUT_12_Q_1260
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_RX_DV_REG6_AND_454_o2_SW0 : LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5),
      O => N132
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_RX_DV_REG6_AND_454_o2 : LUT6
    generic map(
      INIT => X"0000000010000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3),
      I5 => N132,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GND_44_o_RX_DV_REG6_AND_454_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_52_o_RX_ERR_REG6_AND_452_o1_SW0 : LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(0),
      O => N134
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_52_o_RX_ERR_REG6_AND_452_o1 : LUT6
    generic map(
      INIT => X"0000000001000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG6(7),
      I5 => N134,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PWR_52_o_RX_ERR_REG6_AND_452_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG2_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(0),
      O => N136
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG2 : LUT6
    generic map(
      INIT => X"0000200000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I4 => N136,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG1 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      I5 => N136,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_IFG_FLAG
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      O => N140
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1_2597,
      I5 => N140,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT2_SW0 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      O => N146
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT2 : LUT6
    generic map(
      INIT => X"1111111111111110"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => N146,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT1_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      O => N148
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_Mmux_FIELD_CONTROL_5_GND_47_o_mux_2_OUT1 : LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAAB"
    )
    port map (
      I0 => N148,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      I5 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL_5_GND_47_o_mux_2_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_360_o_SW0 : LUT5
    generic map(
      INIT => X"ABAAFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1377,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1380,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_NO_FCS_1586,
      O => N152
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_360_o : LUT6
    generic map(
      INIT => X"FFFFFFFF00010101"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ZERO_1589,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_ONE_1588,
      I2 => N152,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RECLOCK_RX_CONFIG,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_DATA_NO_FCS_OR_360_o_1536
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o_SW0 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1590,
      O => N154
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o : LUT6
    generic map(
      INIT => X"0000000010000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_FIELD_COUNTER_1_AND_506_o,
      I5 => N154,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o_1539
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o11 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(9),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(8),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o12 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(10),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(10),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o11_2236
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o13 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o12_2237
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Reset_OR_DriverANDClockEnable2_SW0 : LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      O => N158
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_56_o_AND_540_o_0_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VLAN_ENABLE_HELD_1312,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      O => N160
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_56_o_AND_540_o_0_Q : LUT6
    generic map(
      INIT => X"0800000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I5 => N160,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_ENABLE_PWR_56_o_AND_540_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT7_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3),
      O => N164
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02131 : LUT6
    generic map(
      INIT => X"8040200008040201"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02131_2241
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02132 : LUT6
    generic map(
      INIT => X"00200020AAAA0020"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1376,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_ENABLE_HELD_1308,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02132_2242
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02133 : LUT6
    generic map(
      INIT => X"BBBFBBBB000F0000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_ENABLE_HELD_1308,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1376,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02132_2242,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02131_2241,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02133_2243
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv11 : LUT6
    generic map(
      INIT => X"8020401008020401"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(8),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv11_2244
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv12 : LUT6
    generic map(
      INIT => X"8020401008020401"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv12_2245
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv13 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(13),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(11),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(12),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv13_2246
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv14 : LUT6
    generic map(
      INIT => X"8008400420021001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_LENGTH_HELD(10),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv14_2247
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv15 : LUT5
    generic map(
      INIT => X"40000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv12_2245,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv11_2244,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv14_2247,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv13_2246,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_SW0 : LUT6
    generic map(
      INIT => X"0001000000010001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_1621,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      O => N168
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o1 : LUT6
    generic map(
      INIT => X"00B000B0BBBB00B0"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MIN_LENGTH_MATCH_1632,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_345,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PAUSE_LT_CHECK_HELD_1309,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1381,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o1_2249
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o2 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1381,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1377,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1380,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o2_2250
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o3 : LUT6
    generic map(
      INIT => X"FFA8FFA8FFFFFFA8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o2_2250,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o1_2249,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1630,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_END_OF_DATA_OR_370_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT101 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(8),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_384_o_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1339,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342,
      O => N172
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_384_o : LUT6
    generic map(
      INIT => X"FFFFFFFFAEFFAEAE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1624,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_EXTENSION_FLAG_1306,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I4 => N172,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1625,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_EXTENSION_FIELD_OR_384_o_1608
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_49_o_FRAME_COUNTER_7_equal_1_o_7_SW0 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1),
      O => N176
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_49_o_FRAME_COUNTER_7_equal_1_o_7_Q : LUT6
    generic map(
      INIT => X"0000000010000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5),
      I5 => N176,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GND_49_o_FRAME_COUNTER_7_equal_1_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_In_SW0 : LUT5
    generic map(
      INIT => X"FFFFEAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I3 => tx_axis_mac_tlast,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      O => N178
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_In : LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_1666,
      I3 => tx_axis_mac_tvalid,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I5 => N178,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_In_1635
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_In_SW0 : LUT6
    generic map(
      INIT => X"0004040404040404"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I5 => tx_axis_mac_tlast,
      O => N180
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_In : LUT6
    generic map(
      INIT => X"FFFFFFFFAAAA88A8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      I3 => tx_axis_mac_tvalid,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      I5 => N180,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_PWR_24_o_equal_77_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o1_2256
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o2 : LUT4
    generic map(
      INIT => X"2AAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I2 => tx_axis_mac_tlast,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o2_2257
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o3 : LUT6
    generic map(
      INIT => X"AAAAAAAA88888880"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o1_2256,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o2_2257,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o3_2258
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o4 : LUT6
    generic map(
      INIT => X"A8A8A8A8A8AAA8A8"
    )
    port map (
      I0 => tx_axis_mac_tvalid,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      I3 => tx_axis_mac_tuser(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_1668,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o4_2259
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o5 : LUT6
    generic map(
      INIT => X"FFFFFFFF54444444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I2 => tx_axis_mac_tlast,
      I3 => tx_axis_mac_tuser(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o5_2260
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o6 : LUT5
    generic map(
      INIT => X"FFFFFFBA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o5_2260,
      I1 => tx_axis_mac_tlast,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9_1634,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o4_2259,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o3_2258,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_ignore_packet_OR_49_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_In_SW0 : LUT4
    generic map(
      INIT => X"8880"
    )
    port map (
      I0 => tx_axis_mac_tlast,
      I1 => tx_axis_mac_tuser(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_1652,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd9_1634,
      O => N182
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_In : LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd5_1657,
      I1 => N182,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_1666,
      I5 => tx_axis_mac_tvalid,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_In_1637
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_In_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_1668,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663,
      I2 => tx_axis_mac_tuser(0),
      O => N184
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_In : LUT6
    generic map(
      INIT => X"FFFFFFFFB3A2A2A2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I1 => tx_axis_mac_tvalid,
      I2 => N184,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_1650,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_tx_enable_reg_AND_28_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_int_tx_ack_OR_32_o_SW0 : LUT4
    generic map(
      INIT => X"8088"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I2 => tx_axis_mac_tuser(0),
      I3 => tx_axis_mac_tvalid,
      O => N186
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_int_tx_ack_OR_32_o : LUT6
    generic map(
      INIT => X"FFFF444044404440"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_1662,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_1666,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I5 => N186,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun_glue_set
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_1 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_2 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_OPCODE_EARLY(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(2),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_1_2265
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_3 : LUT6
    generic map(
      INIT => X"0000000001000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_1_2265,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o_7_Q,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0150_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => N192
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0150 : LUT6
    generic map(
      INIT => X"0000000013131353"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1818,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX,
      I5 => N192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0150_1808
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_SW0 : LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => N194
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv : LUT6
    generic map(
      INIT => X"8888880008080800"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_1837,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839,
      I5 => N194,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156_SW0 : LUT5
    generic map(
      INIT => X"FDFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => N196
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156 : LUT6
    generic map(
      INIT => X"000010F00000F0F0"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_1837,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => N196,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156_1807
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"FFFF0010"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1818,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1_2269
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In3 : LUT5
    generic map(
      INIT => X"7474FE74"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In1_2269,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In2_2270,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_CONTROL_COMPLETE,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT101 : LUT4
    generic map(
      INIT => X"AC00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(11),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT102 : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(43),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(35),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT101_2272
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT103 : LUT6
    generic map(
      INIT => X"7776676655544544"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(19),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(27),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT101_2272,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT102_2273
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT104 : LUT5
    generic map(
      INIT => X"88800800"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT103_2274
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT105 : LUT5
    generic map(
      INIT => X"FFFF5410"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT103_2274,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT102_2273,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT10,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT71 : LUT6
    generic map(
      INIT => X"F0F0FF00CCCCAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(18),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(34),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(42),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(26),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT72 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT71_2276
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT141 : LUT6
    generic map(
      INIT => X"F0F0FF00CCCCAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(21),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(37),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(45),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(29),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT14
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT142 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT141_2278
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT121 : LUT6
    generic map(
      INIT => X"F0F0FF00CCCCAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(20),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(36),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(44),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(28),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT12
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT122 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT121_2280
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT31 : LUT6
    generic map(
      INIT => X"DDA2DD8099A29980"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(40),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(24),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT32 : LUT6
    generic map(
      INIT => X"5499109954111011"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(16),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(32),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT31_2282
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT33 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(8),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT32_2283
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT34 : LUT6
    generic map(
      INIT => X"FFFF514051405140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT3,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT31_2282,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT32_2283,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT51 : LUT4
    generic map(
      INIT => X"AC00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT52 : LUT6
    generic map(
      INIT => X"4440040004000400"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(9),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT51_2285
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT53 : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(41),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(25),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT52_2286
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT54 : LUT6
    generic map(
      INIT => X"FB44EA4451444044"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(33),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(17),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT52_2286,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT53_2287
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT55 : LUT5
    generic map(
      INIT => X"FFFF5150"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT51_2285,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT53_2287,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT5,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT161 : LUT4
    generic map(
      INIT => X"AC00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(14),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT16
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT162 : LUT6
    generic map(
      INIT => X"4440040004000400"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(14),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT161_2289
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT163 : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(46),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(30),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT162_2290
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT164 : LUT6
    generic map(
      INIT => X"FB44EA4451444044"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(38),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(22),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT162_2290,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT163_2291
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT165 : LUT5
    generic map(
      INIT => X"FFFF5150"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT161_2289,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT163_2291,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT16,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT191 : LUT4
    generic map(
      INIT => X"AC00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(15),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_Mux_26_o11_1787,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT19
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT192 : LUT4
    generic map(
      INIT => X"A0CF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(47),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(39),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT191_2293
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT193 : LUT6
    generic map(
      INIT => X"54FF10FF54101010"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(15),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT191_2293,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT192_2294
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT194 : LUT5
    generic map(
      INIT => X"75226422"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(31),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_SOURCE_HELD(23),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT193_2295
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT195 : LUT5
    generic map(
      INIT => X"FFFF5410"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT193_2295,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT192_2294,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT19,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_4_1_SW0 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      O => N200
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_4_1 : LUT6
    generic map(
      INIT => X"2888888888888888"
    )
    port map (
      I0 => N200,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_5_1_SW0 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      O => N202
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA_xor_5_1 : LUT6
    generic map(
      INIT => X"F0780000F078F078"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(5),
      I3 => N202,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_QUANTA5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_SW0 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      O => N204
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv : LUT6
    generic map(
      INIT => X"FFFFFFFF08000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(3),
      I2 => N204,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_QUANTA(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o12_1908,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_n0068_inv_1956
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(8),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o12 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(15),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(3),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o1,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o11_2300
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_1 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_2 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(8),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(10),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_1_2302
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT71 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(46),
      I3 => rx_mac_config_vector(78),
      I4 => rx_mac_config_vector(70),
      I5 => rx_mac_config_vector(38),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT7
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT72 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(62),
      I3 => rx_mac_config_vector(54),
      I4 => rx_mac_config_vector(38),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT71_2304
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT73 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT7,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT71_2304,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT61 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(45),
      I3 => rx_mac_config_vector(77),
      I4 => rx_mac_config_vector(69),
      I5 => rx_mac_config_vector(37),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT6
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT62 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(61),
      I3 => rx_mac_config_vector(53),
      I4 => rx_mac_config_vector(37),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT61_2306
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT63 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT6,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT61_2306,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT51 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(44),
      I3 => rx_mac_config_vector(76),
      I4 => rx_mac_config_vector(68),
      I5 => rx_mac_config_vector(36),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT5
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT52 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(60),
      I3 => rx_mac_config_vector(52),
      I4 => rx_mac_config_vector(36),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT51_2308
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT53 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT5,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT51_2308,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT41 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(43),
      I3 => rx_mac_config_vector(75),
      I4 => rx_mac_config_vector(67),
      I5 => rx_mac_config_vector(35),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT42 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(59),
      I3 => rx_mac_config_vector(51),
      I4 => rx_mac_config_vector(35),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT41_2310
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT43 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT41_2310,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT31 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(42),
      I3 => rx_mac_config_vector(74),
      I4 => rx_mac_config_vector(66),
      I5 => rx_mac_config_vector(34),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT32 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(58),
      I3 => rx_mac_config_vector(50),
      I4 => rx_mac_config_vector(34),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT31_2312
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT33 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT3,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT31_2312,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT21 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(41),
      I3 => rx_mac_config_vector(73),
      I4 => rx_mac_config_vector(65),
      I5 => rx_mac_config_vector(33),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT22 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(57),
      I3 => rx_mac_config_vector(49),
      I4 => rx_mac_config_vector(33),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT21_2314
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT23 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT2,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT21_2314,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT11 : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I2 => rx_mac_config_vector(40),
      I3 => rx_mac_config_vector(72),
      I4 => rx_mac_config_vector(64),
      I5 => rx_mac_config_vector(32),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT12 : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(56),
      I3 => rx_mac_config_vector(48),
      I4 => rx_mac_config_vector(32),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT11_2316
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT13 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT1,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT11_2316,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb81 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(7),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb82 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb81_2318
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb83 : LUT6
    generic map(
      INIT => X"8421000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_addr_lut(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb8,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb81_2318,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_comb
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o81 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(7),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o8
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o82 : LUT6
    generic map(
      INIT => X"8040201008040201"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o81_2320
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o83 : LUT6
    generic map(
      INIT => X"8421000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_expected_pause_data(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o8,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o81_2320,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_rx_data_7_MUX_1197_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_rx_data_7_MUX_1177_o_7_SW0 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      O => N206
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_rx_data_7_MUX_1177_o_7_Q : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I5 => N206,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_rx_data_7_MUX_1177_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state_1_rx_enable_AND_7_o1 : LUT6
    generic map(
      INIT => X"2222222220202000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_next_rx_state_1_rx_enable_AND_7_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_next_rx_state_1_OR_9_o1_SW0 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317,
      O => N208
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_next_rx_state_1_OR_9_o1 : LUT6
    generic map(
      INIT => X"FFFFFFFF1F7F0F0F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I4 => N208,
      I5 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_next_rx_state_1_OR_9_o_0
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0),
      O => N210
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o : LUT6
    generic map(
      INIT => X"00000000F0E0FFEE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I5 => N210,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_glue_set_2324,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_400
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CAPTURE : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_EARLY,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CAPTURE_401
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_glue_rst_2325,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_926
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_glue_rst_2326,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_927
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_glue_set_2327,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_928
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set_2328,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set_2329,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set_2330,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set_2331,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set_2332,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set_2333,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set_2334,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set_2335,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set_2336,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set_2337,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set_2338,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set_2339,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set_2340,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set_2341,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_glue_set_2342,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_glue_set_2343,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_898
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_set_2345,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_899
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_ce : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_899,
      I2 => NlwRenamedSig_OI_N1,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_ce_2344
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_glue_rst_2346,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_900
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_glue_rst_2347,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_901
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_glue_set_2348,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_902
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_glue_set_2349,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_glue_set_2350,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_903
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_glue_set_2351,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_919
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_glue_set_2352,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_920
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_glue_set_2353,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_glue_rst_2354,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_glue_set_2355,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_glue_set_2357,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_930
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_glue_set_2358,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_glue_set_2359,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_glue_set_2360,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_933
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_set_2362,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_glue_set_2363,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_glue_set_2364,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst_2365,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_glue_set_2366,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_glue_set_2367,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_glue_set_2368,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_glue_set_2369,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_glue_set_2370,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_glue_set_2371,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_942
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_glue_set_2372,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_943
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_glue_set_2373,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_glue_set_2374,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_glue_set_2375,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_glue_set_2376,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_glue_set_2377,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_glue_set_2378,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_glue_rst_2379,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_glue_set_2380,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_0_glue_set_2381,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set_2382,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1300
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_2383,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_2384,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_2385,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_glue_set_2386,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1622
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_glue_set_2387,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_1621
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_glue_set_2388,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_1658
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_glue_set_2389,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_1660
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_glue_set_2390,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_1659
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_glue_set_2391,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_glue_set_2392,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_1662
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_glue_set_2393,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_glue_set_2394,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_336
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_glue_set,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_1665
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun_glue_set,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_underrun_335
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set_2397,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_2398,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1778
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set_2399,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1777
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_0 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_0_glue_rst_2400,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_glue_rst_2401,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_1 : FDS
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_1_glue_rst_2402,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set_2403,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set_2404,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1818
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set_2405,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_glue_set_2406,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_2030
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_glue_set_2407,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_2029
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_glue_set_2408,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_2031
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_glue_set_2409,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_296
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_glue_set_2410,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_7 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_7_glue_set_2411,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_6 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_6_glue_set_2412,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_5 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_5_glue_set_2413,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_4 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_4_glue_set_2414,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_3 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_3_glue_set_2415,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_2_glue_set_2416,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_1_glue_set_2417,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_0 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_0_glue_set_2418,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_glue_set_2419,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_8_rt_2420
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_7_rt_2421
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_6_rt_2422
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_5_rt_2423
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_4_rt_2424
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_3_rt_2425
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_2_rt_2426
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_cy_1_rt_2427
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_13_rt_2428
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_12_rt_2429
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_11_rt_2430
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_10_rt_2431
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_9_rt_2432
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_8_rt_2433
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_7_rt_2434
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_6_rt_2435
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_5_rt_2436
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_4_rt_2437
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_3_rt_2438
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_2_rt_2439
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_cy_1_rt_2440
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_9_rt_2441
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_8_rt_2442
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_7_rt_2443
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_6_rt_2444
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_5_rt_2445
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_4_rt_2446
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_3_rt_2447
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_2_rt_2448
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_cy_1_rt_2449
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_xor_9_rt_2450
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_xor_14_rt_2451
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_xor_10_rt_2452
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1017,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_0_0_INT_TX_DA_AND_331_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot_2453
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_rstpot_2453,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_BYTE5_MATCH_1017
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot_2457,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_1302,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_in,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_rstpot_2458
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD : FDS
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_rstpot_2458,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_1302
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_rstpot_2459,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_1303
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot_2460,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1380
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot_2461,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1584
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET : FDS
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_2462,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1377
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot_2463,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1578
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot_2464,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1581
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_rstpot_2465,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_1626
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_rstpot_2467,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot_2468,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample : FDS
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_rstpot_2469,
      S => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_2032
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_rstpot_2470,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_924
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1 : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_rstpot_2471,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_rstpot_2472,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_1668
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_rstpot_2473,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_rstpot_2474,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_300
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_rstpot_2475,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_rstpot,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_273
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_rstpot,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_274
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot_2478,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_rstpot_2479,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_rstpot_2480,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_1666
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_2481,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_rstpot1_2482,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_235
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2 : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1_2483,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_rstpot1_2484,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_834
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_rstpot1_2485,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_rstpot1_2486,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_371
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_rstpot1_2487,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_rstpot1_2488,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot1_2489,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot1_2490,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_1054
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot1_2491,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_rstpot1_2492,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_349
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1_2493,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1_2494,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1_2495,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1418
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_2496,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1381
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_2497,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1587
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1_2498,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_1363
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_2499,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1361
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_2500,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1362
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1_2501,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_1366
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_2502,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1625
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1_2503,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1690
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1_2504,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1696
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o_SW0_SW0 : LUT6
    generic map(
      INIT => X"AAA2FFE2AAA2FFF3"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1450,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1339,
      O => N212
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o_SW0_SW1 : LUT6
    generic map(
      INIT => X"FFFF333354551011"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1450,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG7_1339,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      O => N213
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_END_OF_TX1 : LUT6
    generic map(
      INIT => X"080008000A000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14581_SW2 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      O => N218
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_glue_rst : LUT4
    generic map(
      INIT => X"FFA2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_WFBOT_OR_95_o_678,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_glue_rst_2379
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_glue_rst : LUT5
    generic map(
      INIT => X"AAAAAA2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1059,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_ENABLE_1056,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_2_glue_rst_2325
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_WFBOT_OR_95_o_SW1 : LUT6
    generic map(
      INIT => X"77005F0000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_ENABLE_404,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => N220
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_WFBOT_OR_95_o : LUT6
    generic map(
      INIT => X"FFFF8800FFFF8880"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I4 => N220,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_WFBOT_OR_95_o_678
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv1 : LUT6
    generic map(
      INIT => X"5555555555555554"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_PWR_37_o_MUX_634_o1 : LUT5
    generic map(
      INIT => X"11011000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_CRS_967,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_PWR_37_o_MUX_634_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o_SW0 : LUT3
    generic map(
      INIT => X"81"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      O => N222
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o : LUT6
    generic map(
      INIT => X"00FF00FF04BF00FF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      I2 => N213,
      I3 => N212,
      I4 => N222,
      I5 => N136,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_DV_REG6_RX_ERR_REG6_OR_326_o_1438
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_PRE_FALSE_CARR_FLAG2_SW1 : LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG5(1),
      O => N224
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_463_o1 : LUT6
    generic map(
      INIT => X"4044404440444444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_EXT_1450,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG5,
      I4 => N224,
      I5 => N136,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_RX_ERR_REG5_END_EXT_AND_463_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN13_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1059,
      O => N228
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN2 : LUT6
    generic map(
      INIT => X"0000000001000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_2170,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_2171,
      I5 => N228,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER3_SW0 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1_2595,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => N233
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER3_SW1 : LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => N234
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1764_inv1 : LUT6
    generic map(
      INIT => X"FF00FF00FF07FB03"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER1_2151,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_ER,
      I3 => N233,
      I4 => N234,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1764_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv15_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1313,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      O => N236
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv15_SW1 : LUT5
    generic map(
      INIT => X"FFFFAABA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1313,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MAX_FRAME_ENABLE_HELD_1308,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_FRAME_1376,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      O => N237
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv2 : LUT6
    generic map(
      INIT => X"FFFF80007FFF0000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv13_2246,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv14_2247,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv11_2244,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv12_2245,
      I4 => N236,
      I5 => N237,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_glue_set : LUT5
    generic map(
      INIT => X"000030BA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_ER_REG1_2131,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv1,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_ER_TO_PHY_glue_set_2410
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_glue_rst : LUT4
    generic map(
      INIT => X"00CA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Result(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156_1807,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_glue_rst_2401
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_7_glue_set : LUT5
    generic map(
      INIT => X"333B000A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_7_glue_set_2411
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_6_glue_set : LUT5
    generic map(
      INIT => X"333B000A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_6_glue_set_2412
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_5_glue_set : LUT5
    generic map(
      INIT => X"333B000A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_5_glue_set_2413
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_4_glue_set : LUT5
    generic map(
      INIT => X"F3FBF0FA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_4_glue_set_2414
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_3_glue_set : LUT5
    generic map(
      INIT => X"F3FBF0FA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_3_glue_set_2415
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_2_glue_set : LUT5
    generic map(
      INIT => X"F3FBF0FA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_2_glue_set_2416
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_1_glue_set : LUT5
    generic map(
      INIT => X"F3FBF0FA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_1_glue_set_2417
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_0_glue_set : LUT5
    generic map(
      INIT => X"F3FBF0FA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TXD_REG1(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TXD_TO_PHY_0_glue_set_2418
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_glue_set : LUT5
    generic map(
      INIT => X"FF00FF8A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv1,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_PREAMBLE_AND_428_o_2110,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_FORCE_QUIET,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_TO_PHY_glue_set_2419
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_rstpot1 : LUT4
    generic map(
      INIT => X"00FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_1_next_rx_state_1_OR_9_o_0,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tlast_rstpot
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_643_o3_SW0 : LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(25),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(24),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(31),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      O => N239
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_rstpot : LUT5
    generic map(
      INIT => X"2F222022"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_1626,
      I1 => N241,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_HALF_DUPLEX_HELD_1302,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_rstpot_2465
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT51 : LUT6
    generic map(
      INIT => X"0000AA6600000A06"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT21 : LUT5
    generic map(
      INIT => X"00660006"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT31 : LUT6
    generic map(
      INIT => X"00006A6A0000006A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT41 : LUT5
    generic map(
      INIT => X"00A50021"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT91 : LUT6
    generic map(
      INIT => X"00AA000A00660006"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT81_1592,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_set : LUT6
    generic map(
      INIT => X"F0F0F0F0FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_ce_2361,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      I5 => N243,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_set_2362
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n149221 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_1691,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_371,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14922
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID1 : LUT5
    generic map(
      INIT => X"08080800"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT111 : LUT4
    generic map(
      INIT => X"5554"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mmux_GMII_TXD_7_GND_43_o_mux_9_OUT11
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT911_SW1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      O => N245
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv : LUT6
    generic map(
      INIT => X"FF50FF55FFDCFFDD"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I2 => N245,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I4 => N168,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_1604
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_rstpot_2520,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_0 : FD
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_0_rstpot_2521,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_glue_set : LUT4
    generic map(
      INIT => X"BBB0"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg1_2049,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_300,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_296,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rxstatsaddressmatch_glue_set_2409
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_glue_set : LUT6
    generic map(
      INIT => X"05040404CDCCCCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_JUMBO_FRAMES_HELD_1313,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1622,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv1,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n02133_2243,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0260_inv,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_glue_set_2386
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_glue_set : LUT4
    generic map(
      INIT => X"80FA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_400,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_EARLY,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CAPTURE_401,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_glue_set_2324
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG2,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG3_1344,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_rstpot1_2493
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG5,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_rstpot1_2495
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1466_SW1 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_943,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_942,
      O => N249
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_glue_set : LUT6
    generic map(
      INIT => X"0F0F0F0F0C0C0C0E"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => N249,
      I4 => N34,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_EXCESSIVE_COLLISIONS_AND_156_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_glue_set_2359
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1438_SW1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      O => N251
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_glue_set : LUT6
    generic map(
      INIT => X"5555555554555454"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_942,
      I2 => N251,
      I3 => N16,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_EXCESSIVE_COLLISIONS_AND_156_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_glue_set_2371
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_RXD_REG_7_INV_643_o5_SW0 : LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(29),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(28),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      O => N253
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_val1 : LUT6
    generic map(
      INIT => X"FFFF10F0FFFFF0F0"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_1837,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => N196,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mcount_DATA_COUNT_val
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n13961_SW0 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_ENABLE_1056,
      O => N257
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_glue_set : LUT6
    generic map(
      INIT => X"FFFFFFFF08000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1059,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1,
      I4 => N257,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_4_glue_set_2327
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n13961_SW1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_ENABLE_1056,
      O => N259
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_glue_rst : LUT6
    generic map(
      INIT => X"AAAAAA2AAAAAAAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_MAX_FRAME_LENGTH(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_VLAN_EN_1059,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I3 => N259,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN1,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_MAX_3_glue_rst_2326
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_rstpot1 : LUT6
    generic map(
      INIT => X"000000010F0E0F0F"
    )
    port map (
      I0 => N218,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable12,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      I4 => N261,
      I5 => N262,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_rstpot1_2485
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst_SW0 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => N264
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst_SW1 : LUT4
    generic map(
      INIT => X"ABEF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      O => N265
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst_SW2 : LUT6
    generic map(
      INIT => X"FF0CFF3F55045515"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I5 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => N266
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst : LUT6
    generic map(
      INIT => X"FFFFFFFFEFE02F20"
    )
    port map (
      I0 => N265,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_DATA_VALID_IN_AND_184_o1,
      I3 => N264,
      I4 => N266,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_EXCESSIVE_COLLISIONS_AND_156_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_glue_rst_2365
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT61 : LUT6
    generic map(
      INIT => X"0000AAA500002221"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I2 => N164,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT7 : LUT6
    generic map(
      INIT => X"0000AAA500002221"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I2 => N272,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT411,
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_4 : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_4_rstpot_2533,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_3 : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_3_rstpot_2534,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_glue_set : LUT5
    generic map(
      INIT => X"2AFF2A2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_1621,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXTENSION_FIELD_REG_1627,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_glue_set_2387
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_4_rstpot : LUT3
    generic map(
      INIT => X"09"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_4_rstpot_2533
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_3_rstpot : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_MASKED_3_rstpot_2534
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_glue_set : LUT6
    generic map(
      INIT => X"775F775F775F5F5F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o,
      I2 => N274,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv2_2153,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_glue_set_2343
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_0_rstpot : LUT6
    generic map(
      INIT => X"FF99FFF9FFCCFFFC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I5 => N276,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_0_rstpot_2521
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1527_SW1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      O => N278
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable101 : LUT6
    generic map(
      INIT => X"FFFFFFFFDDDFDDDD"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1057,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => N36,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7),
      I4 => N278,
      I5 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable10
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_1_rstpot_2538,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_0 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_0_rstpot_2539,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv1 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_ER,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1911_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_1_rstpot : LUT4
    generic map(
      INIT => X"84AA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_NORMAL_COUNT_xor_3_11,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_1_rstpot_2538
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1060,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut_2540
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_cy : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o,
      DI => NlwRenamedSig_OI_N1,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut_2540,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_l1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut1 : LUT5
    generic map(
      INIT => X"FFFFA8FF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_JUMBO_EN_1060,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut1_2542
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_cy1 : MUXCY
    port map (
      CI => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_14_FRAME_MAX_14_equal_66_o_l1,
      DI => N0,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set_lut1_2542,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_glue_set
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_2 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_2_rstpot_2543,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3_PWR_21_o_MUX_14_o,
      Q => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R2_286,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R3_288
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3_PWR_21_o_MUX_14_o,
      Q => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R2_290,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R3_292
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_glue_set : LUT6
    generic map(
      INIT => X"F444444444444444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1736_inv,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_glue_set_2368
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_glue_set : LUT6
    generic map(
      INIT => X"2022FFFF20222022"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_UNDERRUN_OUT,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1704_inv,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_glue_set_2376
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_cst1,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1895_inv,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Result(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT_2_rstpot_2478
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_18_Q : LUT4
    generic map(
      INIT => X"8ADF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(18),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_9_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(18)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      O => N295
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_glue_set : LUT6
    generic map(
      INIT => X"AAA8FFFFAAA8AAA8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14922,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1809_inv,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_920,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_glue_set_2352
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_set : LUT6
    generic map(
      INIT => X"AAAAAAAAAAAABAAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_ce_2344,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(10),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15082_2180,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n15081_2179,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(11),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DEFER_COUNT_DONE_glue_set_2345
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_rstpot1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_TX_EN_DELAY_400,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_NUMBER_OF_BYTES_rstpot1_2482
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_BROADCAST,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DST_ADDR_MULTI_MATCH_1018,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VECTOR_2_rstpot1_2483
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0238_inv1_SW0 : LUT5
    generic map(
      INIT => X"EA404040"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FIRST_FRAME_1621,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(9),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXTENSION_FIELD_REG_1627,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_REG(9),
      O => N241
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_6_Q : LUT4
    generic map(
      INIT => X"028A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1728_inv,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1440_738,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_glue_set_2370
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1420_741,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_glue_set_2380
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_1659,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_two_byte_tx_OR_38_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_glue_set_2390
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_glue_set : LUT5
    generic map(
      INIT => X"EEFECCFC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14501_2158,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_glue_set_2366
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_0_glue_rst : LUT3
    generic map(
      INIT => X"06"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156_1807,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_0_glue_rst_2400
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_1_glue_rst : LUT4
    generic map(
      INIT => X"006A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0200_inv_1792,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0156_1807,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_1_glue_rst_2402
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_rstpot : LUT6
    generic map(
      INIT => X"00AA002200FA0032"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT10,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I5 => N303,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_rstpot_2520
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_glue_set : LUT6
    generic map(
      INIT => X"88808880FFFF8880"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_COL_780,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_ER_IN_965,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN_966,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_933,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1764_inv,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_EARLY_COL_glue_set_2360
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set : LUT6
    generic map(
      INIT => X"FF04040404040404"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1778,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00811,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_glue_set_2398
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set : LUT6
    generic map(
      INIT => X"04040404FF040404"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_BAD_FRAME_INT_347,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_1777,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_n00811,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GND_27_o_DATA_7_equal_8_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_OPCODE_INT_glue_set_2399
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_glue_ce_SW0 : LUT6
    generic map(
      INIT => X"0000E000EEEEEEEE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      O => N305
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv1_SW0 : LUT6
    generic map(
      INIT => X"FFFAFFFAFFFAFFFB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_PREAMBLE_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      O => N307
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv1 : LUT6
    generic map(
      INIT => X"20200000FF20FFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2_2125,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_GMII_TX_EN_REG1_2130,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I5 => N307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_next_tx_state_3_tx_state_3_OR_24_o3_SW0 : LUT5
    generic map(
      INIT => X"FFFFAA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I2 => tx_axis_mac_tvalid,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_1650,
      O => N309
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(13),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(13),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_13_glue_set_2328
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(12),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_12_glue_set_2329
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(11),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(11),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_11_glue_set_2330
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(10),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_10_glue_set_2331
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(9),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_9_glue_set_2332
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(8),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_8_glue_set_2333
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_7_glue_set_2334
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_6_glue_set_2335
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_5_glue_set_2336
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_4_glue_set_2337
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_3_glue_set_2338
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_2_glue_set_2339
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_1_glue_set_2340
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set : LUT5
    generic map(
      INIT => X"CCFACCCC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_0(14),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_SCSH_JAM_AND_386_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BYTE_COUNT_1_0_glue_set_2341
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_glue_set_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CLIENT_FRAME_DONE_936,
      O => N312
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_glue_set : LUT6
    generic map(
      INIT => X"AA08AA08BB19AA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_STATUS_VALID,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot,
      I5 => N312,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_glue_set_2342
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_CONTROL_11_1 : LUT6
    generic map(
      INIT => X"0000200000000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN12_2171,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_VLAN11_2170,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(1),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LEN(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_CONTROL
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_rstpot1 : LUT6
    generic map(
      INIT => X"4440400044444444"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_fsmfake0(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_2085,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316,
      I5 => N208,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_mac_tvalid_rstpot
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_3_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12),
      O => N316
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set : LUT6
    generic map(
      INIT => X"AA2AFF3FAA2AAA2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_1_2302,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT_15_GND_31_o_equal_8_o_15_Q,
      I3 => N316,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_REG_1971,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_glue_set_2405
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_0_Q : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_1_Q : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_2_Q : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_3_Q : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_0_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_4_Q : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_0_Q : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_0_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_1_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In2 : LUT5
    generic map(
      INIT => X"FFFFA2AA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_In2_2270
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1859_inv3_SW0 : LUT4
    generic map(
      INIT => X"FFFB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_898,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      O => N274
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_ce : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_ce_2361
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14151 : LUT6
    generic map(
      INIT => X"0000000020202200"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_CRS_967,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I5 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1415
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o1 : LUT6
    generic map(
      INIT => X"0000E000EEEEEEEE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETSCSH_941,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_OVER_512_898,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_MIFG_AND_267_o1_2166
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT911_SW4 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(5),
      O => N272
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_5_Q : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_1_Q : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_1_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_2_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_2_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_0_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_2_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_3_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_3_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_1_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_3_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_4_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_0_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_4_Q : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_2_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_4_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_5_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_1_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_5_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_3_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_5_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_6_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_2_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_6_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_4_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_6_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_7_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_505_o1 : LUT5
    generic map(
      INIT => X"20000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1590,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_LT_CHECK_HELD_1310,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_48_o_RXD_7_equal_9_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_505_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_VLAN_MATCH_1_GND_48_o_MUX_1052_o11 : LUT6
    generic map(
      INIT => X"F444044404440444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_GND_48_o_RXD_7_equal_9_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_VLAN_MATCH_1_GND_48_o_MUX_1052_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_0_rstpot : LUT6
    generic map(
      INIT => X"00DF00FFFF00FF00"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_in,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG2_2125,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_COL_REG1_2111,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_TX_EN_REG1_2132,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_0_rstpot_2539
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14581_SW3 : LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL,
      O => N243
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1891_inv11_SW0 : LUT6
    generic map(
      INIT => X"5553333355553333"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_924,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1756_inv,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL,
      O => N261
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1891_inv11_SW1 : LUT6
    generic map(
      INIT => X"5555333555553333"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_924,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1756_inv,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL,
      O => N262
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_n0224_inv_SW2 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I2 => N168,
      O => N276
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_7_Q : LUT4
    generic map(
      INIT => X"028A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(7),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_1_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_8_Q : LUT4
    generic map(
      INIT => X"028A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(8),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_2_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_9_Q : LUT5
    generic map(
      INIT => X"082A5D7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_3_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(9),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_10_Q : LUT5
    generic map(
      INIT => X"082A5D7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_4_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(10),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_1_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_2_rstpot : LUT5
    generic map(
      INIT => X"A9AAFFAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0198_inv,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_NORMAL_COUNT_xor_3_11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT_2_rstpot_2543
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_glue_set : LUT4
    generic map(
      INIT => X"FF02"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1454,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_glue_set_2363
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_glue_set : LUT6
    generic map(
      INIT => X"FFFFFFFF00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1448,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_glue_set_2367
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot : LUT5
    generic map(
      INIT => X"0000FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I2 => N305,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0150_1808,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_2481
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1842_inv1_SW0 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_1047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_CRS_967,
      O => N320
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_glue_rst : LUT6
    generic map(
      INIT => X"00000000FFFF8AAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_901,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I3 => N320,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_PWR_37_o_MUX_634_o,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1415,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_glue_rst_2347
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14191_SW0 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      O => N328
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_glue_rst : LUT6
    generic map(
      INIT => X"FFF0FFF02220AAA0"
    )
    port map (
      I0 => N328,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TX_EN,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_900,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_QUIET_901,
      I5 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_glue_rst_2346
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_glue_set : LUT6
    generic map(
      INIT => X"FFFFFFFF00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_943,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1434_740,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_glue_set_2372
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_rstpot_SW0 : LUT6
    generic map(
      INIT => X"7F7F7FFF7F7F7F7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I5 => N168,
      O => N303
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT_2_11 : MUXF7
    port map (
      I0 => N332,
      I1 => N333,
      S => N36,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT_2_1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT_2_11_F : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF5557"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1057,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => N332
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_GND_37_o_sub_12_OUT_2_11_G : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DELAY(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_IFG_DEL_EN_1057,
      O => N333
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set : LUT6
    generic map(
      INIT => X"0100010001000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FALSE_CARR_FLAG_1304,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_FLAG_1305,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG6_1340,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_1411,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_EXT_FIELD_glue_set_2384
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_rstpot : LUT6
    generic map(
      INIT => X"FFFFAAAEAAAEAAAE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_RETRANSMIT_372,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_1666,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd7_1656,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd5_1657,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_end_rstpot_2480
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set : LUT5
    generic map(
      INIT => X"11111000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_1361,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_1362,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1379,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_300,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1300,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_glue_set_2382
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_rstpot : LUT4
    generic map(
      INIT => X"A8AC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_rstpot_2479
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_glue_set : LUT4
    generic map(
      INIT => X"44F4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_902,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_LATE_COLLISION_glue_set_2348
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_glue_set : LUT4
    generic map(
      INIT => X"44F4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN2_920,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_919,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_SUCCESS_glue_set_2351
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set : LUT5
    generic map(
      INIT => X"0808AA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_ENABLE_REG_1314,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG7_1342,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_2385
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_glue_set : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_reg_2051,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_2030,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pause_match_glue_set_2406
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_glue_set : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_reg_2050,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_2029,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_special_pause_match_glue_set_2407
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_glue_set : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_byte_match_2056,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_2031,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcast_match_glue_set_2408
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_rstpot : LUT5
    generic map(
      INIT => X"44444044"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd2_2079,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_BAD_FRAME_INT_317,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_VALID_INT_316,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_GOOD_FRAME_INT_318,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_rx_axi_shim_rx_state_FSM_FFd1_rstpot_2475
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_rstpot1 : LUT4
    generic map(
      INIT => X"2220"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_VALID_1379,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_VALIDATE_REQUIRED_1300,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_300,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_FINAL_rstpot1_2492
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1 : LUT5
    generic map(
      INIT => X"44400400"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG6_1343,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_1415,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_SRC_ADDRESS_FIELD_rstpot1_2494
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_glue_set : LUT6
    generic map(
      INIT => X"FFFF800080008000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tlast_reg_1665,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd6_1651,
      I3 => tx_axis_mac_tvalid,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_1659,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_1658,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_glue_set_2388
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_glue_set_SW1 : LUT6
    generic map(
      INIT => X"F444444444444444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_1049,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      O => N334
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_glue_set : LUT6
    generic map(
      INIT => X"2022FFFF20222022"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd3_388,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd1_386,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM2_TX_STATE_FSM_FFd2_387,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I5 => N334,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_glue_set_2378
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_SW1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFDFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(6),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(5),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_ERR_REG1_1341,
      O => N336
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set : LUT6
    generic map(
      INIT => X"AAAAAAAA00000800"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG1(2),
      I4 => N336,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_glue_set_2383
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_glue_set_SW1 : LUT6
    generic map(
      INIT => X"0000000002002200"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_GOOD_943,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_BAD_942,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_TX_EN_IN_966,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL,
      O => N338
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_glue_set : LUT6
    generic map(
      INIT => X"5555555500010000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETST_939,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      I5 => N338,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_glue_set_2369
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_glue_rst : LUT6
    generic map(
      INIT => X"FFFF8AFFFFFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_glue_rst_2354
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_glue_set_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => tx_axis_mac_tuser(0),
      I1 => tx_axis_mac_tvalid,
      O => N340
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_glue_set : LUT6
    generic map(
      INIT => X"00404040AAEAEAEA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663,
      I1 => N340,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tlast_tx_mac_tvalid_OR_21_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_glue_set_2393
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set : LUT5
    generic map(
      INIT => X"55551000"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STATUS_VALID,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I4 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_0_glue_set_2397
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_rstpot1 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_rstpot1_2486
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1 : LUT5
    generic map(
      INIT => X"11111000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1418,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1587,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_rstpot1_2497
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_904,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_STOP_MAX_PKT_glue_set_2349
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_930,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_glue_set_2357
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_931,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SLOT_TIME_REACHED_glue_set_2358
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_rstpot1 : LUT5
    generic map(
      INIT => X"44400400"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_834,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED2_900,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DEFERRED_rstpot1_2484
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_0_glue_set : LUT3
    generic map(
      INIT => X"F6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_13_1203,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_14_1202,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_prbs_1_SHIFT_DATA_0_glue_set_2381
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot : LUT4
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_HALF_DUPLEX_406,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_rstpot_2457
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_rstpot : LUT6
    generic map(
      INIT => X"FFFFFFFDAAAAAAA8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FCS_1418,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_298,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_299,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filter_match_0_301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_297,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_1303,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_MATCH_FRAME_INT_rstpot_2459
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_rstpot : LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_2032,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg2_2057,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_resync_promiscuous_mode_data_sync2,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_rstpot_2469
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_rstpot : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I1 => tx_axis_mac_tvalid,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_rstpot_2471
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_rstpot : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => tx_axis_mac_tvalid,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd3_1650,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_rstpot_2472
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_rstpot : LUT4
    generic map(
      INIT => X"2220"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_srl16_reg2_2048,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_promiscuous_mode_sample_2032,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_address_match_2033,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_filtered_data_valid_rstpot_2474
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_rstpot1_2487
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_rstpot1_2488
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1377,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1630,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_LENGTH_TYPE_ERR_rstpot1_2498
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1623,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_STATISTICS_VALID_rstpot1_2501
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_duplex_data_sync2,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_tx_enable_data_sync2,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_rstpot1_2503
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_duplex_data_sync2,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_sync_rx_enable_data_sync2,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_rstpot1_2504
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_glue_set : LUT4
    generic map(
      INIT => X"FF02"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_glue_set_2355
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot_SW0 : LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      O => N344
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot : LUT6
    generic map(
      INIT => X"2A0A20003B0A3100"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DEST_ADDRESS_FIELD_1416,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I2 => N344,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_1581,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_broadcastaddressmatch_299,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_MULTICAST_MATCH_rstpot_2464
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_glue_set : LUT6
    generic map(
      INIT => X"66F644F4FFFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst1_1659,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_burst2_1658,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_1660,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_336,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I5 => N346,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_glue_set_2389
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_glue_set_SW1 : LUT4
    generic map(
      INIT => X"AA80"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIN_PKT_LEN_REACHED_930,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      O => N348
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_glue_set : LUT6
    generic map(
      INIT => X"4440444055554440"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => N348,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_glue_set_2374
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_glue_set_SW0 : LUT5
    generic map(
      INIT => X"FDFFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I4 => tx_axis_mac_tlast,
      O => N350
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_glue_set : LUT6
    generic map(
      INIT => X"00202020FFFF2020"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_336,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I4 => tx_axis_mac_tvalid,
      I5 => N350,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_glue_set_2391
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_glue_set_SW0 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_mac_tready_reg_1667,
      I1 => tx_axis_mac_tuser(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      O => N352
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_glue_set : LUT6
    generic map(
      INIT => X"0010001055550010"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_1662,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_OUT_312,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_gate_tready_1669,
      I5 => N352,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_underrun_glue_set_2392
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1623,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1622,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_1626,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      O => N354
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1 : LUT6
    generic map(
      INIT => X"0000000001000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1625,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1624,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1630,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631,
      I5 => N354,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_GOOD_FRAME_rstpot1_2500
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_glue_set_SW1 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      O => N356
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_glue_set : LUT6
    generic map(
      INIT => X"4444444444444F44"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS,
      I1 => N356,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_glue_set_2364
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_glue_set_SW1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_944,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_FAIL_932,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_OK_940,
      O => N358
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_glue_set : LUT6
    generic map(
      INIT => X"FFFF5755FFFF0200"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_CRC_MODE_964,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FCS_2454,
      I4 => N358,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n14301,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_SCSH_glue_set_2373
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_glue_set_SW0 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_COUNT(2),
      O => N360
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_glue_set : LUT6
    generic map(
      INIT => X"FFFFFFFF00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I5 => N360,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_glue_set_2377
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot1_SW1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(4),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(6),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(7),
      O => N362
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot1 : LUT6
    generic map(
      INIT => X"0001000100010000"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_COUNT(1),
      I3 => N362,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ETIFG_938,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_937,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IFG_REACHED_rstpot1_2489
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot_SW0 : LUT4
    generic map(
      INIT => X"FF57"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_pauseaddressmatch_298,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_specialpauseaddressmatch_297,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      O => N364
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot : LUT6
    generic map(
      INIT => X"101010101010DC10"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1585,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_1584,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1,
      I4 => N364,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_ENABLE_rstpot_2461
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_SW0 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FCS_ERR_1624,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_FRAME_LEN_ERR_1630,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_MAX_LENGTH_ERR_1622,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_ERR_1626,
      O => N366
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1 : LUT6
    generic map(
      INIT => X"0202000202020202"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_INHIBIT_FRAME_1623,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_EXCEEDED_MIN_LEN_1631,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_1625,
      I5 => N366,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_BAD_FRAME_rstpot1_2499
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_glue_set : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_903,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_EXCESSIVE_COLLISIONS_glue_set_2350
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_1818,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_HELD_glue_set_2404
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot1 : LUT5
    generic map(
      INIT => X"10541010"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_1055,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_DATA_VALID_OUT,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_DA_rstpot1_2491
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_glue_set : LUT5
    generic map(
      INIT => X"0808FF08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MAX_PKT_LEN_REACHED_929,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TX_947,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CFL_946,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1704_inv,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_glue_set_2375
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_SW0 : LUT5
    generic map(
      INIT => X"84210000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(30),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(27),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => N253,
      O => N368
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1 : LUT6
    generic map(
      INIT => X"2222022022222222"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_CRC_FIELD_1412,
      I1 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FCS_CHECK_CALC(26),
      I4 => N239,
      I5 => N368,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_CRC_ENGINE_ERR_rstpot1_2502
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot_SW0 : LUT5
    generic map(
      INIT => X"90000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o1,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o12_2237,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_MATCH_GND_48_o_MUX_1004_o11_2236,
      O => N370
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot : LUT6
    generic map(
      INIT => X"000099F0000000F0"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_1380,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_DAT_FIELD_1413,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      I5 => N370,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_MATCH_rstpot_2460
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_rstpot_SW1 : LUT6
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_n1795_inv1_2162,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_COL,
      O => N372
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_rstpot : LUT6
    generic map(
      INIT => X"0CFF00FF08AA00AA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_924,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BURST_START_923,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PRE_948,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I5 => N372,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_PRE_DELAY_rstpot_2470
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_7_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_5_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_8_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_6_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_9_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_7_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_8_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_11_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_9_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_10_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_17_Q : LUT5
    generic map(
      INIT => X"F7F7A2F7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(17),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(8),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(17)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_11_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(11),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv1 : LUT4
    generic map(
      INIT => X"F444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_RX_DV_REG_1582,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0436_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_14_Q : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut_12_Q : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER_lut(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(10),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(11),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(12),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(13),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mmux_COUNT_SET_GND_31_o_MUX_237_o11_2300,
      O => N374
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot : LUT6
    generic map(
      INIT => X"44F4444444044444"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_STATUS_INT_1695,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_1694,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I5 => N374,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_COUNT_SET_rstpot_2468
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_3_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_7_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_8_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_4_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_8_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_9_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_PREAMBLE_FIELD_AND_531_o_inv1 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_PREAMBLE_FIELD_AND_531_o_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_5_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_9_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_10_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_6_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_10_Q : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_10_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_11_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(11),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(11),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_7_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_11_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(11),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_12_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_8_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(8)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_12_Q : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(12),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_12_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_13_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(13),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o_inv1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_JAM_OR_286_o_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_9_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(9)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut_13_Q : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DEFER_COUNT(13),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_DEFER_COUNT_lut(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_13_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(13),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_14_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(14),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable241 : LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I3 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Reset_OR_DriverANDClockEnable24
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_n0461_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_n0183_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut_10_Q : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EN_ER_COUNT(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CDS_949,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_IDL_950,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_EN_ER_COUNT_lut(10)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut_14_Q : LUT3
    generic map(
      INIT => X"2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_FRAME_COUNTER(14),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mcount_FRAME_COUNTER_lut(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut_15_Q : LUT5
    generic map(
      INIT => X"51555D55"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_PAUSE_COUNT(15),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_REQ_TO_TX_1699,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_GOOD_FRAME_IN_TX_REG_1964,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_sync_good_rx_data_sync2,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_PAUSE_VALUE_TO_TX(15),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_Mcount_PAUSE_COUNT_lut(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT11 : LUT5
    generic map(
      INIT => X"EFEE4544"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(31),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT21 : LUT5
    generic map(
      INIT => X"EFEE4544"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(30),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT31 : LUT5
    generic map(
      INIT => X"EFEE4544"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(29),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT41 : LUT5
    generic map(
      INIT => X"EFEE4544"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(28),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT11 : LUT3
    generic map(
      INIT => X"AB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT21 : LUT3
    generic map(
      INIT => X"AB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT31 : LUT3
    generic map(
      INIT => X"AB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT41 : LUT3
    generic map(
      INIT => X"AB"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT51 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT61 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT71 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_GND_37_o_DATA_REG_1_7_mux_83_OUT81 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_1(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_TRANSMIT_1046,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_PREAMBLE_1034,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_GND_37_o_DATA_REG_1_7_mux_83_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT51 : LUT5
    generic map(
      INIT => X"888D8888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(27),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(4)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT61 : LUT5
    generic map(
      INIT => X"888D8888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(26),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(5)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT71 : LUT5
    generic map(
      INIT => X"888D8888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(25),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(6)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mmux_DATA_REG_OUT81 : LUT5
    generic map(
      INIT => X"888D8888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRC_1044,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_CRCGEN_CALC(24),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_EXTENSION_370,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_DATA_REG_3(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_GMII_TXD(7)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT17 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT21 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(10),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_10_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT81 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_1_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT91 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT101 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_3_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT111 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(4),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT121 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT131 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(6),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_6_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT141 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(7),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT151 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(8),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_8_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Mmux_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT161 : LUT5
    generic map(
      INIT => X"FF8FF888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE(9),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_TYPE_15_PWR_56_o_mux_2_OUT_9_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_345_o1 : LUT5
    generic map(
      INIT => X"888888F8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CRC_COMPUTE_1378,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_DATA_1419,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_END_FRAME_2466,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_SFD_FLAG_CRC_COMPUTE_OR_345_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_38_o1 : LUT6
    generic map(
      INIT => X"FFFFFFFF777FF7FF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_DATA_VALID_968,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_945,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_COF_SEEN_925,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_END_OF_TX_INV_38_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_xor_1_11 : LUT6
    generic map(
      INIT => X"0000F88FF88F0000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_xor_0_11 : LUT5
    generic map(
      INIT => X"55414141"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut_2_1 : LUT5
    generic map(
      INIT => X"AA828282"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut_1_1 : LUT5
    generic map(
      INIT => X"AA828282"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut_0_1 : LUT5
    generic map(
      INIT => X"AA828282"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_load_count_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_2_11 : LUT6
    generic map(
      INIT => X"7878007800780078"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter2
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_1_11 : LUT5
    generic map(
      INIT => X"66060606"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter1
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_0_11 : LUT4
    generic map(
      INIT => X"4055"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(0),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_NORMAL_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(2),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_rstpot : LUT4
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => tx_axis_mac_tlast,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd1_1653,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd8_1652,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_rstpot_2467
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set : LUT6
    generic map(
      INIT => X"F7F7F7F7F7000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ENABLE_REG_1690,
      I4 => pause_req,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_1816,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_REQ_INT_glue_set_2403
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_rstpot : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_sync_update_data_sync2,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_2046,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_update_pause_ad_sync_reg_rstpot_2473
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot1 : LUT6
    generic map(
      INIT => X"4040004040000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_HALF_DUPLEX_1058,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_INT_BURSTING_417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_CONTROL_1828,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_IN_PIPE_rstpot1_2490
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_11_Q : LUT5
    generic map(
      INIT => X"082A5D7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_5_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(11),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_2_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(11)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_12_Q : LUT5
    generic map(
      INIT => X"082A5D7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_6_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(12),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_3_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(12)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_13_Q : LUT5
    generic map(
      INIT => X"082A5D7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_7_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(13),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_4_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(13)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_15_Q : LUT5
    generic map(
      INIT => X"082A5D7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_9_Q,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(15),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_6_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(15)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_16_Q : LUT4
    generic map(
      INIT => X"8ADF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(16),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_7_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(16)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv2 : LUT5
    generic map(
      INIT => X"FFFF5554"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_EXTENSION_REG1_2126,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(0),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_JAM_EXTENSION_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_Mcount_JAM_EXTENSION_COUNT_xor_2_11,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_GMII_MII_TX_GEN_n0204_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_LATE_COL_SAVED_AND_285_o1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_935,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_EXCESSIVE_COLLISIONS,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COL_SAVED_859,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_LATE_COL_SAVED_AND_285_o
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_4_11 : LUT6
    generic map(
      INIT => X"C6000000C6C6C6C6"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter4
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_12 : LUT5
    generic map(
      INIT => X"8F00008F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_DATA_VALID_EARLY_INT_1301,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_DV_REG1_1345,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_rx_data_valid_reg1_2047,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter_xor_3_11,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_counter(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mcount_counter3
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_PAUSE_VECTOR_1_1 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_ADD_CONTROL_FRAME_346,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_ENABLE_REG_1696,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_PAUSE_REQ_INT_1778,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_GOOD_FRAME_INT_348,
      O => rx_statistics_vector(23)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_SW1 : LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(2),
      I3 => N295,
      O => N376
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot : LUT6
    generic map(
      INIT => X"FFEAFFC05540FFC0"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_1377,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I5 => N376,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_TYPE_PACKET_rstpot_2462
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In_SW1 : LUT6
    generic map(
      INIT => X"AA2AFF3FAA2AAA2A"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_INT_TX_END_OF_TX,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_AVAIL_IN_REG_1838,
      O => N378
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In : LUT4
    generic map(
      INIT => X"EA40"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_1839,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_ACK_INT_1837,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd2_1793,
      I3 => N378,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_STATE_COUNT_FSM_FFd1_In_1794
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot_SW1 : LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_MATCH_1585,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(3),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LENGTH_FIELD_LT_CHECK_DISABLE_AND_501_o1,
      O => N380
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot : LUT6
    generic map(
      INIT => X"02220AAACEEE0AAA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_1578,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_SFD_FLAG_1307,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1417,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I5 => N380,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_CONTROL_FRAME_INT_rstpot_2463
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_SW1 : LUT4
    generic map(
      INIT => X"FEFA"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(5),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RXD_REG7(7),
      I3 => N158,
      O => N382
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1 : LUT6
    generic map(
      INIT => X"0444044454440444"
    )
    port map (
      I0 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_1381,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_LEN_FIELD_1414,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_FIELD_CONTROL(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_LESS_THAN_256_1590,
      I5 => N382,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_PADDED_FRAME_rstpot1_2496
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut_14_Q : LUT6
    generic map(
      INIT => X"8808AA2ADD5DFF7F"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_WFBOT_934,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_TIME_REACHED_1048,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_BOC_Q(8),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_BACK_OFF_COUNT(14),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_BACK_OFF_TIME_5_Q,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_BACK_OFF_COUNT_lut(14)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_glue_set : LUT5
    generic map(
      INIT => X"11110010"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_COL_371,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_REG_STATUS_VALID_922,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_UNDERRUN_INT_1691,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1817,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_921,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_TX_UNDERRUN_glue_set_2353
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_glue_set_SW0 : LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_early_deassert_1661,
      I1 => tx_axis_mac_tlast,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd2_1649,
      I3 => tx_axis_mac_tvalid,
      O => N346
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT81 : LUT5
    generic map(
      INIT => X"0A020501"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_IFG_REG_1628,
      I2 => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_IFG_1277,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_Mmux_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT81_1592,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_CHECKER_SLOT_LENGTH_CNTR_9_GND_49_o_mux_9_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1_Q,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_2_1_2579
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1 : FD
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_rstpot_2481,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_MUX_CONTROL_1_2580
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_glue_set_2362,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_JAM_1_2595
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1 : FDR
    port map (
      C => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_glue_set_2366,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_MIFG_1_2596
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_0_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_0_dpot_2582
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_1_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER1,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_1_dpot_2583
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_2_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(2),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER2,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_2_dpot_2584
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_3_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER3,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_3_dpot_2585
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_4_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(4),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER4,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_4_dpot_2586
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_5_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(5),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER5,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_5_dpot_2587
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_6_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(6),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER6,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_6_dpot_2588
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_7_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(7),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER7,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_7_dpot_2589
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_8_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(8),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER8,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_8_dpot_2590
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_9_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(9),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER9,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_9_dpot_2591
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_10_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(10),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER10,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_10_dpot_2592
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_11_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(11),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER11,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_11_dpot_2593
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_dpot : LUT6
    generic map(
      INIT => X"AABBAA88ABBBA888"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER(12),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd1_1191,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_INT_BURST_OVER_420,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_Mcount_BURST_COUNTER12,
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_GND_40_o_equal_2_o,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_BURST_COUNTER_12_dpot_2594
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1 : FDR
    port map (
      C => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_glue_set_2385,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_RX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_RX_SM_PREAMBLE_1_2597
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT83 : MUXF7
    port map (
      I0 => N384,
      I1 => N385,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count_2_pause_addr_7_wide_mux_27_OUT_7_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT83_F : LUT6
    generic map(
      INIT => X"FD75B931EC64A820"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I2 => rx_mac_config_vector(47),
      I3 => rx_mac_config_vector(63),
      I4 => rx_mac_config_vector(55),
      I5 => rx_mac_config_vector(39),
      O => N384
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_Mmux_load_count_2_pause_addr_7_wide_mux_27_OUT83_G : LUT5
    generic map(
      INIT => X"FBEA5140"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_addr_filter_top_address_filter_inst_load_count(0),
      I2 => rx_mac_config_vector(79),
      I3 => rx_mac_config_vector(71),
      I4 => rx_mac_config_vector(39),
      O => N385
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_glue_set : MUXF7
    port map (
      I0 => N386,
      I1 => N387,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd10_1654,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_glue_set_2394
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_glue_set_F : LUT5
    generic map(
      INIT => X"FFFF0444"
    )
    port map (
      I0 => N309,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_336,
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_state_FSM_FFd4_1655,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_two_byte_tx_1664,
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_1660,
      O => N386
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_tx_data_valid_glue_set_G : LUT5
    generic map(
      INIT => X"FFFF0010"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_ignore_packet_1663,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_no_burst_1668,
      I2 => tx_axis_mac_tvalid,
      I3 => tx_axis_mac_tuser(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_G_AXI_SHIM_tx_axi_shim_force_assert_1660,
      O => N387
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT74 : MUXF7
    port map (
      I0 => N388,
      I1 => N389,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_2_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT74_F : LUT5
    generic map(
      INIT => X"64202020"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT7,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT71_2276,
      O => N388
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT74_G : LUT6
    generic map(
      INIT => X"0101000101000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(2),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(10),
      O => N389
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT144 : MUXF7
    port map (
      I0 => N390,
      I1 => N391,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_5_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT144_F : LUT5
    generic map(
      INIT => X"64202020"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT14,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT141_2278,
      O => N390
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT144_G : LUT6
    generic map(
      INIT => X"0101000101000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(5),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(13),
      O => N391
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT124 : MUXF7
    port map (
      I0 => N392,
      I1 => N393,
      S => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT_4_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT124_F : LUT5
    generic map(
      INIT => X"64202020"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT12,
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT121_2280,
      O => N392
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_Mmux_DATA_COUNT_4_GND_28_o_wide_mux_25_OUT124_G : LUT6
    generic map(
      INIT => X"0101000101000000"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(1),
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(3),
      I2 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(2),
      I3 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_DATA_COUNT(0),
      I4 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_SAMPLE(4),
      I5 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_TX_PAUSE_VALUE_HELD(12),
      O => N393
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_lut_0_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_LATE_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_LATE_COUNT_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut_0_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_FRAME_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mcount_FRAME_COUNT_lut(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_lut_0_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_COUNTER(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_Madd_DATA_COUNTER_14_GND_48_o_add_6_OUT_lut_0_Q
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_NO_0_1_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(2),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_NO_1_1_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(3),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(1)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_NO_2_1_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(4),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(2)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_NO_3_1_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_ATTEMPT_COUNT(5),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_INT_RETRY(3)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_0_inv1_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_FSM_FFd2_1192,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_TX_STATE_0_inv
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Mcount_DATA_COUNT_xor_0_11_INV_0 : INV
    port map (
      I => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_DATA_COUNT(0),
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_FLOW_RX_Result(0)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_CORE_DOES_HD_TX_SM3_n0081_inv1_cepot
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => NlwRenamedSig_OI_N1,
      A2 => N0,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => tx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_5_Q,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_2608,
      Q15 => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_Q15_UNCONNECTED
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131 : FDE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_Mshreg_PREAMBLE_PIPE_13_2608,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131_2609
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mshreg_STATISTICS_VECTOR_22 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_N1,
      A1 => NlwRenamedSig_OI_N1,
      A2 => NlwRenamedSig_OI_N1,
      A3 => NlwRenamedSig_OI_N1,
      CE => N0,
      CLK => rx_axi_clk,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_FRAME_DECODER_DATA_WITH_FCS_1587,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mshreg_STATISTICS_VECTOR_22_2610,
      Q15 => NLW_U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mshreg_STATISTICS_VECTOR_22_Q15_UNCONNECTED
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR_22 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_Mshreg_STATISTICS_VECTOR_22_2610,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_RXGEN_STATISTICS_VECTOR(22)
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift1 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => N0,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift1_2611
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift2 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift1_2611,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift2_2612
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift3 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift2_2612,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift3_2613
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift4 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift3_2613,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift4_2614
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift5 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift4_2614,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift5_2615
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift6 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift5_2615,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift6_2616
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift7 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift6_2616,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift7_2617
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_131_2609,
      I1 => U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4_shift7_2617,
      O => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311_2618
    );
  U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13 : FDRE
    port map (
      C => tx_axi_clk,
      CE => N0,
      D => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_1311_2618,
      R => NlwRenamedSig_OI_U0_trimac_top_TRI_SPEED_TRIMAC_INST_SYNC_TX_RESET_I_R4,
      Q => U0_trimac_top_TRI_SPEED_TRIMAC_INST_TXGEN_TX_SM1_PREAMBLE_PIPE_13_Q
    );

end STRUCTURE;

-- synthesis translate_on