-- VHDL Entity atlys.dio_cmos_mbh.symbol
--
-- Created:
--          by - warren.warren (mbb)
--          at - 10:59:35 03/29/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;

entity dio_cmos_mbh is
   port(
      clk            : in     std_logic;
      clk160         : in     std_logic;
      clk_io_i       : in     std_logic;
      idelay_cal_i   : in     std_logic;
      --idelay_ce_o   : out    std_logic_vector (71 downto 0);
      --idelay_inc_o  : out    std_logic;
      --idelay_zero_o : out    std_logic_vector (71 downto 0);
      idelay_ctl_i   : in     t_idelay_ctl;
      iserdes_strb_i : in     std_logic;
      rawsigs_i      : in     std_logic_vector (15 downto 0);
      -- registers
      reg            : in     t_reg_bus;
      rst            : in     std_logic;
      strobe40_i     : in     std_logic;
      tlu_busy       : in     std_logic;
      tlu_rst        : in     std_logic;
      tlu_tclk       : in     std_logic;
      tlu_trig       : in     std_logic;
      tog20_i        : in     std_logic;
      idelay_busy_o  : out    std_logic;
      rx_link4x_o    : out    slv4_array (15 downto 0);
      v_nio          : inout  std_logic_vector (20 downto 1);
      v_pio          : inout  std_logic_vector (20 downto 1)
   );

-- Declarations

end dio_cmos_mbh ;

--
-- VHDL Architecture atlys.dio_cmos_mbh.struct
--
-- Created:
--          by - warren.warren (mbb)
--          at - 20:11:10 05/14/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library atlys;
use atlys.pkg_atlys_itsdaq.all;

library hsio;
use hsio.pkg_core_globals.all;

library unisim;
use unisim.VCOMPONENTS.all;


architecture struct of dio_cmos_mbh is

   -- Architecture declarations

   -- Internal signal declarations
   signal HI           : std_ulogic;
   signal LO           : std_logic;
   signal bco20_mode   : std_logic;
   signal bco_ddr      : std_logic;
   signal bco_ddr_q    : std_logic;
   signal bco_en       : std_logic;
   signal bco_inv      : std_logic;
   signal ck           : std_logic;
   signal ckfast       : std_logic;
   signal clkn         : std_logic;
   signal clkn160      : std_logic;
   signal dclk_en      : std_logic;
   signal dclk_inv     : std_logic;
   signal dclk_inv_n   : std_logic;
   signal dclk_mode40  : std_logic;
   signal ddro         : std_logic_vector(15 downto 0);
   signal idelay_busy  : std_logic_vector(23 downto 0);
   signal rx_strm_o    : std_logic_vector(47 downto 0);
   signal selected_bco : std_logic;
   signal ser_in       : std_logic_vector(15 downto 0);
   signal tog20q       : std_logic;
   signal tog20q2      : std_logic;


attribute KEEP : string;
--attribute KEEP of reg_control_i : signal is "true";
--attribute KEEP of reg_com_enable_i : signal is "true";
--attribute KEEP of dbg_sig_o : signal is "true";
--attribute KEEP of sink_sig_o : signal is "true";

   -- Component Declarations
   component iserdes2_dly_unit
   generic (
      LINK_ID : integer := 0
   );
   port (
      clk               : in     std_logic ;
      clk_io_i          : in     std_logic ;
      idelay_cal_i      : in     std_logic ;
      --idelay_ce_o   : out    std_logic_vector (71 downto 0);
      --idelay_inc_o  : out    std_logic;
      --idelay_zero_o : out    std_logic_vector (71 downto 0);
      idelay_ctl_i      : in     t_idelay_ctl ;
      iserdes_strb_i    : in     std_logic ;
      rst               : in     std_logic ;
      serdata_i         : in     std_logic ;
      idelay_busy_o     : out    std_ulogic ;
      serdata_delayed_o : out    std_logic ;
      serx4_o           : out    std_logic_vector (3 downto 0)
   );
   end component;
   component IBUFDS
   generic (
      CAPACITANCE      : string  := "DONT_CARE";
      DIFF_TERM        : boolean := FALSE;
      DQS_BIAS         : string  := "FALSE";
      IBUF_DELAY_VALUE : string  := "0";
      IBUF_LOW_PWR     : boolean := TRUE;
      IFD_DELAY_VALUE  : string  := "AUTO";
      IOSTANDARD       : string  := "DEFAULT"
   );
   port (
      I  : in     std_ulogic;
      IB : in     std_ulogic;
      O  : out    std_ulogic
   );
   end component;
   component OBUFDS
   generic (
      CAPACITANCE : string := "DONT_CARE";
      IOSTANDARD  : string := "DEFAULT";
      SLEW        : string := "SLOW"
   );
   port (
      I  : in     std_ulogic;
      O  : out    std_ulogic;
      OB : out    std_ulogic
   );
   end component;
   component ODDR2
   generic (
      DDR_ALIGNMENT : string := "NONE";
      INIT          : bit    := '0';
      SRTYPE        : string := "SYNC"
   );
   port (
      C0 : in     std_ulogic;
      C1 : in     std_ulogic;
      CE : in     std_ulogic  := 'H';
      D0 : in     std_ulogic;
      D1 : in     std_ulogic;
      R  : in     std_ulogic  := 'L';
      S  : in     std_ulogic  := 'L';
      Q  : out    std_ulogic
   );
   end component;
   component m_power
   port (
      hi : out    std_logic ;
      lo : out    std_logic
   );
   end component;


begin
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 3 eb3
   -- eb1 1
   bco_en <= '1'; --reg(R_COM_ENA)(B_BCO_EN);
   bco_inv <= reg(R_COM_ENA)(B_BCO_INV);
   bco20_mode <= reg(R_COM_ENA)(B_BCO20_MODE);

   tog20q <= tog20_i when rising_edge(clk);
   tog20q2 <= tog20q when rising_edge(clk);

   selected_bco <= tog20q2 when (bco20_mode='1') else
                    strobe40_i;

   bco_ddr <= selected_bco when (bco_inv = '1') else
              not selected_bco;

   --needs q to phase shift for ddr
   bco_ddr_q <= bco_ddr when rising_edge(clk);


   -- HDL Embedded Text Block 6 eb6
   -- eb2 2
   dclk_en <= reg(R_COM_ENA)(B_DCLK_EN);
   dclk_inv <= reg(R_COM_ENA)(B_DCLK_INV);


   dclk_mode40 <= reg(R_CONTROL)(CTL_DCLK40_MODE);

   -- HDL Embedded Text Block 8 eb8
   idelay_busy_o <=
     '0' when (idelay_busy = 0) else
     '1';


   -- ModuleWare code(v1.12) for instance 'U_10' of 'buff'
   v_nio(16) <= tlu_rst;

   -- ModuleWare code(v1.12) for instance 'U_11' of 'buff'
   v_pio(16) <= tlu_busy;

   -- ModuleWare code(v1.12) for instance 'U_14' of 'buff'
   v_nio(15) <= tlu_tclk;

   -- ModuleWare code(v1.12) for instance 'U_15' of 'buff'
   v_pio(15) <= tlu_trig;

   -- ModuleWare code(v1.12) for instance 'U_16' of 'buff'
   v_pio(20) <= tlu_trig;

   -- ModuleWare code(v1.12) for instance 'U_17' of 'buff'
   v_nio(20) <= tlu_tclk;

   -- ModuleWare code(v1.12) for instance 'U_18' of 'buff'
   v_nio(19) <= ddro(RS_VMB_DIGINJ);

   -- ModuleWare code(v1.12) for instance 'U_19' of 'buff'
   v_pio(19) <= ddro(RS_VMB_SIN);

   -- ModuleWare code(v1.12) for instance 'U_20' of 'buff'
   v_nio(18) <= ddro(RS_VMB_LOADREG);

   -- ModuleWare code(v1.12) for instance 'U_21' of 'buff'
   v_pio(18) <= ddro(RS_VMB_CK2);

   -- ModuleWare code(v1.12) for instance 'U_22' of 'buff'
   v_nio(17) <= ddro(RS_VMB_CK1);

   -- ModuleWare code(v1.12) for instance 'U_23' of 'buff'
   v_pio(17) <= ddro(RS_VMB_SHIFTENB);

   -- ModuleWare code(v1.12) for instance 'U_32' of 'buff'
   ser_in(I_VMB_PL332) <= v_pio(7);

   -- ModuleWare code(v1.12) for instance 'U_36' of 'buff'
   ser_in(I_VMB_PL371) <= v_pio(12);

   -- ModuleWare code(v1.12) for instance 'U_37' of 'buff'
   ser_in(I_VMB_PL342) <= v_nio(7);

   -- ModuleWare code(v1.12) for instance 'U_38' of 'buff'
   ser_in(I_VMB_PL341) <= v_pio(8);

   -- ModuleWare code(v1.12) for instance 'U_39' of 'buff'
   ser_in(I_VMB_PL331) <= v_nio(8);

   -- ModuleWare code(v1.12) for instance 'U_40' of 'buff'
   ser_in(I_VMB_PL351) <= v_pio(9);

   -- ModuleWare code(v1.12) for instance 'U_41' of 'buff'
   ser_in(I_VMB_PL352) <= v_nio(9);

   -- ModuleWare code(v1.12) for instance 'U_42' of 'buff'
   ser_in(I_VMB_PL372) <= v_nio(12);

   -- ModuleWare code(v1.12) for instance 'U_43' of 'buff'
   ser_in(I_VMB_PL373) <= v_pio(13);

   -- ModuleWare code(v1.12) for instance 'U_44' of 'buff'
   ser_in(I_VMB_SEROUT) <= v_nio(14);

   -- ModuleWare code(v1.12) for instance 'U_45' of 'buff'
   ser_in(I_VMB_HBCMOS) <= v_pio(14);

   -- ModuleWare code(v1.12) for instance 'U_46' of 'buff'
   ser_in(I_VMB_HBNORCMOS) <= v_nio(13);

   -- ModuleWare code(v1.12) for instance 'U_2' of 'inv'
   clkn <= not(clk);

   -- ModuleWare code(v1.12) for instance 'U_3' of 'inv'
   clkn160 <= not(clk160);

   -- ModuleWare code(v1.12) for instance 'U_4' of 'inv'
   dclk_inv_n <= not(dclk_inv);

   -- Instance port mappings.
   Uib2 : IBUFDS
      generic map (
         CAPACITANCE      => "DONT_CARE",
         DIFF_TERM        => TRUE,
         IBUF_DELAY_VALUE => "0",
         IFD_DELAY_VALUE  => "AUTO",
         IOSTANDARD       => "LVDS_25"
      )
      port map (
         O  => ser_in(I_VMB_OUT3),
         I  => v_pio(5),
         IB => v_nio(5)
      );
   Uib3 : IBUFDS
      generic map (
         CAPACITANCE      => "DONT_CARE",
         DIFF_TERM        => TRUE,
         IBUF_DELAY_VALUE => "0",
         IFD_DELAY_VALUE  => "AUTO",
         IOSTANDARD       => "LVDS_25"
      )
      port map (
         O  => ser_in(I_VMB_OUT4),
         I  => v_pio(6),
         IB => v_nio(6)
      );
   Uib4 : IBUFDS
      generic map (
         CAPACITANCE      => "DONT_CARE",
         DIFF_TERM        => TRUE,
         IBUF_DELAY_VALUE => "0",
         IFD_DELAY_VALUE  => "AUTO",
         IOSTANDARD       => "LVDS_25"
      )
      port map (
         O  => ser_in(I_VMB_OUT2),
         I  => v_pio(4),
         IB => v_nio(4)
      );
   Uib5 : IBUFDS
      generic map (
         CAPACITANCE      => "DONT_CARE",
         DIFF_TERM        => TRUE,
         IBUF_DELAY_VALUE => "0",
         IFD_DELAY_VALUE  => "AUTO",
         IOSTANDARD       => "LVDS_25"
      )
      port map (
         O  => ser_in(I_VMB_OUT1),
         I  => v_pio(3),
         IB => v_nio(3)
      );
   Uob0 : OBUFDS
      generic map (
         CAPACITANCE => "DONT_CARE",
         IOSTANDARD  => "LVDS_25"
      )
      port map (
         O  => v_pio(1),
         OB => v_nio(1),
         I  => ddro(RS_VMB_IN1)
      );
   Uob1 : OBUFDS
      generic map (
         CAPACITANCE => "DONT_CARE",
         IOSTANDARD  => "LVDS_25"
      )
      port map (
         O  => v_pio(2),
         OB => v_nio(2),
         I  => ddro(RS_VMB_IN2)
      );
   Uobbco : OBUFDS
      generic map (
         CAPACITANCE => "DONT_CARE",
         IOSTANDARD  => "LVDS_25"
      )
      port map (
         O  => v_pio(11),
         OB => v_nio(11),
         I  => ck
      );
   Uobdclk : OBUFDS
      generic map (
         CAPACITANCE => "DONT_CARE",
         IOSTANDARD  => "LVDS_25"
      )
      port map (
         O  => v_pio(10),
         OB => v_nio(10),
         I  => ckfast
      );
   Uoddrbco : ODDR2
      generic map (
         DDR_ALIGNMENT => "NONE",
         INIT          => '0',
         SRTYPE        => "SYNC"
      )
      port map (
         Q  => ck,
         C0 => clk,
         C1 => clkn,
         CE => HI,
         D0 => bco_ddr,
         D1 => bco_ddr_q,
         R  => rst,
         S  => LO
      );
   Uoddrdclk : ODDR2
      generic map (
         DDR_ALIGNMENT => "NONE",
         INIT          => '0',
         SRTYPE        => "SYNC"
      )
      port map (
         Q  => ckfast,
         C0 => clk160,
         C1 => clkn160,
         CE => HI,
         D0 => dclk_inv_n,
         D1 => dclk_inv,
         R  => rst,
         S  => LO
      );
   Umpower : m_power
      port map (
         hi => HI,
         lo => LO
      );

   gserin0: FOR i IN 0 TO 15 GENERATE
      gserin1: IF (C_LINKS_EN(i) = '1') GENERATE
         Uiserdesdly : iserdes2_dly_unit
            generic map (
               LINK_ID => i
            )
            port map (
               clk               => clk,
               clk_io_i          => clk_io_i,
               idelay_cal_i      => idelay_cal_i,
               idelay_ctl_i      => idelay_ctl_i,
               iserdes_strb_i    => iserdes_strb_i,
               rst               => rst,
               serdata_i         => ser_in(i),
               idelay_busy_o     => idelay_busy(i),
               serdata_delayed_o => open,
               serx4_o           => rx_link4x_o(i)
            );
      end generate gserin1;

      gserin2: IF (C_LINKS_EN(i) = '0') GENERATE

         -- ModuleWare code(v1.12) for instance 'U_33' of 'buff'
         idelay_busy(i) <= LO;
         -- HDL Embedded Text Block 1 eb1
         -- eb1 1
         rx_link4x_o(i) <= "0000";

      end generate gserin2;

   end generate gserin0;

   gdo2: FOR c IN 0 TO 15 GENERATE
      Uoddr1 : ODDR2
         generic map (
            DDR_ALIGNMENT => "NONE",
            INIT          => '0',
            SRTYPE        => "SYNC"
         )
         port map (
            Q  => ddro(c),
            C0 => clk,
            C1 => clkn,
            CE => HI,
            D0 => rawsigs_i(c),
            D1 => rawsigs_i(c),
            R  => rst,
            S  => LO
         );
   end generate gdo2;

end struct;