Generation Settings

Declarations

Ports:

clk            : std_logic
rst            : std_logic
strobe40_i     : std_logic
rawsigs_i      : std_logic_vector(15 downto 0)
l1r3_i         : std_logic
vm_pio         : std_logic_vector(20 DOWNTO 1)
vm_nio         : std_logic_vector(20 DOWNTO 1)
noise_i        : std_logic
--dbg_sig_o  : out    std_logic;
dbg_spare_o    : std_logic
--dbg_sig_o  : out    std_logic;
dbg_l1r3_o     : std_logic
--idelay_ce_o   : out    std_logic_vector (71 downto 0);
--idelay_inc_o  : out    std_logic;
--idelay_zero_o : out    std_logic_vector (71 downto 0);
idelay_ctl_i   : t_idelay_ctl
-- registers
reg            : t_reg_bus
coml0_i        : std_logic
--dbg_sig_o  : out    std_logic;
dbg_coml0_o    : std_logic
clk_io_i       : std_logic
idelay_cal_i   : std_logic
iserdes_strb_i : std_logic
idelay_busy_o  : std_logic
sck_i          : std_logic
sck_t_i        : std_logic
sda_tx_i       : std_logic
sda_rx_o       : std_logic
sda_t_i        : std_logic
rx_link4x_o    : slv4_array(15 downto 0)

Diagram Signals:

signal LO             : std_logic
signal bco            : std_logic
signal txsigs         : std_logic_vector(15 downto 0)
signal HI             : std_ulogic
signal ddro           : std_logic_vector(7 downto 0)
signal ser_in         : std_logic_vector(7 DOWNTO 4)
signal rx_strm_o      : std_logic_vector(47 downto 0)
signal bco_en         : std_logic
signal bco_ddr        : std_logic
signal bco_ddr_n      : std_logic
signal rawout_en      : std_logic
signal clkn           : std_logic
signal idelay_busy    : std_logic_vector(15 downto 0)
signal ser_in_atl_tmu : std_logic

Pre User:

Post User:

attribute KEEP : string;
--attribute KEEP of reg_control_i : signal is "true";
--attribute KEEP of reg_com_enable_i : signal is "true";
--attribute KEEP of dbg_sig_o : signal is "true";
--attribute KEEP of sink_sig_o : signal is "true";

Package List

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library atlys;
use atlys.pkg_atlys_itsdaq.all;

library hsio;
use hsio.pkg_core_globals.all;

library unisim;
use unisim.VCOMPONENTS.all;

Bundles