-- VHDL Entity atlys.dio_itsdaq_drv.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 11:00:12 03/29/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity dio_itsdaq_drv is port( clk : in std_logic; clk_io_i : in std_logic; coml0_i : in std_logic; idelay_cal_i : in std_logic; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl; iserdes_strb_i : in std_logic; l1r3_i : in std_logic; noise_i : in std_logic; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus; rst : in std_logic; sck_i : in std_logic; sck_t_i : in std_logic; sda_t_i : in std_logic; sda_tx_i : in std_logic; strobe40_i : in std_logic; --dbg_sig_o : out std_logic; dbg_coml0_o : out std_logic; --dbg_sig_o : out std_logic; dbg_l1r3_o : out std_logic; --dbg_sig_o : out std_logic; dbg_spare_o : out std_logic; idelay_busy_o : out std_logic; rx_link4x_o : out slv4_array (15 downto 0); sda_rx_o : out std_logic; vm_nio : inout std_logic_vector (20 downto 1); vm_pio : inout std_logic_vector (20 downto 1) ); -- Declarations end dio_itsdaq_drv ; -- -- VHDL Architecture atlys.dio_itsdaq_drv.struct -- -- Created: -- by - warren.warren (mbb) -- at - 20:11:10 05/14/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library atlys; use atlys.pkg_atlys_itsdaq.all; library hsio; use hsio.pkg_core_globals.all; library unisim; use unisim.VCOMPONENTS.all; architecture struct of dio_itsdaq_drv is -- Architecture declarations -- Internal signal declarations signal HI : std_ulogic; signal LO : std_logic; signal bco : std_logic; signal bco_ddr : std_logic; signal bco_ddr_n : std_logic; signal bco_en : std_logic; signal clkn : std_logic; signal ddro : std_logic_vector(7 downto 0); signal idelay_busy : std_logic_vector(15 downto 0); signal rawout_en : std_logic; signal rx_strm_o : std_logic_vector(47 downto 0); signal ser_in : std_logic_vector(7 downto 4); signal ser_in_atl_tmu : std_logic; signal txsigs : std_logic_vector(15 downto 0); attribute KEEP : string; --attribute KEEP of reg_control_i : signal is "true"; --attribute KEEP of reg_com_enable_i : signal is "true"; --attribute KEEP of dbg_sig_o : signal is "true"; --attribute KEEP of sink_sig_o : signal is "true"; -- Component Declarations component iserdes2_dly_unit generic ( LINK_ID : integer := 0 ); port ( clk : in std_logic ; clk_io_i : in std_logic ; idelay_cal_i : in std_logic ; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl ; iserdes_strb_i : in std_logic ; rst : in std_logic ; serdata_i : in std_logic ; idelay_busy_o : out std_ulogic ; serdata_delayed_o : out std_logic ; serx4_o : out std_logic_vector (3 downto 0) ); end component; component IBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; DIFF_TERM : boolean := FALSE; DQS_BIAS : string := "FALSE"; IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE; IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT" ); port ( I : in std_ulogic; IB : in std_ulogic; O : out std_ulogic ); end component; component OBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "DEFAULT"; SLEW : string := "SLOW" ); port ( I : in std_ulogic; O : out std_ulogic; OB : out std_ulogic ); end component; component ODDR2 generic ( DDR_ALIGNMENT : string := "NONE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port ( C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic := 'H'; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic := 'L'; S : in std_ulogic := 'L'; Q : out std_ulogic ); end component; component m_power port ( hi : out std_logic ; lo : out std_logic ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 1 eb1 prc_modes : process (rawout_en, reg, coml0_i, l1r3_i, txsigs) begin if (rawout_en = '1') then txsigs <= rawsigs_i; else txsigs(OD_COML0) <= coml0_i; txsigs(OD_L1R3) <= l1r3_i; txsigs(OD_SPARE) <= reg(R_CONTROL1)(CTL_DRV_SP0); --SCAN_EN txsigs(3) <= '0'; -- n/a txsigs(4) <= reg(R_CONTROL1)(CTL_DRV_DXOUT0); -- DXL txsigs(5) <= reg(R_CONTROL1)(CTL_DRV_DXOUT1); -- DXR txsigs(6) <= reg(R_CONTROL1)(CTL_DRV_DXOUT2); -- SDO_BC txsigs(7) <= reg(R_CONTROL1)(CTL_DRV_DXOUT3); -- SDO_CLK txsigs(15 downto 8) <= txsigs(7 downto 0); end if; end process; -- HDL Embedded Text Block 2 eb2 -- eb1 1 bco_en <= reg(R_COM_ENA)(B_BCO_EN); -- for compat reasons bco is inverted bco_ddr <= strobe40_i when (reg(R_COM_ENA)(B_BCO_INV) = '1') else not strobe40_i; -- HDL Embedded Text Block 4 eb4 rx_link4x_o(0) <= "0000"; -- 0 -- 1 rx_link4x_o(2) <= "0000"; -- 2 rx_link4x_o(3) <= "0000"; -- 3 -- 4 rx_link4x_o(5) <= "0000"; -- 5 rx_link4x_o(6) <= "0000"; -- 6 -- 7 rx_link4x_o(8) <= "0000"; -- 8 rx_link4x_o(9) <= "0000"; -- 9 --10 rx_link4x_o(11) <= "0000"; --11 rx_link4x_o(12) <= "0000"; --12 rx_link4x_o(13) <= "0000"; --13 rx_link4x_o(14) <= "0000"; --14 --15 -- HDL Embedded Text Block 5 eb5 -- eb5 5 -------------------------- --vm_pio(vibD15) <= tmu_data -- 42 D15P, vmIO20P --vm_nio(vibD15) <= tmu_data -- 41 D15M, vmIO20M vm_pio(vibD14) <= reg(R_DRV_CONF)( 8); -- rst_ext -- 40 D14P, vmIO19P vm_nio(vibD14) <= reg(R_DRV_CONF)( 7); -- tmu_coml0_swap -- 39 D14M, vmIO19M vm_pio(vibD13) <= sck_i; -- 38 D13P, vmIO18P vm_nio(vibD13) <= sck_t_i; -- 37 D13M, vmIO18M sda_rx_o <= vm_pio(vibD12); -- 36 D12P, vmIO17P vm_nio(vibD12) <= sda_tx_i; -- 35 D12M, vmIO17M vm_pio(vibD11) <= sda_t_i; -- 34 D11P, vmIO16P --vm_nio(vibD11) --vm_pio(vibD10) --vm_nio(vibD10) --vm_pio(vibD9) --vm_nio(vibD9) --vm_pio(vibD8) --vm_nio(vibD8) --vm_pio(vibD7) --vm_nio(vibD7) --vm_pio(vibD6) --vm_nio(vibD6) --vm_pio(vibD5) --vm_nio(vibD5) --vm_pio(vibD4) --vm_nio(vibD4) --vm_pio(vibD3) --vm_nio(vibD3) --vm_pio(vibD2) --vm_nio(vibD2) --vm_pio(vibD1) --vm_nio(vibD1) --vm_pio(vibD0) --vm_nio(vibD0) -- HDL Embedded Text Block 6 eb6 rawout_en <= reg(R_CONTROL1)(CTL_RAWOUT_EN); -- HDL Embedded Text Block 8 eb8 idelay_busy(0) <= '0'; --idelay_busy(1) <= '0'; -- DXIN0 idelay_busy(2) <= '0'; idelay_busy(3) <= '0'; --idelay_busy(4) <= '0'; -- DXIN1 idelay_busy(5) <= '0'; idelay_busy(6) <= '0'; --idelay_busy(7) <= '0'; -- DXIN2 idelay_busy(8) <= '0'; idelay_busy(9) <= '0'; --idelay_busy(10) <= '0'; -- DXIN3 idelay_busy(11) <= '0'; idelay_busy(12) <= '0'; idelay_busy(13) <= '0'; idelay_busy(14) <= '0'; --idelay_busy(15) <= '0'; -- TMU idelay_busy_o <= '0' when (idelay_busy = 0) else '1'; -- ModuleWare code(v1.12) for instance 'U_6' of 'buff' dbg_coml0_o <= txsigs(OD_COML0); -- ModuleWare code(v1.12) for instance 'U_7' of 'buff' dbg_l1r3_o <= txsigs(OD_L1R3); -- ModuleWare code(v1.12) for instance 'U_8' of 'buff' dbg_spare_o <= txsigs(OD_SPARE); -- ModuleWare code(v1.12) for instance 'U_0' of 'inv' bco_ddr_n <= not(bco_ddr); -- ModuleWare code(v1.12) for instance 'U_1' of 'inv' clkn <= not(clk); -- Instance port mappings. Uiserdesdly1 : iserdes2_dly_unit generic map ( LINK_ID => 1 ) port map ( clk => clk, clk_io_i => clk_io_i, idelay_cal_i => idelay_cal_i, idelay_ctl_i => idelay_ctl_i, iserdes_strb_i => iserdes_strb_i, rst => rst, serdata_i => ser_in(ID_DX0), idelay_busy_o => idelay_busy(1), serdata_delayed_o => open, serx4_o => rx_link4x_o(1) ); Uiserdesdly2 : iserdes2_dly_unit generic map ( LINK_ID => 15 ) port map ( clk => clk, clk_io_i => clk_io_i, idelay_cal_i => idelay_cal_i, idelay_ctl_i => idelay_ctl_i, iserdes_strb_i => iserdes_strb_i, rst => rst, serdata_i => ser_in_atl_tmu, idelay_busy_o => idelay_busy(15), serdata_delayed_o => open, serx4_o => rx_link4x_o(15) ); Uiserdesdly4 : iserdes2_dly_unit generic map ( LINK_ID => 4 ) port map ( clk => clk, clk_io_i => clk_io_i, idelay_cal_i => idelay_cal_i, idelay_ctl_i => idelay_ctl_i, iserdes_strb_i => iserdes_strb_i, rst => rst, serdata_i => ser_in(ID_DX1), idelay_busy_o => idelay_busy(4), serdata_delayed_o => open, serx4_o => rx_link4x_o(4) ); Uiserdesdly7 : iserdes2_dly_unit generic map ( LINK_ID => 7 ) port map ( clk => clk, clk_io_i => clk_io_i, idelay_cal_i => idelay_cal_i, idelay_ctl_i => idelay_ctl_i, iserdes_strb_i => iserdes_strb_i, rst => rst, serdata_i => ser_in(ID_DX2), idelay_busy_o => idelay_busy(7), serdata_delayed_o => open, serx4_o => rx_link4x_o(7) ); Uiserdesdly10 : iserdes2_dly_unit generic map ( LINK_ID => 10 ) port map ( clk => clk, clk_io_i => clk_io_i, idelay_cal_i => idelay_cal_i, idelay_ctl_i => idelay_ctl_i, iserdes_strb_i => iserdes_strb_i, rst => rst, serdata_i => ser_in(ID_DX3), idelay_busy_o => idelay_busy(10), serdata_delayed_o => open, serx4_o => rx_link4x_o(10) ); Uib : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in(ID_DX0), I => vm_pio(vibD1), IB => vm_nio(vibD1) ); Uib1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in(ID_DX1), I => vm_pio(vibD4), IB => vm_nio(vibD4) ); Uib2 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in(ID_DX2), I => vm_pio(vibD7), IB => vm_nio(vibD7) ); Uib3 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in(ID_DX3), I => vm_pio(vibD10), IB => vm_nio(vibD10) ); Uib5 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in_atl_tmu, I => vm_pio(vibD15), IB => vm_nio(vibD15) ); Uob0 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibCMD), OB => vm_nio(vibCMD), I => ddro(OD_COML0) ); Uob1 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibL1R), OB => vm_nio(vibL1R), I => ddro(OD_L1R3) ); Uob2 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibDRC), OB => vm_nio(vibDRC), I => ddro(OD_SPARE) ); Uob4 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibD0), OB => vm_nio(vibD0), I => ddro(OD_DX0) ); Uob5 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibD3), OB => vm_nio(vibD3), I => ddro(OD_DX1) ); Uob6 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibD6), OB => vm_nio(vibD6), I => ddro(OD_DX2) ); Uob7 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibD9), OB => vm_nio(vibD9), I => ddro(OD_DX3) ); Uobbco : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibBCO), OB => vm_nio(vibBCO), I => bco ); Uoddrbco : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => bco, C0 => clk, C1 => clkn, CE => HI, D0 => bco_ddr_n, D1 => bco_ddr, R => rst, S => LO ); Umpower : m_power port map ( hi => HI, lo => LO ); gdo2: FOR c IN 0 TO 7 GENERATE Uoddr1 : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => ddro(c), C0 => clk, C1 => clkn, CE => HI, D0 => txsigs(c), D1 => txsigs(c+8), R => rst, S => LO ); end generate gdo2; end struct;