Generation Settings

Declarations

Ports:

clk              : std_logic
rst              : std_logic
strobe40_i       : std_logic
dbg_com_o        : std_logic
dbg_l1r_o        : std_logic
dbg_reset_o      : std_logic
rawcom_en_com_i  : std_logic
rawcom_en_l1r_i  : std_logic
rawcom_en_rst_i  : std_logic
rawcom_i         : std_logic
com_i            : std_logic
l1r_i            : std_logic
reset_i          : std_logic
-- registers
reg              : t_reg_bus
strm_reg_i       : slv16_array(143 DOWNTO 0)
clk_io_i         : std_logic
iserdes_strb_i   : std_logic
--idelay_ce_o   : out    std_logic_vector (71 downto 0);
--idelay_inc_o  : out    std_logic;
--idelay_zero_o : out    std_logic_vector (71 downto 0);
idelay_ctl_i     : t_idelay_ctl
idelay_cal_i     : std_logic
vm_nio           : std_logic_vector(20 DOWNTO 1)
vm_pio           : std_logic_vector(20 DOWNTO 1)
rawsigs_i        : std_logic_vector(15 downto 0)
rx_link4x_o      : slv4_array(15 downto 0)
idelay_busy_o    : std_logic
tlu_tclk         : std_logic
tlu_trig         : std_logic
tlu_busy         : std_logic
tlu_rst          : std_logic

Diagram Signals:

signal LO               : std_logic
signal bco_en           : std_logic
signal dclk_en          : std_logic
signal dclk_inv         : std_logic
signal dclk_mode40      : std_logic
signal dclk_ddr_d1      : std_logic
signal dclk_ddr_d2      : std_logic
signal bco              : std_logic
signal com              : std_logic
signal dclk             : std_logic
signal l1r              : std_logic
signal reset            : std_logic
signal HI               : std_logic
signal com_in           : std_logic
signal rawcom_in        : std_logic
signal l1r_in           : std_logic
signal reset_in         : std_logic
signal rx_strm_o        : std_logic_vector(7 downto 0)
signal bco_ddr          : std_logic
signal bco_ddr_n        : std_logic
signal gendata0_i       : std_logic
signal gendata1_i       : std_logic
signal simdata1_i       : std_logic
signal simdata0_i       : std_logic
signal idelay_busy      : std_logic_vector(15 downto 0)
signal ser_in           : std_logic_vector(1 DOWNTO 0)
signal clkn             : std_logic
signal rawout_en        : std_logic
signal rx_link4x        : slv4_array(15 downto 0)
signal dbg_link_delayed : std_logic_vector(15 downto 0)
signal dbg_bco_en       : std_logic
signal dbg_bco          : std_logic
signal dbg_dclk         : std_logic
signal dbg_l1r          : std_logic
signal dbg_com          : std_logic
signal dbg_reset        : std_logic
signal dbg_oe           : std_logic
signal dbg_dclk_en      : std_logic
signal dbg_rx_link4x    : slv4_array(15 downto 0)

Pre User:

Post User:

attribute KEEP : string;
--attribute KEEP of reg_control_i : signal is "true";
--attribute KEEP of reg_com_enable_i : signal is "true";

Package List

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils;
use utils.pkg_types.all;
library hsio;
use hsio.pkg_core_globals.all;

library unisim;
use unisim.VCOMPONENTS.all;
library atlys;
use atlys.pkg_atlys_itsdaq.all;

Bundles