-- VHDL Entity atlys.dio_vib_idc.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 15:05:27 05/20/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity dio_vib_idc is port( clk : in std_logic; clk_io_i : in std_logic; com_i : in std_logic; idelay_cal_i : in std_logic; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl; iserdes_strb_i : in std_logic; l1r_i : in std_logic; rawcom_en_com_i : in std_logic; rawcom_en_l1r_i : in std_logic; rawcom_en_rst_i : in std_logic; rawcom_i : in std_logic; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus; reset_i : in std_logic; rst : in std_logic; strm_reg_i : in slv16_array (143 downto 0); strobe40_i : in std_logic; tlu_busy : in std_logic; tlu_rst : in std_logic; tlu_tclk : in std_logic; tlu_trig : in std_logic; dbg_com_o : out std_logic; dbg_l1r_o : out std_logic; dbg_reset_o : out std_logic; idelay_busy_o : out std_logic; rx_link4x_o : out slv4_array (15 downto 0); vm_nio : inout std_logic_vector (20 downto 1); vm_pio : inout std_logic_vector (20 downto 1) ); -- Declarations end dio_vib_idc ; -- -- VHDL Architecture atlys.dio_vib_idc.struct -- -- Created: -- by - warren.warren (mbb) -- at - 15:05:27 05/20/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; library unisim; use unisim.VCOMPONENTS.all; library atlys; use atlys.pkg_atlys_itsdaq.all; architecture struct of dio_vib_idc is -- Architecture declarations -- Internal signal declarations signal HI : std_logic; signal LO : std_logic; signal bco : std_logic; signal bco_ddr : std_logic; signal bco_ddr_n : std_logic; signal bco_en : std_logic; signal clkn : std_logic; signal com : std_logic; signal com_in : std_logic; signal dbg_bco : std_logic; signal dbg_bco_en : std_logic; signal dbg_com : std_logic; signal dbg_dclk : std_logic; signal dbg_dclk_en : std_logic; signal dbg_l1r : std_logic; signal dbg_link_delayed : std_logic_vector(15 downto 0); signal dbg_oe : std_logic; signal dbg_reset : std_logic; signal dbg_rx_link4x : slv4_array(15 downto 0); signal dclk : std_logic; signal dclk_ddr_d1 : std_logic; signal dclk_ddr_d2 : std_logic; signal dclk_en : std_logic; signal dclk_inv : std_logic; signal dclk_mode40 : std_logic; signal gen13data0_i : std_logic_vector(1 downto 0); signal gen13data1_i : std_logic_vector(1 downto 0); signal idelay_busy : std_logic_vector(15 downto 0); signal l1r : std_logic; signal l1r_in : std_logic; signal rawcom_in : std_logic; signal rawout_en : std_logic; signal reset : std_logic; signal reset_in : std_logic; signal rx_link4x : slv4_array(15 downto 0); signal ser_in : std_logic_vector(15 downto 0); signal sim13data0_i : std_logic_vector(1 downto 0); signal sim13data1_i : std_logic_vector(1 downto 0); attribute KEEP : string; --attribute KEEP of reg_control_i : signal is "true"; --attribute KEEP of reg_com_enable_i : signal is "true"; -- Component Declarations component iserdes2_dly_unit generic ( LINK_ID : integer := 0 ); port ( clk : in std_logic ; clk_io_i : in std_logic ; idelay_cal_i : in std_logic ; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl ; iserdes_strb_i : in std_logic ; rst : in std_logic ; serdata_i : in std_logic ; idelay_busy_o : out std_ulogic ; serdata_delayed_o : out std_logic ; serx4_o : out std_logic_vector (3 downto 0) ); end component; component four_phase port ( sig_i : in std_logic ; sig_o : out std_logic ; --dbg_sig_o : out std_logic; dbg_sig0_o : out std_logic ; -- sig_0_o : out std_logic; -- sig_90_o : out std_logic; -- sig_180_o : out std_logic; -- sig_270_o : out std_logic; sel_i : in std_logic_vector (1 downto 0); invert_i : in std_logic ; com_i : in std_logic ; com_en : in std_logic ; rst : in std_logic ; clk : in std_logic ); end component; component IBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; DIFF_TERM : boolean := FALSE; DQS_BIAS : string := "FALSE"; IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE; IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT" ); port ( I : in std_ulogic; IB : in std_ulogic; O : out std_ulogic ); end component; component OBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "DEFAULT"; SLEW : string := "SLOW" ); port ( I : in std_ulogic; O : out std_ulogic; OB : out std_ulogic ); end component; component ODDR2 generic ( DDR_ALIGNMENT : string := "NONE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port ( C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic := 'H'; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic := 'L'; S : in std_ulogic := 'L'; Q : out std_ulogic ); end component; component m_power port ( hi : out std_logic ; lo : out std_logic ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 2 eb2 dclk_en <= reg(R_COM_ENA)(B_DCLK_EN); dclk_inv <= reg(R_COM_ENA)(B_DCLK_INV); --dclk_inv_n <= not(reg(R_COM_ENA)(B_DCLK_INV)); dclk_mode40 <= reg(R_CONTROL)(CTL_DCLK40_MODE); dclk_ddr_d1 <= not(dclk_inv) when (dclk_mode40 = '0') else (strobe40_i xor dclk_inv); dclk_ddr_d2 <= dclk_inv when (dclk_mode40 = '0') else not (strobe40_i xor dclk_inv); -- HDL Embedded Text Block 4 eb4 bco_en <= reg(R_COM_ENA)(B_BCO_EN); -- for compat reasons bco is inverted bco_ddr <= strobe40_i when (reg(R_COM_ENA)(B_BCO_INV) = '1') else not strobe40_i; -- HDL Embedded Text Block 5 eb5 rx_link4x_o <= rx_link4x; -- HDL Embedded Text Block 6 eb6 -- eb5 5 -------------------------- dbg_oe <= reg(R_CONTROL)(CTL_DBG_EN); vm_pio(vibD15) <= dbg_bco; -- dbg_oe done at DDR vm_nio(vibD15) <= dbg_dclk; -- dbg_oe done at DDR vm_pio(vibD14) <= dbg_oe and dbg_com; vm_nio(vibD14) <= dbg_oe and dbg_l1r; vm_pio(vibD13) <= dbg_oe and tlu_busy; --dbg vm_nio(vibD13) <= dbg_oe and tlu_rst; --dbg vm_pio(vibD12) <= dbg_oe and tlu_trig; --dbg vm_nio(vibD12) <= dbg_oe and tlu_tclk; --dbg --vm_pio(vibD11) <= dbg_oe and --vm_nio(vibD11) <= dbg_oe and --vm_pio(vibD10) <= dbg_oe and --vm_nio(vibD10) <= dbg_oe and vm_pio(vibD9) <= dbg_oe and dbg_rx_link4x(1)(0); -- dbg vm_nio(vibD9) <= dbg_oe and dbg_rx_link4x(1)(2); -- dbg vm_pio(vibD8) <= dbg_oe and dbg_rx_link4x(0)(0); -- dbg vm_nio(vibD8) <= dbg_oe and dbg_rx_link4x(0)(2); -- dbg --vm_pio(vibD7) <= dbg_oe and --vm_nio(vibD7) <= dbg_oe and --vm_pio(vibD6) <= dbg_oe and --vm_nio(vibD6) <= dbg_oe and --vm_pio(vibD5) <= dbg_oe and dbg_link_delayed(2); --vm_nio(vibD5) <= dbg_oe and dbg_link_delayed(3); vm_pio(vibD4) <= dbg_oe and dbg_link_delayed(0); vm_nio(vibD4) <= dbg_oe and dbg_link_delayed(1); --vm_pio(vibD3) -- reserved for link in 3 --vm_nio(vibD3) -- diff n --vm_pio(vibD2) -- reserved for link in 2 --vm_nio(vibD2) -- diff n --vm_pio(vibD1) -- link in 1 (diff) --vm_nio(vibD1) -- diff n --vm_pio(vibD0) -- link in 0 (diff) --vm_nio(vibD0) -- diff n -- HDL Embedded Text Block 7 eb7 prc_modes : process (rawout_en, rawsigs_i, com_i, l1r_i, reset_i) begin if (rawout_en = '1') then com_in <= rawsigs_i(RS_ID0_COM); l1r_in <= rawsigs_i(RS_IDC_L1); reset_in <= rawsigs_i(RS_ID0_R3); else com_in <= com_i; l1r_in <= l1r_i; reset_in <= reset_i; end if; end process; -- HDL Embedded Text Block 8 eb8 rawout_en <= reg(R_CONTROL1)(CTL_RAWOUT_EN); -- HDL Embedded Text Block 9 eb9 idelay_busy_o <= '0' when (idelay_busy = 0) else '1'; -- HDL Embedded Text Block 10 eb10 dbg_rx_link4x <= rx_link4x; -- ModuleWare code(v1.12) for instance 'U_0' of 'and' dbg_bco_en <= dbg_oe and bco_en; -- ModuleWare code(v1.12) for instance 'U_1' of 'and' dbg_dclk_en <= dbg_oe and dclk_en; -- ModuleWare code(v1.12) for instance 'U_7' of 'buff' rawcom_in <= rawcom_i; -- ModuleWare code(v1.12) for instance 'U_36' of 'buff' dbg_l1r_o <= dbg_l1r; -- ModuleWare code(v1.12) for instance 'U_37' of 'buff' dbg_com_o <= dbg_com; -- ModuleWare code(v1.12) for instance 'U_38' of 'buff' dbg_reset_o <= dbg_reset; -- ModuleWare code(v1.12) for instance 'U_3' of 'inv' bco_ddr_n <= not(bco_ddr); -- ModuleWare code(v1.12) for instance 'U_5' of 'inv' clkn <= not(clk); -- Instance port mappings. Ufourphase0 : four_phase port map ( sig_i => com_in, sig_o => com, dbg_sig0_o => dbg_com, sel_i => reg(R_COM_ENA)(15 DOWNTO 14), invert_i => LO, com_i => rawcom_in, com_en => rawcom_en_com_i, rst => rst, clk => clk ); Ufourphase1 : four_phase port map ( sig_i => l1r_in, sig_o => l1r, dbg_sig0_o => dbg_l1r, sel_i => reg(R_COM_ENA)(15 DOWNTO 14), invert_i => LO, com_i => rawcom_in, com_en => rawcom_en_l1r_i, rst => rst, clk => clk ); Ufourphase2 : four_phase port map ( sig_i => reset_in, sig_o => reset, dbg_sig0_o => dbg_reset, sel_i => reg(R_COM_ENA)(15 DOWNTO 14), invert_i => reg(R_COM_ENA)(B_RST_INV), com_i => rawcom_in, com_en => rawcom_en_rst_i, rst => rst, clk => clk ); Uibd0 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in(0), I => vm_pio(vibD0), IB => vm_nio(vibD0) ); Uibd1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "LVDS_25" ) port map ( O => ser_in(1), I => vm_pio(vibD1), IB => vm_nio(vibD1) ); Uobbco : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibBCO), OB => vm_nio(vibBCO), I => bco ); Uobcom : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibCMD), OB => vm_nio(vibCMD), I => com ); Uobd2r : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibRST), OB => vm_nio(vibRST), I => reset ); Uobdrc : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibDRC), OB => vm_nio(vibDRC), I => dclk ); Uobl1r : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => vm_pio(vibL1R), OB => vm_nio(vibL1R), I => l1r ); Uoddrbcopp0 : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => bco, C0 => clk, C1 => clkn, CE => bco_en, D0 => bco_ddr, D1 => bco_ddr_n, R => rst, S => LO ); Uoddrdbgbco : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_bco, C0 => clk, C1 => clkn, CE => dbg_bco_en, D0 => bco_ddr, D1 => bco_ddr_n, R => rst, S => LO ); Uoddrdbgdck : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_dclk, C0 => clk, C1 => clkn, CE => dbg_dclk_en, D0 => dclk_ddr_d1, D1 => dclk_ddr_d2, R => rst, S => LO ); Uoddrdclkpp0 : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dclk, C0 => clk, C1 => clkn, CE => dclk_en, D0 => dclk_ddr_d1, D1 => dclk_ddr_d2, R => rst, S => LO ); Umpower : m_power port map ( hi => HI, lo => LO ); gserin1: FOR i IN 0 TO 1 GENERATE gserin2: IF (C_LINKS_EN(i) = '1') GENERATE Uiserdesdly3 : iserdes2_dly_unit generic map ( LINK_ID => i ) port map ( clk => clk, clk_io_i => clk_io_i, idelay_cal_i => idelay_cal_i, idelay_ctl_i => idelay_ctl_i, iserdes_strb_i => iserdes_strb_i, rst => rst, serdata_i => ser_in(i), idelay_busy_o => idelay_busy(i), serdata_delayed_o => dbg_link_delayed(i), serx4_o => rx_link4x(i) ); end generate gserin2; gserin3: IF (C_LINKS_EN(i) = '0') GENERATE -- HDL Embedded Text Block 3 eb3 rx_link4x(i) <= "0000"; -- ModuleWare code(v1.12) for instance 'U_33' of 'buff' idelay_busy(i) <= LO; -- ModuleWare code(v1.12) for instance 'U_35' of 'buff' dbg_link_delayed(i) <= LO; end generate gserin3; end generate gserin1; end struct;