Generation Settings

Declarations

Ports:

rst               : std_logic
clk               : std_logic
--idelay_ce_o   : out    std_logic_vector (71 downto 0);
--idelay_inc_o  : out    std_logic;
--idelay_zero_o : out    std_logic_vector (71 downto 0);
idelay_ctl_i      : t_idelay_ctl
serdata_i         : std_logic
clk_io_i          : std_logic
idelay_cal_i      : std_logic
iserdes_strb_i    : std_logic
idelay_busy_o     : std_ulogic
serx4_o           : std_logic_vector(3 downto 0)
serdata_delayed_o : std_logic

Diagram Signals:

signal idelay_inc        : std_logic
signal idelay_ce         : std_logic
signal HI                : std_logic
signal LO                : std_logic
signal strm_loop         : std_logic
signal idelay_rst        : std_logic

Pre User:

Post User:

Package List

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;

library unisim;
use unisim.all;

Bundles