-- VHDL Entity atlys.iserdes2_dly_unit.symbol
--
-- Created:
--          by - warren.warren (mbb)
--          at - 20:11:09 05/14/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;

entity iserdes2_dly_unit is
   generic(
      LINK_ID : integer := 0
   );
   port(
      clk               : in     std_logic;
      clk_io_i          : in     std_logic;
      idelay_cal_i      : in     std_logic;
      --idelay_ce_o   : out    std_logic_vector (71 downto 0);
      --idelay_inc_o  : out    std_logic;
      --idelay_zero_o : out    std_logic_vector (71 downto 0);
      idelay_ctl_i      : in     t_idelay_ctl;
      iserdes_strb_i    : in     std_logic;
      rst               : in     std_logic;
      serdata_i         : in     std_logic;
      idelay_busy_o     : out    std_ulogic;
      serdata_delayed_o : out    std_logic;
      serx4_o           : out    std_logic_vector (3 downto 0)
   );

-- Declarations

end iserdes2_dly_unit ;

--
-- VHDL Architecture atlys.iserdes2_dly_unit.struct
--
-- Created:
--          by - warren.warren (mbb)
--          at - 20:11:09 05/14/15
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;

library unisim;
use unisim.all;


architecture struct of iserdes2_dly_unit is

   -- Architecture declarations

   -- Internal signal declarations
   signal HI         : std_logic;
   signal LO         : std_logic;
   signal idelay_ce  : std_logic;
   signal idelay_inc : std_logic;
   signal idelay_rst : std_logic;
   signal strm_loop  : std_logic;


   -- Component Declarations
   component iserdes2_4b
   generic (
      -- width of the data for the system
      --sys_w               :     integer := 1;
      -- width of the data for the device
      dev_w : integer := 2
   );
   port (
      BITSLIP           : in     std_logic;
      DELAY_CLK         : in     std_logic;
      DELAY_DATA_CAL    : in     std_logic;
      DELAY_DATA_CE     : in     std_logic;
      DELAY_DATA_INC    : in     std_logic;
      IO_RESET          : in     std_logic;
      clk_fabric_i      : in     std_logic;
      clk_io_i          : in     std_logic;
      delay_rst_i       : in     std_logic;
      iserdes_strb_i    : in     std_logic;
      serdata_i         : in     std_logic;
      DELAY_BUSY        : out    std_logic;
      pardata_o         : out    std_logic_vector (dev_w-1 downto 0);
      serdata_delayed_o : out    std_logic
   );
   end component;
   component m_power
   port (
      hi : out    std_logic ;
      lo : out    std_logic
   );
   end component;


begin
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 2 eb2
   -- eb2 2
   idelay_rst <= idelay_ctl_i.zero(LINK_ID) or rst;
   idelay_ce <= idelay_ctl_i.ce(LINK_ID);
   idelay_inc <= idelay_ctl_i.inc;

   strm_loop <=  idelay_ctl_i.strm_loop(LINK_ID);


   -- Instance port mappings.
   Uiserdes : iserdes2_4b
      generic map (
         -- width of the data for the system
         --sys_w               :     integer := 1;
         -- width of the data for the device
         dev_w => 4
      )
      port map (
         serdata_i         => serdata_i,
         pardata_o         => serx4_o,
         serdata_delayed_o => serdata_delayed_o,
         DELAY_BUSY        => idelay_busy_o,
         DELAY_CLK         => clk,
         delay_rst_i       => idelay_rst,
         DELAY_DATA_CAL    => idelay_cal_i,
         DELAY_DATA_CE     => idelay_ce,
         DELAY_DATA_INC    => idelay_inc,
         BITSLIP           => LO,
         clk_io_i          => clk_io_i,
         iserdes_strb_i    => iserdes_strb_i,
         clk_fabric_i      => clk,
         IO_RESET          => rst
      );
   Umpower : m_power
      port map (
         hi => HI,
         lo => LO
      );

end struct;