-- VHDL Entity atlys.itsdaq_clk_rst.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 15:20:39 05/27/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; entity itsdaq_clk_rst is port( --#clockpinforAtlysrevCboard clk100_i : in std_logic; rst_top_o : out std_logic; rst1_o : out std_logic; rst2_o : out std_logic; clk40_o : out std_logic; ext_bco_i : in std_logic; rst_btn_ni : in std_logic; rst_no : out std_logic; clk_ext_sel_i : in std_logic; ext_por_no : out std_logic; strobe40_o : out std_logic; clk125_locked_o : out std_logic; clk125_o : out std_logic; iserdes_clk_o : out std_ulogic; is_clk_tdc_o : out std_logic; iserdes_strb_o : out std_logic; is_strb_tdc_o : out std_logic; clk80_o : out std_logic; clks_locked_o : out std_logic; s20_o : out std_logic; tog20_o : out std_logic; rst3_o : out std_logic; rst125_o : out std_ulogic; rst_top_125_o : out std_ulogic ); -- Declarations end itsdaq_clk_rst ; -- -- VHDL Architecture atlys.itsdaq_clk_rst.struct -- -- Created: -- by - warren.warren (mbb) -- at - 15:20:39 05/27/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library unisim; use unisim.VCOMPONENTS.all; use ieee.numeric_std.all; architecture struct of itsdaq_clk_rst is -- Architecture declarations -- Internal signal declarations signal clks_lckd_tdc_o : std_logic; signal pll12540_locked : std_logic; signal clk125 : std_logic; signal rst : std_logic; signal clk40i : std_logic; signal clk40i_nobufg : std_logic; signal clk40 : std_logic; signal clk80 : std_logic; signal clk320_nobufg : std_logic; signal clk160 : std_logic; signal pll_locked : std_logic; signal clks_locked : std_logic; signal ext_por : std_logic; signal clk40a : std_logic; signal clk40b : std_logic; signal clk80a : std_logic; signal clk80b : std_logic; signal clk160a : std_logic; signal clk160b : std_logic; signal clkn40a : std_logic; signal pll_rst : std_logic; signal pll640_locked : std_logic; signal clk640_nobufg : std_logic; -- Component Declarations component cg_pll_125_40 port ( CLK100_IN : in std_logic; RESET : in std_logic; CLK125 : out std_logic; CLK40 : out std_logic; LOCKED : out std_logic ); end component; component cg_pll_3208040 port ( CLK40_IN : in std_logic; RESET : in std_logic; CLK320 : out std_logic; CLK40 : out std_logic; CLK80 : out std_logic; LOCKED : out std_logic ); end component; component cg_pll_6408040 port ( CLK40_IN : in std_logic; RESET : in std_logic; CLK40 : out std_logic; CLK640 : out std_logic; CLK80 : out std_logic; LOCKED : out std_logic ); end component; component xilinx_reset generic ( PIPE_LEN : integer := 15 ); port ( clk : in std_ulogic ; ready_i : in std_logic ; reset_no : out std_ulogic ; reset_o : out std_ulogic ); end component; component BUFG port ( I : in std_ulogic; O : out std_ulogic ); end component; component BUFGMUX generic ( CLK_SEL_TYPE : string := "SYNC" ); port ( I0 : in std_ulogic := '0'; I1 : in std_ulogic := '0'; S : in std_ulogic := '0'; O : out std_ulogic := '0' ); end component; component BUFPLL generic ( DIVIDE : integer := 1; -- {1..8} ENABLE_SYNC : boolean := TRUE ); port ( GCLK : in std_ulogic; LOCKED : in std_ulogic; PLLIN : in std_ulogic; IOCLK : out std_ulogic; LOCK : out std_ulogic; SERDESSTROBE : out std_ulogic ); end component; component strobe40_gen port ( clk : in std_logic; clk40 : in std_logic; rst : in std_logic; s20_o : out std_logic; strobe40_o : out std_logic; tog20_o : out std_logic ); end component; begin -- ModuleWare code(v1.12) for instance 'U_1' of 'buff' -- ModuleWare code(v1.12) for instance 'U_3' of 'buff' -- ModuleWare code(v1.12) for instance 'U_4' of 'buff' -- ModuleWare code(v1.12) for instance 'U_5' of 'buff' -- ModuleWare code(v1.12) for instance 'U_6' of 'buff' clk125_locked_o <= pll12540_locked; -- ModuleWare code(v1.12) for instance 'U_7' of 'buff' clk125_o <= clk125; -- ModuleWare code(v1.12) for instance 'U_9' of 'buff' clks_locked_o <= clks_locked; -- ModuleWare code(v1.12) for instance 'U_10' of 'buff' clk40_o <= clk40; -- ModuleWare code(v1.12) for instance 'U_12' of 'buff' rst_top_o <= rst; -- ModuleWare code(v1.12) for instance 'U_15' of 'buff' clk80_o <= clk80; -- ModuleWare code(v1.12) for instance 'U_13' of 'inv' pll_rst <= not(pll12540_locked); -- Instance port mappings. Upll12540 : cg_pll_125_40 port map ( CLK100_IN => clk100_i, CLK125 => clk125, CLK40 => clk40i_nobufg, RESET => ext_por, LOCKED => pll12540_locked ); Upll3208040 : cg_pll_3208040 port map ( CLK40_IN => clk40i, CLK80 => clk80, CLK320 => clk320_nobufg, CLK40 => clk40, RESET => pll_rst, LOCKED => pll_locked ); Upll640 : cg_pll_6408040 port map ( CLK40_IN => clk40i, CLK80 => open, CLK640 => clk640_nobufg, CLK40 => open, RESET => pll_rst, LOCKED => pll640_locked ); Uxreset : xilinx_reset generic map ( PIPE_LEN => 15 ) port map ( clk => clk100_i, ready_i => rst_btn_ni, reset_no => ext_por_no, reset_o => ext_por ); Uxreset1 : xilinx_reset generic map ( PIPE_LEN => 7 ) port map ( clk => clk80, ready_i => clks_locked, reset_no => rst_no, reset_o => rst ); Uxreset2 : xilinx_reset generic map ( PIPE_LEN => 7 ) port map ( clk => clk80, ready_i => clks_locked, reset_no => open, reset_o => rst1_o ); Uxreset3 : xilinx_reset generic map ( PIPE_LEN => 7 ) port map ( clk => clk80, ready_i => clks_locked, reset_no => open, reset_o => rst2_o ); Uxreset4 : xilinx_reset generic map ( PIPE_LEN => 7 ) port map ( clk => clk80, ready_i => clks_locked, reset_no => open, reset_o => rst3_o ); Uxreset5 : xilinx_reset generic map ( PIPE_LEN => 15 ) port map ( clk => clk125, ready_i => pll12540_locked, reset_no => open, reset_o => rst125_o ); Uxreset6 : xilinx_reset generic map ( PIPE_LEN => 15 ) port map ( clk => clk125, ready_i => clks_locked, reset_no => open, reset_o => rst_top_125_o ); Ubufg40 : BUFG port map ( O => clk40i, I => clk40i_nobufg ); Ubufgmux40 : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" ) port map ( O => open, I0 => clk40a, I1 => clk40b, S => clk_ext_sel_i ); Ubufgmux80 : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" ) port map ( O => open, I0 => clk80a, I1 => clk80b, S => clk_ext_sel_i ); Ubufpll : BUFPLL generic map ( DIVIDE => 4, -- {1..8} ENABLE_SYNC => TRUE ) port map ( IOCLK => iserdes_clk_o, LOCK => clks_locked, SERDESSTROBE => iserdes_strb_o, GCLK => clk80, LOCKED => pll_locked, PLLIN => clk320_nobufg ); Ubufpll1 : BUFPLL generic map ( DIVIDE => 8, -- {1..8} ENABLE_SYNC => TRUE ) port map ( IOCLK => is_clk_tdc_o, LOCK => clks_lckd_tdc_o, SERDESSTROBE => is_strb_tdc_o, GCLK => clk80, LOCKED => pll640_locked, PLLIN => clk640_nobufg ); Ustrb40 : strobe40_gen port map ( strobe40_o => strobe40_o, s20_o => s20_o, tog20_o => tog20_o, clk40 => clk40, rst => rst, clk => clk80 ); end struct;