Generation Settings
| Component declarations | yes |
| Configurations | in separate file |
| add pragmas |
| exclude view name |
Declarations
Ports:
--#onBoardUSBcontroller
usb_ast_ni : std_logic --#Bank=0, Pinname=IO_L35P_GCLK17, Schname=U1-FLAGA
usb_dst_ni : std_logic --#Bank=0, Pinname=IO_L35N_GCLK16, Schname=U1-FLAGB
usb_flag_i : std_logic --#Bank=0, Pinname=IO_L64P_SCP5, Schname=U1-FLAGC
usb_wait_i : std_logic --#Bank=0, Pinname=IO_L63P_SCP7, Schname=U1-SLRD
usb_db_io : std_logic_vector(7 downto 0) --#Bank=0, Pinname=IO_L2N, Schname=U1-FD0
usb_clk_i : std_logic --#Bank=0, Pinname=IO_L37P_GCLK13, Schname=U1-IFCLK
usb_oe_o : std_logic --#Bank=0, Pinname=IO_L64N_SCP4, Schname=U1-SLOE
usb_wr_o : std_logic --#Bank=0, Pinname=IO_L63N_SCP6, Schname=U1-SLWR
usb_pktend_o : std_logic --#Bank=0, Pinname=IO_L1N_VREF, Schname=U1-PKTEND
usb_dir_o : std_logic --#Bank=0, Pinname=IO_L2P, Schname=U1-SLCS
usb_mode_o : std_logic --#Bank=0, Pinname=IO_L6N, Schname=U1-INT0#
usb_adr_o : std_logic_vector(1 downto 0) --#Bank=0, Pinname=IO_L62N_VREF, Schname=U1-FIFOAD0
--#onBoardQuad-SPIFlash
flash_clk_o : std_logic --#Bank=2, Pinname=IO_L1P_CCLK_2, Schname=SCK
flash_cs_o : std_logic --#Bank=2, Pinname=IO_L65N_CSO_B_2, Schname=CS
flash_dq_i : std_logic_vector(3 downto 0) --#Bank=2, Pinname=IO_L3N_MOSI_CSI_B_MISO0_2, Schname=SDI
--#onBoardLeds
led_o : std_logic_vector(7 downto 0) --#Bank=1, Pinname=IO_L52N_M1DQ15, Schname=LD0
--#onBoardPUSHBUTTONS
btn_i : std_logic_vector(5 downto 0) --#Bank=2, Pinname=IO_L1N_M0_CMPMISO_2, Schname=M0/RESET
--#onBoardSWITCHES
sw_i : std_logic_vector(7 downto 0) --#Bank=0, Pinname=IO_L37N_GCLK12, Schname=SW0
--#DDR2
ddr2_clk0_o : std_logic --#Bank=3, Pinname=IO_L46P_M3CLK, Schname=DDR-CK_P
ddr2_clk1_o : std_logic --#Bank=3, Pinname=IO_L46N_M3CLKN, Schname=DDR-CK_N
ddr2_cke_o : std_logic --#Bank=3, Pinname=IO_L53P_M3CKE, Schname=DDR-CKE
ddr2_ras_no : std_logic --#Bank=3, Pinname=IO_L43P_GCLK23_M3RASN, Schname=DDR-RAS
ddr2_cas_no : std_logic --#Bank=3, Pinname=IO_L43N_GCLK22_IRDY2_M3CASN, Schname=DDR-CAS
ddr2_wen_o : std_logic --#Bank=3, Pinname=IO_L50P_M3WE, Schname=DDR-WE
ddr2_rzq_o : std_logic --#Bank=3, Pinname=IO_L31P, Schname=RZQ
ddr2_zio_o : std_logic --#Bank=3, Pinname=IO_L83P, Schname=ZIO
ddr2_ba_o : std_logic_vector(2 downto 0) --#Bank=3, Pinname=IO_L48P_M3BA0, Schname=DDR-BA0
ddr2_a_o : std_logic_vector(12 downto 0) --#Bank=3, Pinname=IO_L47P_M3A0, Schname=DDR-A0
ddr2_dq_io : std_logic_vector(15 downto 0) --#Bank=3, Pinname=IO_L37P_M3DQ0, Schname=DDR-DQ0
ddr2_udqs_po : std_logic --#Bank=3, Pinname=IO_L34P_M3UDQS, Schname=DDR-UDQS_P
ddr2_udqs_no : std_logic --#Bank=3, Pinname=IO_L34N_M3UDQSN, Schname=DDR-UDQS_N
ddr2_ldqs_po : std_logic --#Bank=3, Pinname=IO_L39P_M3LDQS, Schname=DDR-LDQS_P
ddr2_ldqs_no : std_logic --#Bank=3, Pinname=IO_L39N_M3LDQSN, Schname=DDR-LDQS_N
ddr2_ldm_o : std_logic --#Bank=3, Pinname=IO_L42N_GCLK24_M3LDM, Schname=DDR-LDM
ddr2_udm_o : std_logic --#Bank=3, Pinname=IO_L42P_GCLK25_TRDY2_M3UDM, Schname=DDR-UDM
ddr2_odt_o : std_logic --#Bank=3, Pinname=IO_L45N_M3ODT, Schname=DDR-ODT
--#onboardHDMIOUT
hdmi_o_clk_po : std_logic --#Bank=0, Pinname=IO_L8P, Schname=TMDS-TX-CLK_P
hdmi_o_clk_no : std_logic --#Bank=0, Pinname=IO_L8N_VREF, Schname=TMDS-TX-CLK_N
hdmi_o_d_po : std_logic_vector(2 downto 0) --#Bank=0, Pinname=IO_L11P, Schname=TMDS-TX-0_P
hdmi_o_d_no : std_logic_vector(2 downto 0) --#Bank=0, Pinname=IO_L11N, Schname=TMDS-TX-0_N
hdmi_o_scl_io : std_logic --#Bank=0, Pinname=IO_L34P_GCLK19, Schname=TMDS-TX-SCL
hdmi_o_sda_io : std_logic --#Bank=0, Pinname=IO_L34N_GCLK18, Schname=TMDS-TX-SDA
--#onboardHDMIIN1(PMODA)
hdmi_i1_clk_pi : std_logic --#Bank=0, Pinname=IO_L36P_GCLK15, Schname=TMDS-RXB-CLK_P
hdmi_i1_clk_ni : std_logic --#Bank=0, Pinname=IO_L36N_GCLK14, Schname=TMDS-RXB-CLK_N
hdmi_i1_d_pi : std_logic_vector(2 downto 0) --#Bank=0, Pinname=IO_L38P, Schname=TMDS-RXB-0_P
hdmi_i1_d_ni : std_logic_vector(2 downto 0) --#Bank=0, Pinname=IO_L38N_VREF, Schname=TMDS-RXB-0_N
hdmi_i1_scl_io : std_logic --#Bank=0, Pinname=IO_L50P, Schname=PMOD-SCL
hdmi_i1_sda_io : std_logic --#Bank=0, Pinname=IO_L50N, Schname=PMOD-SDA
--#onboardHDMIIN2
hdmi_i2_clk_pi : std_logic --#Bank=1, Pinname=IO_L43P_GCLK5_M1DQ4, Schname=TMDS-RX-CLK_P
hdmi_i2_clk_ni : std_logic --#Bank=1, Pinname=IO_L43N_GCLK4_M1DQ5, Schname=TMDS-RX-CLK_N
hdmi_i2_d_pi : std_logic_vector(2 downto 0) --#Bank=1, Pinname=IO_L45P_A1_M1LDQS, Schname=TMDS-RX-0_P
hdmi_i2_d_ni : std_logic_vector(2 downto 0) --#Bank=1, Pinname=IO_L45N_A0_M1LDQSN, Schname=TMDS-RX-0_N
hdmi_i2_scl_io : std_logic --#Bank=1, Pinname=IO_L47P_FWE_B_M1DQ0, Schname=TMDS-RX-SCL
hdmi_i2_sda_io : std_logic --#Bank=1, Pinname=IO_L47N_LDC_M1DQ1, Schname=TMDS-RX-SDA
--#onboardUSBHostController
usbhost_clk_o : std_logic --#Bank=1, Pinname=IO_L49P_M1DQ10, Schname=PIC32-SCK1
usbhost_ss_o : std_logic --#Bank=1, Pinname=IO_L49N_M1DQ11, Schname=PIC32-SS1
usbhost_sdi_i : std_logic --#Bank=1, Pinname=IO_L50P_M1UDQS, Schname=PIC32-SDI1
usbhost_sdo_o : std_logic --#Bank=1, Pinname=IO_L48N_M1DQ9, Schname=PIC32-SDO1
--#Audio
aud_bitclk_i : std_logic --#Bank=1, Pinname=IO_L40N_GCLK10_M1A6, Schname=AUD-BIT-CLK
aud_sdi_i : std_logic --#Bank=1, Pinname=IO_L51N_M1DQ13, Schname=AUD-SDI
aud_sdo_o : std_logic --#Bank=1, Pinname=IO_L50N_M1UDQSN, Schname=AUD-SDO
aud_sync_o : std_logic --#Bank=1, Pinname=IO_L52P_M1DQ14, Schname=AUD-SYNC
aud_rst_o : std_logic --#Bank=1, Pinname=IO_L51P_M1DQ12, Schname=AUD-RESET
--#PMODConnector
pmod_ja_io : std_logic_vector(7 downto 0) --#Bank=2, Pinname=IO_L62N_D6, Schname=JA-D0_N
--#onboardVHDCI
--#Channnel1connectstoPsignals,Channel2toNsignals
vmod_exp_pio : std_logic_vector(20 downto 1) --#Bank=2, Pinname=IO_L2P_CMPCLK, Schname=EXP-IO1_P
vmod_exp_nio : std_logic_vector(20 downto 1) --#Bank=2, Pinname=IO_L2N_CMPMOSI, Schname=EXP-IO1_N
--#USBUARTConnector
usbuart_rx_i : std_logic --#Bank=0, Pinname=IO_L66N_SCP0, Schname=USBB-RXD
usbuart_tx_o : std_logic --#Bank=0, Pinname=IO_L66P_SCP1, Schname=USBB-TXD
eth_txclk_o : std_logic --#Bank=1, Pinname=IO_L41N_GCLK8_M1CASN, Schname=E-TXCLK
eth_txd_o : std_logic_vector(7 downto 0) --#Bank=1, Pinname=IO_L37N_A6_M1A1, Schname=E-TXD0
eth_rxd_i : std_logic_vector(7 downto 0) --#Bank=1, Pinname=IO_L38P_A5_M1CLK, Schname=E-RXD0
eth_rxdv_i : std_logic --#Bank=1, Pinname=IO_L35P_A11_M1A7, Schname=E-RXDV
eth_rxer_i : std_logic --#Bank=1, Pinname=IO_L35N_A10_M1A2, Schname=E-RXER
eth_rxclk_i : std_logic --#Bank=1, Pinname=IO_L41P_GCLK9_IRDY1_M1RASN, Schname=E-RXCLK
eth_mdc_i : std_logic --#Bank=1, Pinname=IO_L1N_A24_VREF, Schname=E-MDC
eth_mdi_i : std_logic --#Bank=1, Pinname=IO_L48P_HDC_M1DQ8, Schname=E-MDIO
eth_int_i : std_logic --#Bank=1, Pinname=IO_L42N_GCLK6_TRDY1_M1LDM, Schname=E-INT
led_status_o : std_logic --LED_FPGA_STATUS
eth_gtxclk_o : std_logic --#Bank=1, Pinname=IO_L40P_GCLK11_M1A5, Schname=E-GTXCLK
eth_col_i : std_logic --#Bank=1, Pinname=IO_L42N_GCLK6_TRDY1_M1LDM, Schname=E-INT
eth_crs_i : std_logic --#Bank=1, Pinname=IO_L42N_GCLK6_TRDY1_M1LDM, Schname=E-INT
--#TEMACEthernetMAC
eth_rst_no : std_logic --#Bank=1, Pinname=IO_L32N_A16_M1A9, Schname=E-RESET
eth_txer_o : std_logic --#Bank=1, Pinname=IO_L38N_A4_M1CLKN, Schname=E-TXER
eth_txen_o : std_logic --#Bank=1, Pinname=IO_L37P_A7_M1A0, Schname=E-TXEN
--#clockpinforAtlysrevCboard
clk100_i : std_logic
-- rx ll fifo interface
sim_rx_lls_i : t_llsrc
sim_rx_lld_o : std_logic
sim_tx_lls_o : t_llsrc
sim_tx_lld_i : std_logic
sim_clk80_o : std_logic
sim_iserdes_clk_o : std_logic
sim_rst_top_o : std_logic
sim_clk40_o : std_logic
sim_clk125_o : std_logic
sim_rst125_o : std_logic
Diagram Signals:
signal HI : std_logic
signal LO : std_logic
signal clk40 : std_logic
signal clk160 : std_logic
signal tick : std_logic_vector(MAX_TICTOG downto 0)
-- Client Receiver Interface - EMAC0
signal led : std_logic_vector(7 downto 0)
-- Client Receiver Interface - EMAC0
signal led0 : std_logic_vector(7 downto 0)
--#onBoardLeds
signal fw_version : std_logic_vector(7 downto 0) --#Bank=1, Pinname=IO_L52N_M1DQ15, Schname=LD0
signal tog : std_logic_vector(MAX_TICTOG downto 0)
signal clk80 : std_logic
signal rst_n : std_logic
signal ZERO2 : std_logic_vector(1 downto 0)
signal ZERO4 : std_logic_vector(3 downto 0)
signal ZERO8 : std_logic_vector(7 downto 0)
signal ZERO13 : std_logic_vector(12 downto 0)
signal ZERO16 : std_logic_vector(15 downto 0)
signal ext_por_n : std_logic
-- rx ll fifo interface
signal rx_lls : t_llsrc
signal tx_lld : std_logic
signal tx_lls : t_llsrc
signal rx_lld : std_logic
signal rawsigs : std_logic_vector(15 downto 0)
signal outsigs : std_logic_vector(15 downto 0)
signal dbg_outsigs : std_logic_vector(15 downto 0)
signal clk_ext_on : std_logic
--idelay_ce_o : out std_logic_vector (71 downto 0);
--idelay_inc_o : out std_logic;
--idelay_zero_o : out std_logic_vector (71 downto 0);
signal idelay_ctl : t_idelay_ctl
signal sda_tx : std_logic_vector(15 DOWNTO 0)
signal sck_t : std_logic_vector(15 DOWNTO 0)
signal sck : std_logic_vector(15 DOWNTO 0)
signal sda_t : std_logic_vector(15 DOWNTO 0)
signal sda_rx : std_logic_vector(15 DOWNTO 0)
signal dbg_count : std_logic_vector(7 downto 0)
signal clocky_leds : std_logic_vector(7 downto 0)
signal stat_clks_top : std_logic_vector(7 downto 0)
-- registers
signal reg : t_reg_bus
signal db_wr : std_logic_vector(31 DOWNTO 0)
signal stat_clks_main : std_logic_vector(3 downto 0)
signal ZERO64 : std_logic_vector(63 downto 0)
signal s40 : std_logic
signal sf_stat_word : slv64_array(1 DOWNTO 0)
signal sf_mac_stat : slv64_array(1 DOWNTO 0)
signal stat_word_usb : std_logic_vector(63 downto 0)
signal stat_word_cu : std_logic_vector(63 DOWNTO 0)
signal clk125 : std_logic
signal clkn125 : std_logic
signal clk125_locked : std_logic
signal clk100_bufg : std_ulogic
signal clks_locked : std_logic
signal macaddress : std_logic_vector(47 DOWNTO 0)
signal net_leds : std_logic_vector(3 downto 0)
signal iserdes_strb : std_logic
signal iserdes_clk : std_ulogic
signal idelay_cal : std_logic
signal idelay_busy : std_logic
signal s20 : std_logic
signal tog20 : std_logic
signal rst_main : std_logic
signal rst_net : std_logic
signal rst_dio : std_logic
signal rst_top : std_logic
signal rst125 : std_ulogic
signal tlu_tclk : std_logic
signal tlu_busy : std_logic
signal tlu_rst : std_logic
signal tlu_trig : std_logic
signal tlu_busy_n : std_logic
signal tlu_tclk_n : std_logic
signal tlu_trig_n : std_logic
signal tlu_rst_n : std_logic
signal strm_reg : slv16_array(143 DOWNTO 0)
signal com_abc : std_logic
-- In
signal rx_link4x : slv4_array(67 downto 0)
signal dbg_link_delayed : std_logic_vector(67 downto 0)
signal tdc_calib_edge0_i : std_logic
signal tdc_counter1 : std_logic_vector(31 downto 0)
signal tdc_counter2 : std_logic_vector(31 downto 0)
signal tdc_data : std_logic_vector(39 downto 0)
signal tdc_new : std_logic
signal is_clk_tdc : std_logic
signal is_strb_tdc : std_logic
signal command : std_logic_vector(15 DOWNTO 0)
signal rx_len : std_logic_vector(15 downto 0)
signal oc_dack_n : std_logic
-- hsio oc bus
signal oc_data : std_logic_vector(15 DOWNTO 0)
-- locallink interfaces
--in
signal lls_top : t_llsrc_array(1 downto 0)
signal lld_top : std_logic_vector(1 downto 0)
signal rx_size : std_logic_vector(15 downto 0)
signal rx_cbcnt : std_logic_vector(15 downto 0)
signal rx_seq : std_logic_vector(15 downto 0)
signal rx_opcode : std_logic_vector(15 downto 0)
signal rx_magicn : std_logic_vector(15 downto 0)
signal rx_opseq : std_logic_vector(15 downto 0)
signal oc_valid : std_logic
signal dbg_oc_start : std_logic
signal rst_ocb : std_logic
signal core_lls : t_llsrc
signal core_lld : std_logic
signal rst_top_125 : std_ulogic
signal clk_in : std_logic
signal out_1 : std_logic
signal out_2 : std_logic
signal pardata : std_logic_vector(7 downto 0)
signal pmod_tlu_trig_n : std_logic
signal in_2 : std_logic
signal in_1_par : std_logic_vector(7 downto 0)
Pre User:
Post User:
attribute KEEP : string;
attribute KEEP of rst_net : signal is "true";
Package List
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils;
use utils.pkg_types.all;
library atlys;
use atlys.pkg_atlys_itsdaq.all;
library hsio;
use hsio.pkg_core_globals.all;
library unisim;
use unisim.VCOMPONENTS.all;
Bundles