-- VHDL Entity atlys.itsdaq_top.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 12:05:32 05/25/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; entity itsdaq_top is generic( SIM_MODE : integer := 0 ); port( --#clockpinforAtlysrevCboard clk100_i : in std_logic; --#onBoardUSBcontroller usb_ast_ni : in std_logic; --#Bank=0, Pinname=IO_L35P_GCLK17, Schname=U1-FLAGA usb_dst_ni : in std_logic; --#Bank=0, Pinname=IO_L35N_GCLK16, Schname=U1-FLAGB usb_wait_i : in std_logic; --#Bank=0, Pinname=IO_L63P_SCP7, Schname=U1-SLRD usb_flag_i : in std_logic; --#Bank=0, Pinname=IO_L64P_SCP5, Schname=U1-FLAGC usb_db_io : out std_logic_vector (7 downto 0); --#Bank=0, Pinname=IO_L2N, Schname=U1-FD0 usb_clk_i : in std_logic; --#Bank=0, Pinname=IO_L37P_GCLK13, Schname=U1-IFCLK usb_oe_o : out std_logic; --#Bank=0, Pinname=IO_L64N_SCP4, Schname=U1-SLOE usb_wr_o : out std_logic; --#Bank=0, Pinname=IO_L63N_SCP6, Schname=U1-SLWR usb_pktend_o : out std_logic; --#Bank=0, Pinname=IO_L1N_VREF, Schname=U1-PKTEND usb_dir_o : out std_logic; --#Bank=0, Pinname=IO_L2P, Schname=U1-SLCS usb_mode_o : out std_logic; --#Bank=0, Pinname=IO_L6N, Schname=U1-INT0# usb_adr_o : out std_logic_vector (1 downto 0); --#Bank=0, Pinname=IO_L62N_VREF, Schname=U1-FIFOAD0 --#onBoardQuad-SPIFlash flash_clk_o : out std_logic; --#Bank=2, Pinname=IO_L1P_CCLK_2, Schname=SCK flash_cs_o : out std_logic; --#Bank=2, Pinname=IO_L65N_CSO_B_2, Schname=CS flash_dq_i : in std_logic_vector (3 downto 0); --#Bank=2, Pinname=IO_L3N_MOSI_CSI_B_MISO0_2, Schname=SDI --#onBoardLeds led_o : out std_logic_vector (7 downto 0); --#Bank=1, Pinname=IO_L52N_M1DQ15, Schname=LD0 --#onBoardPUSHBUTTONS btn_i : in std_logic_vector (5 downto 0); --#Bank=2, Pinname=IO_L1N_M0_CMPMISO_2, Schname=M0/RESET --#onBoardSWITCHES sw_i : in std_logic_vector (7 downto 0); --#Bank=0, Pinname=IO_L37N_GCLK12, Schname=SW0 --#DDR2 ddr2_clk0_o : out std_logic; --#Bank=3, Pinname=IO_L46P_M3CLK, Schname=DDR-CK_P ddr2_clk1_o : out std_logic; --#Bank=3, Pinname=IO_L46N_M3CLKN, Schname=DDR-CK_N ddr2_cke_o : out std_logic; --#Bank=3, Pinname=IO_L53P_M3CKE, Schname=DDR-CKE ddr2_ras_no : out std_logic; --#Bank=3, Pinname=IO_L43P_GCLK23_M3RASN, Schname=DDR-RAS ddr2_cas_no : out std_logic; --#Bank=3, Pinname=IO_L43N_GCLK22_IRDY2_M3CASN, Schname=DDR-CAS ddr2_wen_o : out std_logic; --#Bank=3, Pinname=IO_L50P_M3WE, Schname=DDR-WE ddr2_rzq_o : out std_logic; --#Bank=3, Pinname=IO_L31P, Schname=RZQ ddr2_zio_o : out std_logic; --#Bank=3, Pinname=IO_L83P, Schname=ZIO ddr2_ba_o : out std_logic_vector (2 downto 0); --#Bank=3, Pinname=IO_L48P_M3BA0, Schname=DDR-BA0 ddr2_a_o : out std_logic_vector (12 downto 0); --#Bank=3, Pinname=IO_L47P_M3A0, Schname=DDR-A0 ddr2_dq_io : inout std_logic_vector (15 downto 0); --#Bank=3, Pinname=IO_L37P_M3DQ0, Schname=DDR-DQ0 ddr2_udqs_po : out std_logic; --#Bank=3, Pinname=IO_L34P_M3UDQS, Schname=DDR-UDQS_P ddr2_udqs_no : out std_logic; --#Bank=3, Pinname=IO_L34N_M3UDQSN, Schname=DDR-UDQS_N ddr2_ldqs_po : out std_logic; --#Bank=3, Pinname=IO_L39P_M3LDQS, Schname=DDR-LDQS_P ddr2_ldqs_no : out std_logic; --#Bank=3, Pinname=IO_L39N_M3LDQSN, Schname=DDR-LDQS_N ddr2_ldm_o : out std_logic; --#Bank=3, Pinname=IO_L42N_GCLK24_M3LDM, Schname=DDR-LDM ddr2_udm_o : out std_logic; --#Bank=3, Pinname=IO_L42P_GCLK25_TRDY2_M3UDM, Schname=DDR-UDM ddr2_odt_o : out std_logic; --#Bank=3, Pinname=IO_L45N_M3ODT, Schname=DDR-ODT --#onboardHDMIOUT hdmi_o_clk_po : out std_logic; --#Bank=0, Pinname=IO_L8P, Schname=TMDS-TX-CLK_P hdmi_o_clk_no : out std_logic; --#Bank=0, Pinname=IO_L8N_VREF, Schname=TMDS-TX-CLK_N hdmi_o_d_po : out std_logic_vector (2 downto 0); --#Bank=0, Pinname=IO_L11P, Schname=TMDS-TX-0_P hdmi_o_d_no : out std_logic_vector (2 downto 0); --#Bank=0, Pinname=IO_L11N, Schname=TMDS-TX-0_N hdmi_o_scl_io : inout std_logic; --#Bank=0, Pinname=IO_L34P_GCLK19, Schname=TMDS-TX-SCL hdmi_o_sda_io : inout std_logic; --#Bank=0, Pinname=IO_L34N_GCLK18, Schname=TMDS-TX-SDA --#onboardHDMIIN1(PMODA) hdmi_i1_clk_pi : in std_logic; --#Bank=0, Pinname=IO_L36P_GCLK15, Schname=TMDS-RXB-CLK_P hdmi_i1_clk_ni : in std_logic; --#Bank=0, Pinname=IO_L36N_GCLK14, Schname=TMDS-RXB-CLK_N hdmi_i1_d_pi : in std_logic_vector (2 downto 0); --#Bank=0, Pinname=IO_L38P, Schname=TMDS-RXB-0_P hdmi_i1_d_ni : in std_logic_vector (2 downto 0); --#Bank=0, Pinname=IO_L38N_VREF, Schname=TMDS-RXB-0_N hdmi_i1_scl_io : inout std_logic; --#Bank=0, Pinname=IO_L50P, Schname=PMOD-SCL hdmi_i1_sda_io : inout std_logic; --#Bank=0, Pinname=IO_L50N, Schname=PMOD-SDA --#onboardHDMIIN2 hdmi_i2_clk_pi : in std_logic; --#Bank=1, Pinname=IO_L43P_GCLK5_M1DQ4, Schname=TMDS-RX-CLK_P hdmi_i2_clk_ni : in std_logic; --#Bank=1, Pinname=IO_L43N_GCLK4_M1DQ5, Schname=TMDS-RX-CLK_N hdmi_i2_d_pi : in std_logic_vector (2 downto 0); --#Bank=1, Pinname=IO_L45P_A1_M1LDQS, Schname=TMDS-RX-0_P hdmi_i2_d_ni : in std_logic_vector (2 downto 0); --#Bank=1, Pinname=IO_L45N_A0_M1LDQSN, Schname=TMDS-RX-0_N hdmi_i2_scl_io : inout std_logic; --#Bank=1, Pinname=IO_L47P_FWE_B_M1DQ0, Schname=TMDS-RX-SCL hdmi_i2_sda_io : inout std_logic; --#Bank=1, Pinname=IO_L47N_LDC_M1DQ1, Schname=TMDS-RX-SDA --#onboardUSBHostController usbhost_clk_o : out std_logic; --#Bank=1, Pinname=IO_L49P_M1DQ10, Schname=PIC32-SCK1 usbhost_ss_o : out std_logic; --#Bank=1, Pinname=IO_L49N_M1DQ11, Schname=PIC32-SS1 usbhost_sdi_i : in std_logic; --#Bank=1, Pinname=IO_L50P_M1UDQS, Schname=PIC32-SDI1 usbhost_sdo_o : out std_logic; --#Bank=1, Pinname=IO_L48N_M1DQ9, Schname=PIC32-SDO1 --#Audio aud_bitclk_i : in std_logic; --#Bank=1, Pinname=IO_L40N_GCLK10_M1A6, Schname=AUD-BIT-CLK aud_sdi_i : in std_logic; --#Bank=1, Pinname=IO_L51N_M1DQ13, Schname=AUD-SDI aud_sdo_o : out std_logic; --#Bank=1, Pinname=IO_L50N_M1UDQSN, Schname=AUD-SDO aud_sync_o : out std_logic; --#Bank=1, Pinname=IO_L52P_M1DQ14, Schname=AUD-SYNC aud_rst_o : out std_logic; --#Bank=1, Pinname=IO_L51P_M1DQ12, Schname=AUD-RESET --#onboardVHDCI --#Channnel1connectstoPsignals,Channel2toNsignals vmod_exp_pio : inout std_logic_vector (20 downto 1); --#Bank=2, Pinname=IO_L2P_CMPCLK, Schname=EXP-IO1_P vmod_exp_nio : inout std_logic_vector (20 downto 1); --#Bank=2, Pinname=IO_L2N_CMPMOSI, Schname=EXP-IO1_N --#USBUARTConnector usbuart_rx_i : in std_logic; --#Bank=0, Pinname=IO_L66N_SCP0, Schname=USBB-RXD usbuart_tx_o : out std_logic; --#Bank=0, Pinname=IO_L66P_SCP1, Schname=USBB-TXD eth_txclk_o : out std_logic; --#Bank=1, Pinname=IO_L41N_GCLK8_M1CASN, Schname=E-TXCLK eth_txd_o : out std_logic_vector (7 downto 0); --#Bank=1, Pinname=IO_L37N_A6_M1A1, Schname=E-TXD0 eth_txen_o : out std_logic; --#Bank=1, Pinname=IO_L37P_A7_M1A0, Schname=E-TXEN eth_txer_o : out std_logic; --#Bank=1, Pinname=IO_L38N_A4_M1CLKN, Schname=E-TXER eth_gtxclk_o : out std_logic; --#Bank=1, Pinname=IO_L40P_GCLK11_M1A5, Schname=E-GTXCLK eth_rxd_i : in std_logic_vector (7 downto 0); --#Bank=1, Pinname=IO_L38P_A5_M1CLK, Schname=E-RXD0 eth_rxdv_i : in std_logic; --#Bank=1, Pinname=IO_L35P_A11_M1A7, Schname=E-RXDV eth_rxer_i : in std_logic; --#Bank=1, Pinname=IO_L35N_A10_M1A2, Schname=E-RXER eth_rxclk_i : in std_logic; --#Bank=1, Pinname=IO_L41P_GCLK9_IRDY1_M1RASN, Schname=E-RXCLK eth_mdc_i : in std_logic; --#Bank=1, Pinname=IO_L1N_A24_VREF, Schname=E-MDC eth_mdi_i : in std_logic; --#Bank=1, Pinname=IO_L48P_HDC_M1DQ8, Schname=E-MDIO eth_int_i : in std_logic; --#Bank=1, Pinname=IO_L42N_GCLK6_TRDY1_M1LDM, Schname=E-INT eth_col_i : in std_logic; --#Bank=1, Pinname=IO_L42N_GCLK6_TRDY1_M1LDM, Schname=E-INT eth_crs_i : in std_logic; --#Bank=1, Pinname=IO_L42N_GCLK6_TRDY1_M1LDM, Schname=E-INT --#TEMACEthernetMAC eth_rst_no : out std_logic; --#Bank=1, Pinname=IO_L32N_A16_M1A9, Schname=E-RESET led_status_o : out std_logic; --LED_FPGA_STATUS --#PMODConnector pmod_ja_io : inout std_logic_vector (7 downto 0); --#Bank=2, Pinname=IO_L62N_D6, Schname=JA-D0_N sim_rst_top_o : out std_logic; sim_rst125_o : out std_logic; -- rx ll fifo interface sim_rx_lls_i : in t_llsrc; sim_tx_lld_i : in std_logic; sim_tx_lls_o : out t_llsrc; sim_rx_lld_o : out std_logic; sim_iserdes_clk_o : out std_logic; sim_clk80_o : out std_logic; sim_clk125_o : out std_logic; sim_clk40_o : out std_logic ); -- Declarations end itsdaq_top ; -- -- VHDL Architecture atlys.itsdaq_top.struct -- -- Created: -- by - warren.warren (mbb) -- at - 12:14:46 05/29/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library atlys; use atlys.pkg_atlys_itsdaq.all; library hsio; use hsio.pkg_core_globals.all; library unisim; use unisim.VCOMPONENTS.all; architecture struct of itsdaq_top is -- Architecture declarations -- Internal signal declarations --#onBoardLeds signal fw_version : std_logic_vector(7 downto 0); --#Bank=1, Pinname=IO_L52N_M1DQ15, Schname=LD0 -- Client Receiver Interface - EMAC0 signal led : std_logic_vector(7 downto 0); signal HI : std_logic; signal LO : std_logic; signal rst_dio : std_logic; signal rst_top : std_logic; signal rst_main : std_logic; signal clk40 : std_logic; signal clk80 : std_logic; signal clk160 : std_logic; -- Client Receiver Interface - EMAC0 signal led0 : std_logic_vector(7 downto 0); signal tick : std_logic_vector(MAX_TICTOG downto 0); signal tog : std_logic_vector(MAX_TICTOG downto 0); signal rst_n : std_logic; signal ZERO2 : std_logic_vector(1 downto 0); signal ZERO4 : std_logic_vector(3 downto 0); signal ZERO8 : std_logic_vector(7 downto 0); signal ZERO13 : std_logic_vector(12 downto 0); signal ZERO16 : std_logic_vector(15 downto 0); signal ext_por_n : std_logic; signal ZERO64 : std_logic_vector(63 downto 0); -- rx ll fifo interface signal rx_lls : t_llsrc; signal tx_lld : std_logic; signal tx_lls : t_llsrc; signal rx_lld : std_logic; signal rawsigs : std_logic_vector(15 downto 0); signal outsigs : std_logic_vector(15 downto 0); signal dbg_outsigs : std_logic_vector(15 downto 0); signal clk_ext_on : std_logic; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); signal idelay_ctl : t_idelay_ctl; signal sda_tx : std_logic_vector(15 downto 0); signal sck_t : std_logic_vector(15 downto 0); signal sck : std_logic_vector(15 downto 0); signal sda_t : std_logic_vector(15 downto 0); signal sda_rx : std_logic_vector(15 downto 0); signal dbg_count : std_logic_vector(7 downto 0); signal clocky_leds : std_logic_vector(7 downto 0); signal stat_clks_top : std_logic_vector(7 downto 0); -- registers signal reg : t_reg_bus; signal db_wr : std_logic_vector(31 downto 0); signal stat_clks_main : std_logic_vector(3 downto 0); signal s40 : std_logic; signal sf_stat_word : slv64_array(1 downto 0); signal sf_mac_stat : slv64_array(1 downto 0); signal stat_word_usb : std_logic_vector(63 downto 0); signal stat_word_cu : std_logic_vector(63 downto 0); signal clk125 : std_logic; signal clkn125 : std_logic; signal clk100_bufg : std_ulogic; signal clk125_locked : std_logic; signal clks_locked : std_logic; signal macaddress : std_logic_vector(47 downto 0); signal net_leds : std_logic_vector(3 downto 0); signal iserdes_strb : std_logic; signal iserdes_clk : std_ulogic; signal idelay_cal : std_logic; signal idelay_busy : std_logic; signal s20 : std_logic; signal tog20 : std_logic; signal rst_net : std_logic; signal rst125 : std_ulogic; signal tlu_tclk : std_logic; signal tlu_tclk_n : std_logic; signal tlu_busy : std_logic; signal tlu_busy_n : std_logic; signal tlu_rst : std_logic; signal tlu_rst_n : std_logic; signal tlu_trig : std_logic; signal in_1_par : std_logic_vector(7 downto 0); signal in_2 : std_logic; signal out_1 : std_logic; signal out_2 : std_logic; signal tlu_trig_n : std_logic; signal strm_reg : slv16_array(143 downto 0); signal com_abc : std_logic; -- In signal rx_link4x : slv4_array(67 downto 0); signal dbg_link_delayed : std_logic_vector(67 downto 0); signal tdc_calib_edge0_i : std_logic; signal tdc_counter1 : std_logic_vector(31 downto 0); signal tdc_counter2 : std_logic_vector(31 downto 0); signal tdc_data : std_logic_vector(39 downto 0); signal tdc_new : std_logic; signal pmod_tlu_trig_n : std_logic; signal is_clk_tdc : std_logic; signal is_strb_tdc : std_logic; signal command : std_logic_vector(15 downto 0); signal rx_len : std_logic_vector(15 downto 0); signal oc_dack_n : std_logic; -- hsio oc bus signal oc_data : std_logic_vector(15 downto 0); -- locallink interfaces --in signal lls_top : t_llsrc_array(1 downto 0); signal lld_top : std_logic_vector(1 downto 0); signal rx_size : std_logic_vector(15 downto 0); signal rx_cbcnt : std_logic_vector(15 downto 0); signal rx_seq : std_logic_vector(15 downto 0); signal rx_opcode : std_logic_vector(15 downto 0); signal rx_magicn : std_logic_vector(15 downto 0); signal rx_opseq : std_logic_vector(15 downto 0); signal oc_valid : std_logic; signal dbg_oc_start : std_logic; signal rst_ocb : std_logic; signal core_lld : std_logic; signal core_lls : t_llsrc; signal rst_top_125 : std_ulogic; signal clk_in : std_logic; signal pardata : std_logic_vector(7 downto 0); attribute KEEP : string; attribute KEEP of rst_net : signal is "true"; -- Component Declarations component dio_cmos_mbh port ( clk : in std_logic ; clk160 : in std_logic ; clk_io_i : in std_logic ; idelay_cal_i : in std_logic ; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl ; iserdes_strb_i : in std_logic ; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus ; rst : in std_logic ; strobe40_i : in std_logic ; tlu_busy : in std_logic ; tlu_rst : in std_logic ; tlu_tclk : in std_logic ; tlu_trig : in std_logic ; tog20_i : in std_logic ; idelay_busy_o : out std_logic ; rx_link4x_o : out slv4_array (15 downto 0); v_nio : inout std_logic_vector (20 downto 1); v_pio : inout std_logic_vector (20 downto 1) ); end component; component dio_itsdaq_drv port ( clk : in std_logic ; clk_io_i : in std_logic ; coml0_i : in std_logic ; idelay_cal_i : in std_logic ; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl ; iserdes_strb_i : in std_logic ; l1r3_i : in std_logic ; noise_i : in std_logic ; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus ; rst : in std_logic ; sck_i : in std_logic ; sck_t_i : in std_logic ; sda_t_i : in std_logic ; sda_tx_i : in std_logic ; strobe40_i : in std_logic ; --dbg_sig_o : out std_logic; dbg_coml0_o : out std_logic ; --dbg_sig_o : out std_logic; dbg_l1r3_o : out std_logic ; --dbg_sig_o : out std_logic; dbg_spare_o : out std_logic ; idelay_busy_o : out std_logic ; rx_link4x_o : out slv4_array (15 downto 0); sda_rx_o : out std_logic ; vm_nio : inout std_logic_vector (20 downto 1); vm_pio : inout std_logic_vector (20 downto 1) ); end component; component dio_vib_abcn port ( clk : in std_logic ; clk_io_i : in std_logic ; com_i : in std_logic ; idelay_cal_i : in std_logic ; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl ; iserdes_strb_i : in std_logic ; l1r_i : in std_logic ; rawcom_en_com_i : in std_logic ; rawcom_en_l1r_i : in std_logic ; rawcom_en_rst_i : in std_logic ; rawcom_i : in std_logic ; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus ; reset_i : in std_logic ; rst : in std_logic ; strm_reg_i : in slv16_array (143 downto 0); strobe40_i : in std_logic ; tlu_busy : in std_logic ; tlu_rst : in std_logic ; tlu_tclk : in std_logic ; tlu_trig : in std_logic ; dbg_com_o : out std_logic ; dbg_l1r_o : out std_logic ; dbg_reset_o : out std_logic ; idelay_busy_o : out std_logic ; rx_link4x_o : out slv4_array (15 downto 0); vm_nio : inout std_logic_vector (20 downto 1); vm_pio : inout std_logic_vector (20 downto 1) ); end component; component dio_vib_idc port ( clk : in std_logic ; clk_io_i : in std_logic ; com_i : in std_logic ; idelay_cal_i : in std_logic ; --idelay_ce_o : out std_logic_vector (71 downto 0); --idelay_inc_o : out std_logic; --idelay_zero_o : out std_logic_vector (71 downto 0); idelay_ctl_i : in t_idelay_ctl ; iserdes_strb_i : in std_logic ; l1r_i : in std_logic ; rawcom_en_com_i : in std_logic ; rawcom_en_l1r_i : in std_logic ; rawcom_en_rst_i : in std_logic ; rawcom_i : in std_logic ; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus ; reset_i : in std_logic ; rst : in std_logic ; strm_reg_i : in slv16_array (143 downto 0); strobe40_i : in std_logic ; tlu_busy : in std_logic ; tlu_rst : in std_logic ; tlu_tclk : in std_logic ; tlu_trig : in std_logic ; dbg_com_o : out std_logic ; dbg_l1r_o : out std_logic ; dbg_reset_o : out std_logic ; idelay_busy_o : out std_logic ; rx_link4x_o : out slv4_array (15 downto 0); vm_nio : inout std_logic_vector (20 downto 1); vm_pio : inout std_logic_vector (20 downto 1) ); end component; component iodelay2_prog port ( clk : in std_logic; idelay_busy_i : in std_logic; reg_i : in std_logic_vector (15 downto 0); reg_wr_i : in std_logic; rst : in std_logic; idelay_cal_o : out std_logic; idelay_ctl_o : out t_idelay_ctl ); end component; component iserdes2_tdc_8b port ( clk_io_i : in std_logic ; strb_i : in std_logic ; -- From the system into the device --DATA_IN_FROM_PINS serdata_i : in std_logic ; --_vector(sys_w-1 downto 0); --DATA_IN_TO_DEVICE pardata_o : out std_logic_vector (7 downto 0); --dev_w-1 downto 0); pardata_no : out std_logic_vector (7 downto 0); --dev_w-1 downto 0); -- Clock and reset signals --CLK_IN : in std_logic; -- Fast clock from PLL/MMCM CLK_DIV_IN : in std_logic ; -- Slow clock from PLL/MMCM --LOCKED_IN : in std_logic; --LOCKED_OUT : out std_logic; IO_RESET : in std_logic ); end component; component itsdaq_clk_rst port ( --#clockpinforAtlysrevCboard clk100_i : in std_logic ; rst_top_o : out std_logic ; rst1_o : out std_logic ; rst2_o : out std_logic ; clk40_o : out std_logic ; ext_bco_i : in std_logic ; rst_btn_ni : in std_logic ; rst_no : out std_logic ; clk_ext_sel_i : in std_logic ; ext_por_no : out std_logic ; strobe40_o : out std_logic ; clk125_locked_o : out std_logic ; clk125_o : out std_logic ; iserdes_clk_o : out std_ulogic ; is_clk_tdc_o : out std_logic ; iserdes_strb_o : out std_logic ; is_strb_tdc_o : out std_logic ; clk80_o : out std_logic ; clks_locked_o : out std_logic ; s20_o : out std_logic ; tog20_o : out std_logic ; rst3_o : out std_logic ; rst125_o : out std_ulogic ; rst_top_125_o : out std_ulogic ); end component; component net_top port ( -- asynchronous reset glbl_rst : in std_logic ; -- 200MHz clock input from board --***clk_in_p : in std_logic; --***clk_in_n : in std_logic; clk125_i : in std_logic ; --*** dcm_locked_i : in std_logic ; --*** phy_resetn : out std_logic ; -- GMII Interface ----------------- gmii_txd : out std_logic_vector (7 downto 0); gmii_tx_en : out std_logic ; gmii_tx_er : out std_logic ; gmii_tx_clk : out std_logic ; gmii_rxd : in std_logic_vector (7 downto 0); gmii_rx_dv : in std_logic ; gmii_rx_er : in std_logic ; gmii_rx_clk : in std_logic ; gmii_col : in std_logic ; gmii_crs : in std_logic ; -- Serialised statistics vectors -------------------------------- tx_statistics_s : out std_logic ; rx_statistics_s : out std_logic ; -- Serialised Pause interface controls -------------------------------------- pause_req_s : in std_logic ; fifo_clk_locked_i : in std_logic ; fifo_clk_i : in std_logic ; -- clock to be sync'ed to monitor_o : out std_logic_vector (3 downto 0); rx_lld_i : in std_logic ; tx_lls_i : in t_llsrc ; tx_lld_o : out std_logic ; rx_lls_o : out t_llsrc ; macaddress_i : in std_logic_vector (47 downto 0) ); end component; component main_top generic ( SIM_MODE : integer := 0; TOP_ID : integer := 16#0C02#; ISHSIO : integer := 1; TRIG_TLU_EN : integer := 1; TRIG_TDC_EN : integer := 1; BUILD_NO : integer := 1; RO_MOD_PRES : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_RAW : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_HST : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_TYPE : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_IDBG : std_logic_vector(35 downto 0) := x"000000000"; RO_TYPE : integer := 99 ); port ( idc_p3_io : inout std_logic_vector (31 downto 0); --IDC_P3 sim_dat_lvds_o : out std_logic_vector (31 downto 0); idc_p4_io : inout std_logic_vector (31 downto 0); --IDC_P4 idc_p5_io : out std_logic_vector (31 downto 0); --IDC_P5 led_status_o : out std_logic ; --LED_FPGA_STATUS -- DISPLAY disp_clk_o : out std_logic ; --DISP_CLK disp_dat_o : out std_logic ; --DISP_DAT disp_rst_no : out std_logic ; --DISP_RST_N disp_load_no : out std_logic_vector (1 downto 0); --DISP_LOAD1_N sma_io : inout std_logic_vector (8 downto 1); --IDC_P5 sw_hex_ni : in std_logic_vector (3 downto 0); clk : in std_logic ; clk40 : in std_logic ; spiser_clk_o : out std_logic ; -- payload output spiser_com_o : out std_logic ; sf_stat_word_i : in slv64_array (1 downto 0); tx_ok_i : in std_logic ; -- Client Receiver Interface - EMAC0 rx_ok_i : in std_logic ; sf_mac_stat_i : in slv64_array (1 downto 0); sf_syncacq_i : in std_logic_vector (1 downto 0); stat_word_cu : in std_logic_vector (63 downto 0); stat_word_usb : in std_logic_vector (63 downto 0); ti2c_cvst_no : out std_logic_vector (2 downto 0); ti2c_cvstt_no : out std_logic_vector (2 downto 0); tx_lls_o : out t_llsrc ; sck_o : out slv16 ; sck_to : out slv16 ; sda_o : out slv16 ; sda_to : out slv16 ; sda_i : in slv16 ; rst_in : in std_logic ; tx_lld_i : in std_logic ; rawsigs_o : out std_logic_vector (15 downto 0); -- registers reg : out t_reg_bus ; strobe40_i : in std_logic ; outsigs_o : out std_logic_vector (15 downto 0); dbg_outsigs_i : in std_logic_vector (15 downto 0); clk_ext_on_i : in std_logic ; link_idly_i : in std_logic_vector (67 downto 0); dbg_count_o : out std_logic_vector (7 downto 0); clocky_leds_o : out std_logic_vector (7 downto 0); lemo_clk_o : out std_logic ; clk_p2_pll_i : in std_logic ; stat_clks_top_i : in std_logic_vector (7 downto 0); tlu_busy : out std_logic ; tlu_tclk : out std_logic ; tlu_trig : in std_logic ; db_wr : out std_logic_vector (31 downto 0); stat_clks_main_i : in std_logic_vector (3 downto 0); clk160ps : in std_logic ; clk160 : in std_logic ; tog20_i : in std_logic ; s20_i : in std_logic ; tlu_reset : in std_logic ; com_abc_o : out std_logic ; strm_reg_o : out slv16_array (143 downto 0); -- In link4x_i : in slv4_array (67 downto 0); tdc_calib_edge0_i : in std_logic ; tdc_counter1_i : in std_logic_vector (31 downto 0); tdc_counter2_i : in std_logic_vector (31 downto 0); tdc_data_i : in std_logic_vector (39 downto 0); tdc_new_i : in std_logic ; trid_tlu_new_o : out std_logic ; command_o : out std_logic_vector (15 downto 0); dbg_oc_start_i : in std_logic ; oc_dack_no : out std_logic ; -- hsio oc bus oc_data_i : in std_logic_vector (15 downto 0); oc_valid_i : in std_logic ; rst_ocb_i : in std_logic ); end component; component rx_packet_decoder port ( -- rx ll fifo interface rx_lls_i : in t_llsrc ; rx_lld_o : out std_logic ; -- decoded out (for debug) rx_magicn_o : out slv16 ; rx_seq_o : out slv16 ; rx_len_o : out slv16 ; rx_cbcnt_o : out slv16 ; rx_opcode_o : out slv16 ; rx_ocseq_o : out slv16 ; rx_size_o : out slv16 ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- Core signals - oc bus, resets oc_data_o : out slv16 ; oc_valid_o : out std_logic ; oc_dack_ni : in std_logic ; dbg_oc_start_o : out std_logic ; rst_ocb_o : out std_logic ; clk80 : in std_logic ; rst80 : in std_logic ; -- infrastructure clk125 : in std_logic ; rst125 : in std_logic ); end component; component ll_automux generic ( LEVELS : integer := 2 ); port ( -- locallink interfaces --in lls_i : in t_llsrc_array ((2**LEVELS)-1 downto 0); lld_o : out std_logic_vector ((2**LEVELS)-1 downto 0); --out lls_o : out t_llsrc ; lld_i : in std_logic ; -- infrastructure rst : in std_logic ; clk : in std_logic ); end component; component ll_pkt_fifo_txcx port ( clk125 : in std_logic; clk80 : in std_logic; core_lls_i : in t_llsrc; net_lld_i : in std_logic; rst125 : in std_logic; rst80 : in std_logic; core_lld_o : out std_logic; net_lls_o : out t_llsrc ); end component; component BUFG port ( I : in std_ulogic; O : out std_ulogic ); end component; component IBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; DIFF_TERM : boolean := FALSE; DQS_BIAS : string := "FALSE"; IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE; IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT" ); port ( I : in std_ulogic; IB : in std_ulogic; O : out std_ulogic ); end component; component IBUFGDS generic ( CAPACITANCE : string := "DONT_CARE"; DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE; IOSTANDARD : string := "DEFAULT" ); port ( I : in std_ulogic; IB : in std_ulogic; O : out std_ulogic ); end component; component OBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "DEFAULT"; SLEW : string := "SLOW" ); port ( I : in std_ulogic; O : out std_ulogic; OB : out std_ulogic ); end component; component ODDR2 generic ( DDR_ALIGNMENT : string := "NONE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port ( C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic := 'H'; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic := 'L'; S : in std_ulogic := 'L'; Q : out std_ulogic ); end component; component led_pulse port ( clk : in std_logic ; i : in std_logic ; tick_i : in std_logic ; rst : in std_logic ; o : out std_logic ); end component; component ticks_gen generic ( SIM_MODE : integer := 0; CLK_MHZ : integer := 80 ); port ( clk : in std_logic; rst : in std_logic; tick_o : out std_logic_vector (MAX_TICTOG downto 0); toggle_o : out std_logic_vector (MAX_TICTOG downto 0) ); end component; component twowire_tri port ( en_i : in std_logic; sck_i : in std_logic; sck_ti : in std_logic; sda_i : in std_logic; sda_ti : in std_logic; sda_o : out std_logic; sck_pin : inout std_logic; sda_pin : inout std_logic ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 3 eb3 fw_version <= conv_std_logic_vector(C_FW_BUILD_NO, 8); -- HDL Embedded Text Block 4 eb4 -- eb3 3 HI <= '1'; LO <= '0'; ZERO2 <= "00"; ZERO4 <= "0000"; ZERO8 <= "00000000"; ZERO13 <= "0000000000000"; ZERO16 <= "0000000000000000"; ZERO64 <= x"0000000000000000"; -- HDL Embedded Text Block 6 eb6 macaddress <= x"e0ddccbbaa0" & sw_i(3 downto 0); -- ModuleWare code(v1.12) for instance 'U_19' of 'buff' led0(4) <= net_leds(0); -- ModuleWare code(v1.12) for instance 'U_20' of 'buff' led0(5) <= net_leds(1); -- ModuleWare code(v1.12) for instance 'U_22' of 'buff' led(7) <= tog(T_2Hz); -- ModuleWare code(v1.12) for instance 'U_23' of 'buff' usbuart_tx_o <= usbuart_rx_i; -- ModuleWare code(v1.12) for instance 'U_31' of 'buff' led0(0) <= tlu_trig; -- ModuleWare code(v1.12) for instance 'U_32' of 'buff' led0(1) <= tlu_tclk; -- ModuleWare code(v1.12) for instance 'U_33' of 'buff' led0(2) <= tlu_busy; -- ModuleWare code(v1.12) for instance 'U_34' of 'buff' led0(3) <= tlu_rst; -- ModuleWare code(v1.12) for instance 'U_36' of 'buff' led0(6) <= net_leds(2); -- ModuleWare code(v1.12) for instance 'U_13' of 'inv' clkn125 <= not(clk125); -- ModuleWare code(v1.12) for instance 'U_1' of 'mux' u_1combo_proc: process(led, fw_version, btn_i) begin case btn_i(5) is when '0' => led_o <= led; when '1' => led_o <= fw_version; when others => led_o <= (others => 'X'); end case; end process u_1combo_proc; -- Instance port mappings. Uidelayprog : iodelay2_prog port map ( reg_i => reg(R_IDELAY), reg_wr_i => db_wr(R_IDELAY), idelay_ctl_o => idelay_ctl, idelay_cal_o => idelay_cal, idelay_busy_i => idelay_busy, rst => rst_dio, clk => clk80 ); Uclkrstblk : itsdaq_clk_rst port map ( clk100_i => clk100_bufg, rst_top_o => rst_top, rst1_o => rst_main, rst2_o => rst_net, clk40_o => clk40, ext_bco_i => clk_in, rst_btn_ni => btn_i(0), rst_no => rst_n, clk_ext_sel_i => LO, ext_por_no => ext_por_n, strobe40_o => s40, clk125_locked_o => clk125_locked, clk125_o => clk125, iserdes_clk_o => iserdes_clk, is_clk_tdc_o => is_clk_tdc, iserdes_strb_o => iserdes_strb, is_strb_tdc_o => is_strb_tdc, clk80_o => clk80, clks_locked_o => clks_locked, s20_o => s20, tog20_o => tog20, rst3_o => rst_dio, rst125_o => rst125, rst_top_125_o => rst_top_125 ); Umain : main_top generic map ( SIM_MODE => SIM_MODE, TOP_ID => 16#0B0B#, ISHSIO => 0, TRIG_TLU_EN => C_TLU_EN, TRIG_TDC_EN => C_TDC_EN, BUILD_NO => C_FW_BUILD_NO, RO_MOD_PRES => C_MOD_PRES, RO_MOD_RAW => C_MOD_RAW, RO_MOD_HST => C_MOD_HST, RO_MOD_TYPE => C_MOD_TYPE, RO_MOD_IDBG => C_MOD_IDBG, RO_TYPE => C_RO_TYPE ) port map ( idc_p3_io => open, sim_dat_lvds_o => open, idc_p4_io => open, idc_p5_io => open, led_status_o => led_status_o, disp_clk_o => open, disp_dat_o => open, disp_rst_no => open, disp_load_no => open, sma_io => open, sw_hex_ni => ZERO4, clk => clk80, clk40 => clk40, spiser_clk_o => open, spiser_com_o => open, sf_stat_word_i => sf_stat_word, tx_ok_i => LO, rx_ok_i => LO, sf_mac_stat_i => sf_mac_stat, sf_syncacq_i => ZERO2, stat_word_cu => stat_word_cu, stat_word_usb => stat_word_usb, ti2c_cvst_no => open, ti2c_cvstt_no => open, tx_lls_o => core_lls, sck_o => sck, sck_to => sck_t, sda_o => sda_tx, sda_to => sda_t, sda_i => sda_rx, rst_in => rst_main, tx_lld_i => core_lld, rawsigs_o => rawsigs, reg => reg, strobe40_i => s40, outsigs_o => outsigs, dbg_outsigs_i => dbg_outsigs, clk_ext_on_i => clk_ext_on, link_idly_i => dbg_link_delayed, dbg_count_o => dbg_count, clocky_leds_o => clocky_leds, lemo_clk_o => open, clk_p2_pll_i => LO, stat_clks_top_i => stat_clks_top, tlu_busy => tlu_busy, tlu_tclk => tlu_tclk, tlu_trig => tlu_trig, db_wr => db_wr, stat_clks_main_i => stat_clks_main, clk160ps => LO, clk160 => LO, tog20_i => tog20, s20_i => s20, tlu_reset => tlu_rst, com_abc_o => com_abc, strm_reg_o => strm_reg, link4x_i => rx_link4x, tdc_calib_edge0_i => tdc_calib_edge0_i, tdc_counter1_i => tdc_counter1, tdc_counter2_i => tdc_counter2, tdc_data_i => tdc_data, tdc_new_i => tdc_new, trid_tlu_new_o => open, command_o => command, dbg_oc_start_i => dbg_oc_start, oc_dack_no => oc_dack_n, oc_data_i => oc_data, oc_valid_i => oc_valid, rst_ocb_i => rst_ocb ); Urxpacketdecoder : rx_packet_decoder port map ( rx_lls_i => rx_lls, rx_lld_o => rx_lld, rx_magicn_o => rx_magicn, rx_seq_o => rx_seq, rx_len_o => rx_len, rx_cbcnt_o => rx_cbcnt, rx_opcode_o => rx_opcode, rx_ocseq_o => rx_opseq, rx_size_o => rx_size, lls_o => lls_top(1), lld_i => lld_top(1), oc_data_o => oc_data, oc_valid_o => oc_valid, oc_dack_ni => oc_dack_n, dbg_oc_start_o => dbg_oc_start, rst_ocb_o => rst_ocb, clk80 => clk80, rst80 => rst_top, clk125 => clk125, rst125 => rst_top_125 ); Ulltop_mux : ll_automux generic map ( LEVELS => 1 ) port map ( lls_i => lls_top, lld_o => lld_top, lls_o => tx_lls, lld_i => tx_lld, rst => rst125, clk => clk125 ); Ullpktfifotxcx : ll_pkt_fifo_txcx port map ( core_lls_i => core_lls, core_lld_o => core_lld, net_lls_o => lls_top(0), net_lld_i => lld_top(0), clk80 => clk80, rst80 => rst_top, clk125 => clk125, rst125 => rst125 ); Ubufg100 : BUFG port map ( O => clk100_bufg, I => clk100_i ); Uddrcgtx : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => eth_gtxclk_o, C0 => clk125, C1 => clkn125, CE => HI, D0 => HI, D1 => LO, R => rst125, S => LO ); Uticksgen : ticks_gen generic map ( SIM_MODE => 0, CLK_MHZ => 80 ) port map ( tick_o => tick, toggle_o => tog, clk => clk80, rst => rst_top ); g0: FOR i IN 0 TO 4 GENERATE U_47 : led_pulse port map ( clk => clk80, i => led0(i), tick_i => tick(T_10Hz), rst => rst_top, o => led(i) ); end generate g0; g6: IF (C_PMOD_TYPE = PTYP_TLU) GENERATE Uibds0 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, DQS_BIAS => "FALSE", IBUF_DELAY_VALUE => "0", IBUF_LOW_PWR => TRUE, IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "DEFAULT" ) port map ( O => tlu_rst_n, I => pmod_ja_io(3), IB => pmod_ja_io(2) ); Uobds0 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "DEFAULT", SLEW => "SLOW" ) port map ( O => pmod_ja_io(5), OB => pmod_ja_io(4), I => tlu_tclk_n ); Uobds1 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "DEFAULT", SLEW => "SLOW" ) port map ( O => pmod_ja_io(7), OB => pmod_ja_io(6), I => tlu_busy_n ); -- ModuleWare code(v1.12) for instance 'U_0' of 'inv' tlu_tclk_n <= not(tlu_tclk); -- ModuleWare code(v1.12) for instance 'U_2' of 'inv' tlu_busy_n <= not(tlu_busy); -- ModuleWare code(v1.12) for instance 'U_3' of 'inv' tlu_trig <= not(tlu_trig_n); -- ModuleWare code(v1.12) for instance 'U_4' of 'inv' tlu_rst <= not(tlu_rst_n); Uibds1 : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, DQS_BIAS => "FALSE", IBUF_DELAY_VALUE => "0", IBUF_LOW_PWR => TRUE, IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "DEFAULT" ) port map ( O => pmod_tlu_trig_n, I => pmod_ja_io(1), IB => pmod_ja_io(0) ); Uiserdestdc : iserdes2_tdc_8b port map ( clk_io_i => is_clk_tdc, strb_i => is_strb_tdc, serdata_i => pmod_tlu_trig_n, pardata_o => open, pardata_no => pardata, CLK_DIV_IN => clk80, IO_RESET => rst_dio ); end generate g6; g7: IF (C_PMOD_TYPE= PTYP_TTC) GENERATE Uibds2 : IBUFGDS generic map ( CAPACITANCE => "DONT_CARE", DIFF_TERM => TRUE, IBUF_DELAY_VALUE => "0", IBUF_LOW_PWR => TRUE, IOSTANDARD => "DEFAULT" ) port map ( O => clk_in, I => pmod_ja_io(5), IB => pmod_ja_io(4) ); Utwowiretri3 : twowire_tri port map ( en_i => HI, sck_i => sck(3), sck_ti => sck_t(3), sck_pin => pmod_ja_io(1), sda_i => sda_tx(3), sda_o => sda_rx(3), sda_ti => sda_t(3), sda_pin => pmod_ja_io(0) ); -- ModuleWare code(v1.12) for instance 'U_18' of 'buff' in_2 <= pmod_ja_io(2); -- ModuleWare code(v1.12) for instance 'U_16' of 'buff' pmod_ja_io(6) <= out_1; -- ModuleWare code(v1.12) for instance 'U_17' of 'buff' pmod_ja_io(7) <= out_2; Uiserdestdc1 : iserdes2_tdc_8b port map ( clk_io_i => is_clk_tdc, strb_i => is_strb_tdc, serdata_i => pmod_ja_io(3), pardata_o => in_1_par, pardata_no => open, CLK_DIV_IN => clk80, IO_RESET => rst_dio ); -- ModuleWare code(v1.12) for instance 'U_21' of 'buff' out_1 <= in_2; -- HDL Embedded Text Block 1 eb1 -- eb1 1 out_2 <= '0' when in_1_par = x"00" else '1'; end generate g7; gnet_top: IF (SIM_MODE=0) GENERATE Ueth : net_top port map ( glbl_rst => rst_net, clk125_i => clk125, dcm_locked_i => clk125_locked, phy_resetn => eth_rst_no, gmii_txd => eth_txd_o, gmii_tx_en => eth_txen_o, gmii_tx_er => eth_txer_o, gmii_tx_clk => eth_txclk_o, gmii_rxd => eth_rxd_i, gmii_rx_dv => eth_rxdv_i, gmii_rx_er => eth_rxer_i, gmii_rx_clk => eth_rxclk_i, gmii_col => eth_col_i, gmii_crs => eth_crs_i, tx_statistics_s => open, rx_statistics_s => open, pause_req_s => LO, fifo_clk_locked_i => clks_locked, fifo_clk_i => clk125, monitor_o => net_leds, rx_lld_i => rx_lld, tx_lls_i => tx_lls, tx_lld_o => tx_lld, rx_lls_o => rx_lls, macaddress_i => macaddress ); end generate gnet_top; gdio_drv: IF (C_DIO_TYPE=DIO_DRV) GENERATE Udio_drv : dio_itsdaq_drv port map ( clk => clk80, clk_io_i => iserdes_clk, coml0_i => outsigs(OS_STT_COM), idelay_cal_i => idelay_cal, idelay_ctl_i => idelay_ctl, iserdes_strb_i => iserdes_strb, l1r3_i => outsigs(OS_STT_L1R), noise_i => outsigs(OS_STT_NOS), rawsigs_i => rawsigs, reg => reg, rst => rst_dio, sck_i => sck(10), sck_t_i => sck_t(10), sda_t_i => sda_t(10), sda_tx_i => sda_tx(10), strobe40_i => s40, dbg_coml0_o => dbg_outsigs(OS_STT_COM), dbg_l1r3_o => dbg_outsigs(OS_STT_L1R), dbg_spare_o => dbg_outsigs(OS_STT_NOS), idelay_busy_o => idelay_busy, rx_link4x_o => rx_link4x(15 downto 0), sda_rx_o => sda_rx(10), vm_nio => vmod_exp_nio, vm_pio => vmod_exp_pio ); end generate gdio_drv; gdio_hvcsv1: IF (C_DIO_TYPE=DIO_HVCSV1) GENERATE Udio_hvcsv1 : dio_cmos_mbh port map ( clk => clk80, clk160 => clk160, clk_io_i => iserdes_clk, idelay_cal_i => idelay_cal, idelay_ctl_i => idelay_ctl, iserdes_strb_i => iserdes_strb, rawsigs_i => rawsigs, reg => reg, rst => rst_dio, strobe40_i => s40, tlu_busy => tlu_busy, tlu_rst => tlu_rst, tlu_tclk => tlu_tclk, tlu_trig => tlu_trig, tog20_i => tog20, idelay_busy_o => idelay_busy, rx_link4x_o => rx_link4x(15 downto 0), v_nio => vmod_exp_nio, v_pio => vmod_exp_pio ); end generate gdio_hvcsv1; gdio_idc: IF (C_DIO_TYPE=DIO_IDC) GENERATE Udio_idc : dio_vib_idc port map ( clk => clk80, clk_io_i => iserdes_clk, com_i => outsigs(OS_STT_COM), idelay_cal_i => idelay_cal, idelay_ctl_i => idelay_ctl, iserdes_strb_i => iserdes_strb, l1r_i => outsigs(OS_STT_L1R), rawcom_en_com_i => reg(R_COM_ENA)(B_J37_COM_EN), rawcom_en_l1r_i => reg(R_COM_ENA)(B_COM_J37_L1), rawcom_en_rst_i => reg(R_COM_ENA)(B_COM_J37_RST), rawcom_i => LO, rawsigs_i => rawsigs, reg => reg, reset_i => outsigs(OS_STT_NOS), rst => rst_dio, strm_reg_i => strm_reg, strobe40_i => s40, tlu_busy => tlu_busy, tlu_rst => tlu_rst, tlu_tclk => tlu_tclk, tlu_trig => tlu_trig, dbg_com_o => dbg_outsigs(OS_STT_COM), dbg_l1r_o => dbg_outsigs(OS_STT_L1R), dbg_reset_o => dbg_outsigs(OS_STT_NOS), idelay_busy_o => idelay_busy, rx_link4x_o => rx_link4x(15 downto 0), vm_nio => vmod_exp_nio, vm_pio => vmod_exp_pio ); end generate gdio_idc; gnet_top_sim: IF (SIM_MODE=1) GENERATE -- HDL Embedded Text Block 2 eb2 -- eb2 2 rx_lls <= sim_rx_lls_i; sim_rx_lld_o <= rx_lld; sim_tx_lls_o <= tx_lls; tx_lld <= sim_tx_lld_i; -- ModuleWare code(v1.12) for instance 'U_5' of 'buff' sim_iserdes_clk_o <= iserdes_clk; -- ModuleWare code(v1.12) for instance 'U_6' of 'buff' sim_clk80_o <= clk80; -- ModuleWare code(v1.12) for instance 'U_7' of 'buff' sim_rst_top_o <= rst_top; -- ModuleWare code(v1.12) for instance 'U_8' of 'buff' sim_clk40_o <= clk40; -- ModuleWare code(v1.12) for instance 'U_9' of 'buff' sim_clk125_o <= clk125; -- ModuleWare code(v1.12) for instance 'U_10' of 'buff' sim_rst125_o <= rst125; end generate gnet_top_sim; gdio_abcn: IF (C_DIO_TYPE=DIO_ABCN) GENERATE Udio_abcn : dio_vib_abcn port map ( clk => clk80, clk_io_i => iserdes_clk, com_i => outsigs(OS_ID0_COM), idelay_cal_i => idelay_cal, idelay_ctl_i => idelay_ctl, iserdes_strb_i => iserdes_strb, l1r_i => outsigs(OS_ID0_L1R), rawcom_en_com_i => reg(R_COM_ENA)(B_J37_COM_EN), rawcom_en_l1r_i => reg(R_COM_ENA)(B_COM_J37_L1), rawcom_en_rst_i => reg(R_COM_ENA)(B_COM_J37_RST), rawcom_i => com_abc, rawsigs_i => rawsigs, reg => reg, reset_i => outsigs(OS_ID0_RST), rst => rst_dio, strm_reg_i => strm_reg, strobe40_i => s40, tlu_busy => tlu_busy, tlu_rst => tlu_rst, tlu_tclk => tlu_tclk, tlu_trig => tlu_trig, dbg_com_o => dbg_outsigs(OS_STT_COM), dbg_l1r_o => dbg_outsigs(OS_STT_L1R), dbg_reset_o => dbg_outsigs(OS_STT_NOS), idelay_busy_o => idelay_busy, rx_link4x_o => rx_link4x(15 downto 0), vm_nio => vmod_exp_nio, vm_pio => vmod_exp_pio ); end generate gdio_abcn; end struct;