-- Create fully synchronous reset in the fifo clock domain.
   gen_fifo_reset : process (fifo_clk_i)
   begin
     if fifo_clk_i'event and fifo_clk_i = '1' then
       if fifo_clk_reset_int = '1' then
         fifo_pre_resetn   <= '0';
         fifo_resetn       <= '0';
       else
         fifo_pre_resetn   <= '1';
         fifo_resetn       <= fifo_pre_resetn;
       end if;
     end if;
   end process gen_fifo_reset;

fifo_reset <= not(fifo_resetn);