-----------------
   -- PHY reset
   -- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
   -- this is derived using the 125MHz available and a 6 bit counter
   gen_phy_reset : process (gtx_clk_bufg)
   begin
     if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
       if glbl_rst_intn = '0' then
         phy_resetn_int       <= '0';
         --phy_reset_count      <= (others => '0');
         phy_reset_count      <= 0;
       else
          --if phy_reset_count /= "111111" then
          if phy_reset_count /= 63 then
             --phy_reset_count <= phy_reset_count + "000001";
             phy_reset_count <= phy_reset_count + 1;
          else
             phy_resetn_int   <= '1';
          end if;
       end if;
     end if;
   end process gen_phy_reset;