Generation Settings
| Component declarations | yes |
| Configurations | in separate file |
| add pragmas |
| exclude view name |
Declarations
Ports:
-- asynchronous reset
glbl_rst : std_logic
-- 200MHz clock input from board
--***clk_in_p : in std_logic;
--***clk_in_n : in std_logic;
clk125_i : std_logic --***
dcm_locked_i : std_logic --***
phy_resetn : std_logic
-- GMII Interface
-----------------
gmii_txd : std_logic_vector(7 downto 0)
gmii_tx_en : std_logic
gmii_tx_er : std_logic
gmii_tx_clk : std_logic
gmii_rxd : std_logic_vector(7 downto 0)
gmii_rx_dv : std_logic
gmii_rx_er : std_logic
gmii_rx_clk : std_logic
gmii_col : std_logic
gmii_crs : std_logic
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : std_logic
rx_statistics_s : std_logic
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : std_logic
fifo_clk_i : std_logic -- clock to be sync'ed to
fifo_clk_locked_i : std_logic
monitor_o : std_logic_vector(3 downto 0)
rx_lld_i : std_logic
tx_lls_i : t_llsrc
tx_lld_o : std_logic
rx_lls_o : t_llsrc
macaddress_i : std_logic_vector(47 DOWNTO 0)
Diagram Signals:
------------------------------------------------------------------------------
-- Constants used in this top level wrapper.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal gtx_clk_bufg : std_logic
signal rx_mac_aclk : std_logic
signal tx_mac_aclk : std_logic
-- resets (and reset generation)
signal vector_reset_int : std_logic
signal vector_resetn : std_logic := '0'
signal rx_reset : std_logic
signal tx_reset : std_logic
signal dcm_locked : std_logic
signal glbl_rst_int : std_logic
signal glbl_rst_intn : std_logic
signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0)
signal rx_axis_fifo_tvalid : std_logic
signal rx_axis_fifo_tlast : std_logic
signal rx_axis_fifo_tready : std_logic
signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0)
signal tx_axis_fifo_tvalid : std_logic
signal tx_axis_fifo_tlast : std_logic
signal tx_axis_fifo_tready : std_logic
-- RX Statistics serialisation signals
signal rx_statistics_valid : std_logic
signal rx_statistics_vector : std_logic_vector(27 downto 0)
signal rx_stats_toggle : std_logic := '0'
signal rx_stats_toggle_sync : std_logic
-- TX Statistics serialisation signals
signal tx_statistics_valid : std_logic
signal tx_statistics_vector : std_logic_vector(31 downto 0)
signal pause_req : std_logic
signal pause_val : std_logic_vector(15 downto 0)
signal rx_configuration_vector : std_logic_vector(79 downto 0)
signal tx_configuration_vector : std_logic_vector(79 downto 0)
-- signal tie offs
signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0') -- not used in this example
signal HI : std_logic
signal ZERO2 : std_logic_vector(1 downto 0)
signal ZERO4 : std_logic_vector(3 downto 0)
signal ZERO8 : std_logic_vector(7 downto 0)
signal ZERO13 : std_logic_vector(12 downto 0)
signal ZERO16 : std_logic_vector(15 downto 0)
signal ZERO64 : std_logic_vector(63 downto 0)
signal LO : std_logic
signal HILO : std_logic_vector(1 downto 0)
------------------------------------------------------------------------------
-- Constants used in this top level wrapper.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal s_axi_aclk : std_logic
signal pause_shift : std_logic_vector(17 downto 0)
signal phy_reset_count : integer RANGE 0 to 63
signal phy_resetn_int : std_logic
signal tx_stats_shift : std_logic_vector(33 downto 0)
signal rx_stats_shift : std_logic_vector(29 downto 0)
signal rx_stats_toggle_sync_reg : std_logic
signal vector_pre_resetn : std_logic := '0'
-- TX Statistics serialisation signals
signal tx_statistics_valid_reg : std_logic
-- RX Statistics serialisation signals
signal rx_stats : std_logic_vector(27 downto 0)
-- RX Statistics serialisation signals
signal rx_statistics_valid_reg : std_logic
signal fifo_clk_reset_int : std_logic
signal fifo_pre_resetn : std_logic
signal fifo_resetn : std_logic
signal fifo_reset : std_logic
signal net_data : std_logic_vector(15 DOWNTO 0)
signal net_eof : std_logic
signal net_sof : std_logic
signal net_src_rdy : std_logic
signal net_dst_rdy : std_logic
signal rx_src_mac : std_logic_vector(47 downto 0)
signal tx_sof : std_logic
signal tx_eof : std_logic
signal tx_src_rdy : std_logic
signal tx_data : std_logic_vector(15 DOWNTO 0)
signal rx_data : std_logic_vector(15 DOWNTO 0)
signal rx_dst_rdy : std_logic
signal tx_dst_rdy : std_logic
signal rx_src_rdy : std_logic
signal rx_eof : std_logic
signal rx_sof : std_logic
signal txll_src_rdy_net : std_logic
signal txll_eof_net : std_logic
signal txll_sof_net : std_logic
signal txll_dst_rdy_net : std_logic
-- net client side (output) interface
signal txll_data_net : std_logic_vector(15 DOWNTO 0)
signal local_fifo_reset0 : std_logic
signal rxtx_reset : std_logic
signal local_fifo_reset1 : std_logic
signal macaddr_byte_reversed : std_logic_vector(47 DOWNTO 0)
Pre User:
Post User:
attribute KEEP : string;
attribute KEEP of pause_req : signal is "true";
attribute KEEP of pause_val : signal is "true";
attribute KEEP of rx_stats_shift : signal is "true";
attribute KEEP of tx_stats_shift : signal is "true";
Package List
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library utils;
use utils.pkg_types.all;
Bundles