Generation Settings
| Component declarations | yes |
| Configurations | in separate file |
| add pragmas |
| exclude view name |
Declarations
Ports:
reset_o : std_ulogic
reset_no : std_ulogic
clk : std_ulogic
ready_i : std_logic
Diagram Signals:
signal LO : std_ulogic
signal pre_rst : std_logic
signal not_ready : std_logic
signal rst_latch_n : std_ulogic
signal srl_tap : std_logic_vector(3 DOWNTO 0) -- ID0_1B (J33.12) ID0_1B_BUF (J26.B4)
Pre User:
Post User:
Package List
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Bundles