-- VHDL Entity atlys.xilinx_reset.symbol
--
-- Created:
--          by - warren.warren (mbb)
--          at - 07:43:11 08/02/13
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xilinx_reset is
   generic(
      PIPE_LEN : integer := 15
   );
   port(
      clk      : in     std_ulogic;
      ready_i  : in     std_logic;
      reset_no : out    std_ulogic;
      reset_o  : out    std_ulogic
   );

-- Declarations

end xilinx_reset ;

--
-- VHDL Architecture atlys.xilinx_reset.struct
--
-- Created:
--          by - warren.warren (mbb)
--          at - 07:43:11 08/02/13
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


architecture struct of xilinx_reset is

   -- Architecture declarations

   -- Internal signal declarations
   signal LO          : std_ulogic;
   signal not_ready   : std_logic;
   signal pre_rst     : std_logic;
   signal rst_latch_n : std_ulogic;
   signal srl_tap     : std_logic_vector(3 downto 0);    -- ID0_1B (J33.12) ID0_1B_BUF (J26.B4)

   -- Implicit buffer signal declarations
   signal reset_o_internal : std_ulogic;


   -- Component Declarations
   component FDCP
   generic (
      INIT : bit := '0'
   );
   port (
      C   : in     std_ulogic;
      CLR : in     std_ulogic;
      D   : in     std_ulogic;
      PRE : in     std_ulogic;
      Q   : out    std_ulogic
   );
   end component;
   component SRL16
   generic (
      INIT : bit_vector := X"0000"
   );
   port (
      A0  : in     STD_ULOGIC;
      A1  : in     STD_ULOGIC;
      A2  : in     STD_ULOGIC;
      A3  : in     STD_ULOGIC;
      CLK : in     STD_ULOGIC;
      D   : in     STD_ULOGIC;
      Q   : out    STD_ULOGIC
   );
   end component;
   component m_power
   port (
      hi : out    std_logic ;
      lo : out    std_logic
   );
   end component;


begin
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   -- eb1 1                                        
   srl_tap <= conv_std_logic_vector(PIPE_LEN, 4);


   -- ModuleWare code(v1.12) for instance 'U_0' of 'inv'
   reset_no <= not(reset_o_internal);

   -- ModuleWare code(v1.12) for instance 'U_1' of 'inv'
   not_ready <= not(ready_i);

   -- ModuleWare code(v1.12) for instance 'U_4' of 'or'
   reset_o_internal <= not(rst_latch_n) or pre_rst;

   -- Instance port mappings.
   Ufdcp : FDCP
      generic map (
         INIT => '0'
      )
      port map (
         Q   => rst_latch_n,
         C   => LO,
         CLR => not_ready,
         D   => LO,
         PRE => pre_rst
      );
   Usrl16 : SRL16
      generic map (
         INIT => X"FFFF"
      )
      port map (
         Q   => pre_rst,
         A0  => srl_tap(0),
         A1  => srl_tap(1),
         A2  => srl_tap(2),
         A3  => srl_tap(3),
         CLK => clk,
         D   => not_ready
      );
   Umpower : m_power
      port map (
         hi => open,
         lo => LO
      );

   -- Implicit buffered output assignments
   reset_o <= reset_o_internal;

end struct;