-- VHDL Entity hsio.control_top.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 10:46:33 05/27/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity control_top is port( c_lld : in std_logic_vector (15 downto 0); clk : in std_logic; -- hsio oc bus oc_data_i : in std_logic_vector (15 downto 0); oc_valid_i : in std_logic; rst : in std_logic; rst_ocb_i : in std_logic; s40 : in std_logic; sda_i : in slv16; -- status words in stat_i : in slv16_array (31 downto 0); tick_i : in std_logic_vector (MAX_TICTOG downto 0); tog20_i : in std_logic; trg_all_mask_i : in std_logic_vector (15 downto 0); c_lls : out t_llsrc_array (15 downto 0); com_ocrawcom_o : out std_logic; -- payload output command_o : out std_logic_vector (15 downto 0); db_data_o : out std_logic_vector (15 downto 0); db_wr_o : out std_logic_vector (31 downto 0); oc_dack_no : out std_logic; ocraw_start_o : out std_logic; rawsigs_o : out std_logic_vector (15 downto 0); -- registers reg_o : out t_reg_bus; rst_disp_o : out std_logic; rst_feo_o : out std_logic; rst_netrx_o : out std_logic; rst_nettx_o : out std_logic; rst_ro_o : out std_logic; rst_trig_o : out std_logic; sck_o : out slv16; sck_to : out slv16; sda_o : out slv16; sda_to : out slv16; spiser_clk_o : out std_logic; -- payload output spiser_com_o : out std_logic; sq_addr_o : out std_logic_vector (15 downto 0); sq_stat_o : out std_logic_vector (7 downto 0); strm_cmd_o : out slv16_array (143 downto 0); strm_reg_o : out slv16_array (143 downto 0); -- streams interface strm_req_stat_o : out std_logic_vector (143 downto 0); ti2c_cvst_no : out std_logic_vector (2 downto 0); ti2c_cvstt_no : out std_logic_vector (2 downto 0) ); -- Declarations end control_top ; -- -- VHDL Architecture hsio.control_top.struct -- -- Created: -- by - warren.warren (mbb) -- at - 10:46:33 05/27/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; use ieee.numeric_std.all; --library vga; --use vga.pkg_vga.all; architecture struct of control_top is -- Architecture declarations -- Internal signal declarations signal HI : std_logic; signal com_ocrawcom : std_logic; -- payload output signal command : std_logic_vector(15 downto 0); signal db_data : std_logic_vector(15 downto 0); signal db_wr : std_logic_vector(31 downto 0); signal ocrawcom_start : std_logic; signal ocrawsigs_start : std_logic; signal ocseqsigs_start : std_logic; signal raws_running_o : std_logic; signal rawsigs : std_logic_vector(15 downto 0); -- registers signal reg : t_reg_bus; signal reg_sigs_idle : std_logic_vector(15 downto 0); signal scan_en_d : std_logic; signal scan_en_q : std_logic_vector(2 downto 0); signal scan_start : std_logic; signal seq_running : std_logic; signal seqsigs : std_logic_vector(15 downto 0); signal sigs_and : std_logic_vector(15 downto 0); signal sigs_or : std_logic_vector(15 downto 0); signal sigs_running : std_logic; -- payload functions signal sink_sigs_i : std_logic_vector(15 downto 0); -- Implicit buffer signal declarations signal oc_dack_no_internal : std_logic; -- Component Declarations component ocb_command port ( -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- payload output command_o : out slv16 ; rst_ro_o : out std_logic ; rst_trig_o : out std_logic ; --rst_ocb_o : out std_logic; rst_feo_o : out std_logic ; rst_disp_o : out std_logic ; rst_nettx_o : out std_logic ; rst_netrx_o : out std_logic ; slow_reset_tick_i : in std_logic ; -- infrastructure clk : in std_logic ; rst : in std_logic ); end component; component ocb_echo_watchdog port ( -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_nio : inout std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- infrastructure tick_4hz_i : in std_logic ; clk : in std_logic ; rst : in std_logic ); end component; component ocb_rawcom port ( -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- payload functions abc_com_o : out std_logic ; ocrawcom_start_o : out std_logic ; pattern_go_i : in std_logic ; -- infrastructure strobe40_i : in std_logic ; clk : in std_logic ; rst : in std_logic ); end component; component ocb_rawseq port ( running_o : out std_logic ; reg_sigs_idle_i : in slv16 ; -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- payload functions sigs_o : out std_logic_vector (15 downto 0); pattern_go_i : in std_logic ; reg_sq_ctl_i : in std_logic_vector (15 downto 0); sq_stat_o : out std_logic_vector (7 downto 0); sq_addr_o : out std_logic_vector (15 downto 0); -- infrastructure s40_i : in std_logic ; tog20_i : in std_logic ; clk : in std_logic ; rst : in std_logic ; ocrawseq_start_o : out std_logic ); end component; component ocb_rawsigs port ( running_o : out std_logic ; reg_sigs_idle_i : in std_logic_vector (15 downto 0); --dl0_delay_i : in std_logic_vector (15 downto 0); --dl0_en_i : in std_logic; trg_all_mask_i : in std_logic_vector (15 downto 0); -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- payload functions sigs_o : out std_logic_vector (15 downto 0); pattern_go_i : in std_logic ; -- infrastructure s40_i : in std_logic ; tog20_i : in std_logic ; clk : in std_logic ; rst : in std_logic ; ocrawsigs_start_o : out std_logic ); end component; component ocb_regblock port ( -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- registers reg_o : out t_reg_bus ; db_wr_o : out slv32 ; db_data_o : out slv16 ; -- infrastructure clk : in std_logic ; rst : in std_logic ); end component; component ocb_sink port ( clk : in std_logic; lld_i : in std_logic; oc_data_i : in slv16; oc_valid_i : in std_logic; rst : in std_logic; s40 : in std_logic; sigs_i : in std_logic_vector (15 downto 0); sink_go_i : in std_logic; lls_o : out t_llsrc; oc_dack_no : out std_logic ); end component; component ocb_statread port ( -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- status words in stat_i : in slv16_array (31 downto 0); -- infrastructure clk : in std_logic ; rst : in std_logic ); end component; component ocb_streams generic ( NSTREAMS : integer := 16 ); port ( -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- streams interface strm_req_stat_o : out std_logic_vector ((NSTREAMS-1) downto 0); strm_reg_o : out slv16_array ((NSTREAMS-1) downto 0); strm_cmd_o : out slv16_array ((NSTREAMS-1) downto 0); -- infrastructure clk : in std_logic ; rst : in std_logic ); end component; component ocb_twowire port ( --tw_exec_i : in std_logic; -- oc rx interface oc_valid_i : in std_logic ; oc_data_i : in slv16 ; oc_dack_no : out std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- serialiser tick_400khz_i : in std_logic ; --100kHz tick_40khz_i : in std_logic ; -- 10kHz tick_4khz_i : in std_logic ; -- 1kHz wdog_tick_i : in std_logic ; sck_dbg_o : out std_logic ; sda_dbg_o : out std_logic ; sda_in_dbg_o : out std_logic ; sda_t_dbg_o : out std_logic ; sck_o : out slv16 ; sck_to : out slv16 ; sda_o : out slv16 ; sda_to : out slv16 ; sda_i : in slv16 ; -- infrastructure clk : in std_logic ; rst : in std_logic ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 1 eb1 -- eb1 1 reg_o <= reg; -- HDL Embedded Text Block 2 eb2 -- eb2 2 scan_en_d <= not(reg(R_CONTROL1)(CTL_RAWOUT_EN)) and reg(R_CONTROL1)(CTL_DRV_SP0); scan_en_q(0) <= scan_en_d when rising_edge(clk); scan_en_q(1) <= scan_en_q(0) when rising_edge(clk); scan_en_q(2) <= scan_en_q(1) when rising_edge(clk); scan_start <= '1' when ((scan_en_q(1 downto 0) = "01") or (scan_en_q(2 downto 1) = "01")) else '0'; -- HDL Embedded Text Block 3 eb3 -- eb2 2 reg_sigs_idle <= reg(R_SIGS_IDLE); -- ModuleWare code(v1.12) for instance 'U_5' of 'buff' ti2c_cvst_no(0) <= HI; -- ModuleWare code(v1.12) for instance 'U_6' of 'buff' ti2c_cvst_no(1) <= HI; -- ModuleWare code(v1.12) for instance 'U_7' of 'buff' ti2c_cvst_no(2) <= HI; -- ModuleWare code(v1.12) for instance 'U_8' of 'buff' ti2c_cvstt_no(0) <= HI; -- ModuleWare code(v1.12) for instance 'U_9' of 'buff' ti2c_cvstt_no(1) <= HI; -- ModuleWare code(v1.12) for instance 'U_10' of 'buff' ti2c_cvstt_no(2) <= HI; -- ModuleWare code(v1.12) for instance 'U_11' of 'buff' command_o <= command; -- ModuleWare code(v1.12) for instance 'U_12' of 'buff' com_ocrawcom_o <= com_ocrawcom; -- ModuleWare code(v1.12) for instance 'U_14' of 'buff' db_data_o <= db_data; -- ModuleWare code(v1.12) for instance 'U_15' of 'buff' db_wr_o <= db_wr; -- ModuleWare code(v1.12) for instance 'U_0' of 'or' ocraw_start_o <= ocrawcom_start or ocrawsigs_start or ocseqsigs_start or scan_start; -- ModuleWare code(v1.12) for instance 'U_4' of 'or' raws_running_o <= sigs_running or seq_running; -- Instance port mappings. Uocbcommand : ocb_command port map ( oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(7), lld_i => c_lld(7), command_o => command, rst_ro_o => rst_ro_o, rst_trig_o => rst_trig_o, rst_feo_o => rst_feo_o, rst_disp_o => rst_disp_o, rst_nettx_o => rst_nettx_o, rst_netrx_o => rst_netrx_o, slow_reset_tick_i => tick_i(T_1MHz), clk => clk, rst => rst_ocb_i ); Uocbecho : ocb_echo_watchdog port map ( oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_nio => oc_dack_no_internal, lls_o => c_lls(4), lld_i => c_lld(4), tick_4hz_i => tick_i(T_2Hz), clk => clk, rst => rst_ocb_i ); Uocbrawcom : ocb_rawcom port map ( oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(1), lld_i => c_lld(1), abc_com_o => com_ocrawcom, ocrawcom_start_o => ocrawcom_start, pattern_go_i => command(CMD_RCPATT_GO), strobe40_i => s40, clk => clk, rst => rst_ocb_i ); Uocbrawseq : ocb_rawseq port map ( running_o => seq_running, reg_sigs_idle_i => reg(R_SIGS_IDLE), oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(9), lld_i => c_lld(9), sigs_o => seqsigs, pattern_go_i => command(CMD_SQPATT_GO), reg_sq_ctl_i => reg(R_SQ_CTL), sq_stat_o => sq_stat_o, sq_addr_o => sq_addr_o, s40_i => s40, tog20_i => tog20_i, clk => clk, rst => rst_ocb_i, ocrawseq_start_o => ocseqsigs_start ); Uocbrawsigs : ocb_rawsigs port map ( running_o => sigs_running, reg_sigs_idle_i => reg(R_SIGS_IDLE), trg_all_mask_i => trg_all_mask_i, oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(8), lld_i => c_lld(8), sigs_o => rawsigs, pattern_go_i => command(CMD_RSPATT_GO), s40_i => s40, tog20_i => tog20_i, clk => clk, rst => rst_ocb_i, ocrawsigs_start_o => ocrawsigs_start ); Uocbregblock : ocb_regblock port map ( lls_o => c_lls(2), lld_i => c_lld(2), oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, reg_o => reg, db_wr_o => db_wr, db_data_o => db_data, clk => clk, rst => rst_ocb_i ); Uocbstatread : ocb_statread port map ( oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(3), lld_i => c_lld(3), stat_i => stat_i, clk => clk, rst => rst_ocb_i ); Uocbstreams : ocb_streams generic map ( NSTREAMS => 144 ) port map ( lls_o => c_lls(5), lld_i => c_lld(5), oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, strm_req_stat_o => strm_req_stat_o, strm_reg_o => strm_reg_o, strm_cmd_o => strm_cmd_o, clk => clk, rst => rst_ocb_i ); Uocbtwowire : ocb_twowire port map ( oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(6), lld_i => c_lld(6), tick_400khz_i => tick_i(T_400kHz), tick_40khz_i => tick_i(T_40kHz), tick_4khz_i => tick_i(T_4kHz), wdog_tick_i => tick_i(T_5Hz), sck_dbg_o => open, sda_dbg_o => open, sda_in_dbg_o => open, sda_t_dbg_o => open, sck_o => sck_o, sck_to => sck_to, sda_o => sda_o, sda_to => sda_to, sda_i => sda_i, clk => clk, rst => rst_ocb_i ); g0: FOR n IN 0 TO 15 GENERATE -- ModuleWare code(v1.12) for instance 'U_1' of 'or' sigs_or(n) <= rawsigs(n) or seqsigs(n); -- ModuleWare code(v1.12) for instance 'U_2' of 'and' sigs_and(n) <= rawsigs(n) and seqsigs(n); -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' u_3combo_proc: process(sigs_or, sigs_and, reg_sigs_idle) begin case reg_sigs_idle(n) is when '0' => rawsigs_o(n) <= sigs_or(n); when '1' => rawsigs_o(n) <= sigs_and(n); when others => rawsigs_o(n) <= 'X'; end case; end process u_3combo_proc; end generate g0; g2: IF 1=2 GENERATE Uocbsink : ocb_sink port map ( oc_valid_i => oc_valid_i, oc_data_i => oc_data_i, oc_dack_no => oc_dack_no_internal, lls_o => c_lls(10), lld_i => c_lld(10), sigs_i => sink_sigs_i, sink_go_i => command(CMD_SINK_GO), s40 => s40, clk => clk, rst => rst_ocb_i ); end generate g2; -- Implicit buffered output assignments oc_dack_no <= oc_dack_no_internal; end struct;