-- VHDL Entity hsio.main_top.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 11:22:11 05/23/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity main_top is generic( SIM_MODE : integer := 0; TOP_ID : integer := 16#0C02#; ISHSIO : integer := 1; TRIG_TLU_EN : integer := 1; TRIG_TDC_EN : integer := 1; BUILD_NO : integer := 1; RO_MOD_PRES : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_RAW : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_HST : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_TYPE : std_logic_vector(35 downto 0) := x"000000000"; RO_MOD_IDBG : std_logic_vector(35 downto 0) := x"000000000"; RO_TYPE : integer := 99 ); port( idc_p3_io : inout std_logic_vector (31 downto 0); --IDC_P3 sim_dat_lvds_o : out std_logic_vector (31 downto 0); idc_p4_io : inout std_logic_vector (31 downto 0); --IDC_P4 idc_p5_io : out std_logic_vector (31 downto 0); --IDC_P5 led_status_o : out std_logic; --LED_FPGA_STATUS -- DISPLAY disp_clk_o : out std_logic; --DISP_CLK disp_dat_o : out std_logic; --DISP_DAT disp_rst_no : out std_logic; --DISP_RST_N disp_load_no : out std_logic_vector (1 downto 0); --DISP_LOAD1_N sma_io : inout std_logic_vector (8 downto 1); --IDC_P5 sw_hex_ni : in std_logic_vector (3 downto 0); clk : in std_logic; clk40 : in std_logic; spiser_clk_o : out std_logic; -- payload output spiser_com_o : out std_logic; sf_stat_word_i : in slv64_array (1 downto 0); tx_ok_i : in std_logic; -- Client Receiver Interface - EMAC0 rx_ok_i : in std_logic; sf_mac_stat_i : in slv64_array (1 downto 0); sf_syncacq_i : in std_logic_vector (1 downto 0); stat_word_cu : in std_logic_vector (63 downto 0); stat_word_usb : in std_logic_vector (63 downto 0); ti2c_cvst_no : out std_logic_vector (2 downto 0); ti2c_cvstt_no : out std_logic_vector (2 downto 0); tx_lls_o : out t_llsrc; sck_o : out slv16; sck_to : out slv16; sda_o : out slv16; sda_to : out slv16; sda_i : in slv16; rst_in : in std_logic; tx_lld_i : in std_logic; rawsigs_o : out std_logic_vector (15 downto 0); -- registers reg : out t_reg_bus; strobe40_i : in std_logic; outsigs_o : out std_logic_vector (15 downto 0); dbg_outsigs_i : in std_logic_vector (15 downto 0); clk_ext_on_i : in std_logic; link_idly_i : in std_logic_vector (67 downto 0); dbg_count_o : out std_logic_vector (7 downto 0); clocky_leds_o : out std_logic_vector (7 downto 0); lemo_clk_o : out std_logic; clk_p2_pll_i : in std_logic; stat_clks_top_i : in std_logic_vector (7 downto 0); tlu_busy : out std_logic; tlu_tclk : out std_logic; tlu_trig : in std_logic; db_wr : out std_logic_vector (31 downto 0); stat_clks_main_i : in std_logic_vector (3 downto 0); clk160ps : in std_logic; clk160 : in std_logic; tog20_i : in std_logic; s20_i : in std_logic; tlu_reset : in std_logic; com_abc_o : out std_logic; strm_reg_o : out slv16_array (143 downto 0); -- In link4x_i : in slv4_array (67 downto 0); tdc_calib_edge0_i : in std_logic; tdc_counter1_i : in std_logic_vector (31 downto 0); tdc_counter2_i : in std_logic_vector (31 downto 0); tdc_data_i : in std_logic_vector (39 downto 0); tdc_new_i : in std_logic; trid_tlu_new_o : out std_logic; command_o : out std_logic_vector (15 downto 0); dbg_oc_start_i : in std_logic; oc_dack_no : out std_logic; -- hsio oc bus oc_data_i : in std_logic_vector (15 downto 0); oc_valid_i : in std_logic; rst_ocb_i : in std_logic ); -- Declarations end main_top ; -- -- VHDL Architecture hsio.main_top.struct -- -- Created: -- by - warren.warren (mbb) -- at - 11:22:11 05/23/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- -- hds interface_end -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; library hsio; use hsio.pkg_core_globals.all; library utils; use utils.pkg_types.all; architecture struct of main_top is -- Architecture declarations -- Internal signal declarations signal dbg_tlu_reset : std_logic; signal strm_i : std_logic_vector(135 downto 0); signal dbg_clk_p2_pll : std_logic; signal rst : std_logic; -- registers signal dbg_reg : t_reg_bus; signal dbg_com_abc : std_logic; signal com_abc : std_logic; signal l1r_abc : std_logic; signal dbg_l1r_abc : std_logic; signal dbg_strobe40 : std_logic; signal strobe40_n : std_logic; signal strobe40 : std_logic; signal rst_disp : std_logic; signal HI : std_logic; signal LO : std_logic; signal rst_netrx : std_logic; signal dispDigitA : std_logic_vector(7 downto 0); signal dispDigitB : std_logic_vector(7 downto 0); signal dispDigitC : std_logic_vector(7 downto 0); signal dispDigitD : std_logic_vector(7 downto 0); signal dispDigitE : std_logic_vector(7 downto 0); signal dispDigitF : std_logic_vector(7 downto 0); signal dispDigitG : std_logic_vector(7 downto 0); signal dispDigitH : std_logic_vector(7 downto 0); signal dbg_clk156_delayed : std_logic; signal dbg_clk160 : std_logic; signal dbg_clk160ps : std_logic; signal dbg_clk156 : std_logic; signal dbg_clk40 : std_logic; signal dbg_lemo_clk : std_logic; signal dbg_clk : std_logic; signal dispword : std_logic_vector(31 downto 0); signal dbg_trig80 : std_logic; signal dbg_ocraw_start : std_logic; signal dbg_busy_ro : std_logic; signal dbg_twin_open : std_logic; signal dbg_trig_out : std_logic; signal trig_out : std_logic; signal pretrig_out : std_logic; signal trig80 : std_logic; signal db_data : std_logic_vector(15 downto 0); signal com_ocrawcom : std_logic; signal led_trig : std_logic; signal dbg_l1id : slv24; signal l1id : slv24; signal idbg_link_sel : integer range 0 to 255; signal dbg_tdc_calib_edge0 : std_logic; signal tdc_calib_edge0 : std_logic; signal dbg_lemo_link : std_logic; signal dbg_lemo_strm1 : std_logic; signal dbg_lemo_strm0 : std_logic; signal dbg_oe : std_logic; signal dbg_bcid_l1a : std_logic_vector(11 downto 0); signal bcid_l1a : std_logic_vector(11 downto 0); signal bcid : std_logic_vector(11 downto 0); signal sim_dat : std_logic_vector(15 downto 0); signal HSIO_VER : std_logic_vector(31 downto 0); signal ocraw_start : std_logic; signal binmapchar : std_logic_vector(7 downto 0); signal led_rx : std_logic; signal led_tx : std_logic; signal post_rst_5s : std_logic; signal strm_reg : slv16_array(143 downto 0); -- streams interface signal strm_req_stat : std_logic_vector(143 downto 0); signal strm_cmd : slv16_array(143 downto 0); -- status words in signal stat : slv16_array(31 downto 0); signal command : std_logic_vector(15 downto 0); signal tb_bcount : std_logic_vector(15 downto 0); signal tb_tcount : std_logic_vector(15 downto 0); signal rst_ro : std_logic; signal rst_trig : std_logic; signal trig40 : std_logic; signal dbg_lemo_trig : std_logic; signal lemo_trig : std_logic; signal lemo_clk : std_logic; signal lemo_clk_in : std_logic; signal dbg_strm : std_logic_vector(135 downto 0); --ht_delta_max_i : in slv6; signal busy_ro : std_logic; signal pattern_go : std_logic; signal tick : std_logic_vector(34 downto 0); signal rst_nettx : std_logic; signal s_lld : std_logic_vector(255 downto 0); signal s_lls : t_llsrc_array(255 downto 0); signal build_no_slv : std_logic_vector(15 downto 0); signal epoc_secs : std_logic_vector(31 downto 0); signal rawsigs : std_logic_vector(15 downto 0); signal twin_open : std_logic; signal sim_count : std_logic_vector(7 downto 0); signal dbg_trig_ext : std_logic; signal SPY_STREAM_ID : integer; signal trg_all_mask : std_logic_vector(15 downto 0); signal spy_hold_reg : std_logic_vector(15 downto 0); signal dbg_busy_ext : std_logic; signal busy_ext : std_logic; signal busy_all : std_logic; signal sq_addr : std_logic_vector(15 downto 0); signal sq_stat : std_logic_vector(7 downto 0); signal tb_flags : std_logic_vector(7 downto 0); signal dbg_link_idly : std_logic_vector(67 downto 0); signal led_tlu_trig : std_logic; signal led_tlu_tclk : std_logic; signal led_tlu_busy : std_logic; signal led_ocraw_start : std_logic; signal tog_pll : std_logic_vector(MAX_TICTOG downto 0); signal l0id : std_logic_vector(31 downto 0); signal l0id_l1 : std_logic_vector(7 downto 0); signal lemo_bco_out : std_logic; signal stat_clks_main : std_logic_vector(3 downto 0); signal dbg_tlu_busy : std_logic; signal dbg_tlu_tclk : std_logic; signal dbg_tlu_trig : std_logic; signal tog : std_logic_vector(34 downto 0); signal twin_swap : std_logic; signal twin_clk40 : std_logic; signal twin_clk80 : std_logic; signal clkn80_delayed : std_logic; signal clk40_delayed : std_logic; signal clkn40_delayed : std_logic; signal clk80_delayed : std_logic; signal post_rst_5s_n : std_logic; signal MODULECOUNT : integer; -- Implicit buffer signal declarations signal reg_internal : t_reg_bus; signal tlu_busy_internal : std_logic; signal tlu_tclk_internal : std_logic; attribute KEEP : string; attribute KEEP of dispword : signal is "true"; attribute KEEP of dbg_oe : signal is "true"; --attribute KEEP of sma_io : signal is "true"; --attribute KEEP of idc_p2_io : signal is "true"; --attribute KEEP of idc_p3_io : signal is "true"; --attribute KEEP of idc_p4_io : signal is "true"; --attribute KEEP of idc_p5_io : signal is "true"; -- Note sure if keeping both helps, -- but I doubt it hinders --attribute KEEP of clk40 : signal is "true"; --attribute KEEP of dbg_clk40_delayed : signal is "true"; --attribute KEEP of dbg_clk40 : signal is "true"; --attribute KEEP of clk156 : signal is "true"; --attribute KEEP of dbg_clk156 : signal is "true"; --attribute KEEP of dbg_clk156_delayed : signal is "true"; --attribute KEEP of clk : signal is "true"; --attribute KEEP of dbg_clk : signal is "true"; attribute KEEP of strm_i : signal is "true"; attribute KEEP of dbg_strm : signal is "true"; attribute KEEP of reg : signal is "true"; attribute KEEP of dbg_reg : signal is "true"; attribute KEEP of link_idly_i : signal is "true"; attribute KEEP of dbg_link_idly : signal is "true"; attribute KEEP of dbg_tdc_calib_edge0 : signal is "true"; --attribute KEEP of dbg_tdc_calib_edge1 : signal is "true"; attribute KEEP of twin_open : signal is "true"; attribute KEEP of twin_clk40 : signal is "true"; attribute KEEP of twin_clk80 : signal is "true"; -- Component Declarations component control_top port ( c_lld : in std_logic_vector (15 downto 0); clk : in std_logic ; -- hsio oc bus oc_data_i : in std_logic_vector (15 downto 0); oc_valid_i : in std_logic ; rst : in std_logic ; rst_ocb_i : in std_logic ; s40 : in std_logic ; sda_i : in slv16 ; -- status words in stat_i : in slv16_array (31 downto 0); tick_i : in std_logic_vector (MAX_TICTOG downto 0); tog20_i : in std_logic ; trg_all_mask_i : in std_logic_vector (15 downto 0); c_lls : out t_llsrc_array (15 downto 0); com_ocrawcom_o : out std_logic ; -- payload output command_o : out std_logic_vector (15 downto 0); db_data_o : out std_logic_vector (15 downto 0); db_wr_o : out std_logic_vector (31 downto 0); oc_dack_no : out std_logic ; ocraw_start_o : out std_logic ; rawsigs_o : out std_logic_vector (15 downto 0); -- registers reg_o : out t_reg_bus ; rst_disp_o : out std_logic ; rst_feo_o : out std_logic ; rst_netrx_o : out std_logic ; rst_nettx_o : out std_logic ; rst_ro_o : out std_logic ; rst_trig_o : out std_logic ; sck_o : out slv16 ; sck_to : out slv16 ; sda_o : out slv16 ; sda_to : out slv16 ; spiser_clk_o : out std_logic ; -- payload output spiser_com_o : out std_logic ; sq_addr_o : out std_logic_vector (15 downto 0); sq_stat_o : out std_logic_vector (7 downto 0); strm_cmd_o : out slv16_array (143 downto 0); strm_reg_o : out slv16_array (143 downto 0); -- streams interface strm_req_stat_o : out std_logic_vector (143 downto 0); ti2c_cvst_no : out std_logic_vector (2 downto 0); ti2c_cvstt_no : out std_logic_vector (2 downto 0) ); end component; component disp_binmap port ( --binary_i : in std_logic_vector(3 downto 0); bit0 : in std_logic ; bit1 : in std_logic ; bit2 : in std_logic ; bit3 : in std_logic ; dispchar_o : out std_logic_vector (7 downto 0) ); end component; component disp_top port ( clk : in std_logic; dispDigitA : in std_logic_vector (7 downto 0); dispDigitB : in std_logic_vector (7 downto 0); dispDigitC : in std_logic_vector (7 downto 0); dispDigitD : in std_logic_vector (7 downto 0); dispDigitE : in std_logic_vector (7 downto 0); dispDigitF : in std_logic_vector (7 downto 0); dispDigitG : in std_logic_vector (7 downto 0); dispDigitH : in std_logic_vector (7 downto 0); reset : in std_logic; tick_2khz_i : in std_logic; toggle_2mhz_i : in std_logic; dispClk : out std_logic; dispDat : out std_logic; dispLoadL : out std_logic_vector (1 downto 0); dispRstL : out std_logic ); end component; component readout_top generic ( MOD_PRES : std_logic_vector(35 downto 0) := x"000000000"; MOD_RAW : std_logic_vector(35 downto 0) := x"000000000"; MOD_HST : std_logic_vector(35 downto 0) := x"000000000"; MOD_TYPE : std_logic_vector(35 downto 0) := x"000000000"; MOD_IDBG : std_logic_vector(35 downto 0) := x"000000000"; RO_TYPE : integer := 99 ); port ( bcid_i : in std_logic_vector (11 downto 0); clk : in std_logic ; l1id_i : in std_logic_vector (23 downto 0); -- In link4x_i : in slv4_array (67 downto 0); ocraw_start_i : in std_logic ; -- registers reg : in t_reg_bus ; rst : in std_logic ; s20_i : in std_logic ; s_lld_i : in std_logic_vector (135 downto 0); strm_cmd_i : in slv16_array (143 downto 0); strm_reg_i : in slv16_array (143 downto 0); -- streams interface strm_req_stat_i : in std_logic_vector (143 downto 0); strobe40_i : in std_logic ; tick : in std_logic_vector (MAX_TICTOG downto 0); trig80_i : in std_logic ; --ht_delta_max_i : in slv6; busy_o : out std_logic ; gen13data80_o : out slv2_array (1 downto 0); gen13data_o : out slv2_array (1 downto 0); s_lls_o : out t_llsrc_array (135 downto 0) ); end component; component ro_spy_unit port ( STREAM_ID : in integer ; capture_len_i : in std_logic_vector (15 downto 0); clk : in std_logic ; hold_reg_rst_i : in std_logic ; lld_i : in std_logic ; ocraw_start_i : in std_logic ; rawsigs_i : in std_logic_vector (15 downto 0); reg_spysig_ctl_i : in std_logic_vector (15 downto 0); rst : in std_logic ; sink_go_i : in std_logic ; spy_sig_i : in std_logic_vector (15 downto 0); -- locallink tx interface lls_o : out t_llsrc ; spy_hold_reg_o : out std_logic_vector (15 downto 0) ); end component; component timestamp port ( ts_o : out std_logic_vector (31 downto 0) ); end component; component trigger_top generic ( TLU_EN : integer := 1; TDC_EN : integer := 1 ); port ( busy_ext_i : in std_logic ; busy_ro_i : in std_logic ; clk : in std_logic ; command : in std_logic_vector (15 downto 0); lemo_bcr_i : in std_logic ; lemo_ecr_i : in std_logic ; lemo_trig_i : in std_logic ; lld_i : in std_logic ; ocraw_start_i : in std_logic ; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus ; rst : in std_logic ; s40 : in std_logic ; tdc_data_i : in std_logic_vector (39 downto 0); tdc_new_i : in std_logic ; tick : in std_logic_vector (34 downto 0); tlu_reset_i : in std_logic ; tlu_trig_i : in std_logic ; tog : in std_logic_vector (34 downto 0); twin_open_i : in std_logic ; bcid_l1a_o : out std_logic_vector (11 downto 0); bcid_o : out std_logic_vector (11 downto 0); bcr_all_o : out std_logic ; busy_all_o : out std_logic ; busy_ext_o : out std_logic ; dbg_trig_ext_o : out std_logic ; ecr_all_o : out std_logic ; l0id_l1_o : out std_logic_vector (7 downto 0); l0id_o : out std_logic_vector (31 downto 0); -- locallink tx interface lls_o : out t_llsrc ; outsigs_o : out std_logic_vector (15 downto 0); pretrig_o : out std_logic ; tb_bcount_o : out std_logic_vector (15 downto 0); tb_flags_o : out std_logic_vector (7 downto 0); tb_tcount_o : out std_logic_vector (15 downto 0); tlu_busy_o : out std_logic ; tlu_tclk_o : out std_logic ; trg_all_mask_o : out std_logic_vector (15 downto 0); trid_tlu_new_o : out std_logic ; trig40_o : out std_logic ; trig80_o : out std_logic ; trig_out_o : out std_logic ); end component; component ll_syncmux256 port ( clk : in std_logic ; lld_i : in std_logic ; rst : in std_logic ; s_lls_i : in t_llsrc_array (255 downto 0); lls_o : out t_llsrc ; s_lld_o : out std_logic_vector (255 downto 0); selected_str_o : out std_logic_vector (7 downto 0) ); end component; component BUFR generic ( BUFR_DIVIDE : string := "BYPASS"; SIM_DEVICE : string := "VIRTEX4" ); port ( CE : in std_ulogic; CLR : in std_ulogic; I : in std_ulogic; O : out std_ulogic ); end component; component OBUFDS generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "DEFAULT"; SLEW : string := "SLOW" ); port ( I : in std_ulogic; O : out std_ulogic; OB : out std_ulogic ); end component; component ODDR generic ( DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port ( C : in std_ulogic; CE : in std_ulogic; D1 : in std_ulogic; D2 : in std_ulogic; R : in std_ulogic; S : in std_ulogic; Q : out std_ulogic ); end component; component counter generic ( BITS : integer := 16; ROLLOVER_EN : integer := 1; RST_IS_PRESET : integer := 0 -- reset is preset ); port ( inc_i : in std_logic ; clr_i : in std_logic ; pre_i : in std_logic ; count_o : out std_logic_vector ((BITS-1) downto 0); count_at_max_o : out std_logic ; en_i : in std_logic ; rst : in std_logic ; clk : in std_logic ); end component; component led_pulse port ( clk : in std_logic ; i : in std_logic ; tick_i : in std_logic ; rst : in std_logic ; o : out std_logic ); end component; component m_power port ( hi : out std_logic ; lo : out std_logic ); end component; component ticks_gen generic ( SIM_MODE : integer := 0; CLK_MHZ : integer := 80 ); port ( clk : in std_logic; rst : in std_logic; tick_o : out std_logic_vector (MAX_TICTOG downto 0); toggle_o : out std_logic_vector (MAX_TICTOG downto 0) ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 3 eb3 build_no_slv <= conv_std_logic_vector(BUILD_NO, 16); stat(S_HW_ID) <= conv_std_logic_vector(TOP_ID, 16); -- 0 0x00 stat(S_SANITY) <= x"a510"; -- 1 0x02 stat(S_VERSION) <= conv_std_logic_vector(BUILD_NO, 16); -- 2 0x04 stat(S_MODULECOUNT) <= conv_std_logic_vector(MODULECOUNT, 16); -- 3 0x06 stat(S_TB_TCOUNT) <= tb_tcount; -- 4 0x08 stat(S_TB_BCOUNT) <= tb_bcount; -- 5 0x0a stat(S_TBSQ_FLAGS) <= sq_stat & tb_flags; -- 6 0x0c stat(S_BCID_L1A) <= x"0" & bcid_l1a; -- 7 0x0e stat(S_L0ID_LO) <= l0id(15 downto 0); -- 8 0x10 stat(S_L0ID_HI) <= l0id(31 downto 16); -- 9 0x12 stat(S_SF0_STAT_LO) <= sf_stat_word_i(0)(15 downto 0); -- 10 0x14 stat(S_SF0_STAT_HI) <= sf_stat_word_i(0)(31 downto 16); -- 11 0x16 stat(S_SF1_STAT_LO) <= sf_stat_word_i(1)(15 downto 0); -- 12 0x18 stat(S_SF1_STAT_HI) <= sf_stat_word_i(1)(31 downto 16); -- 13 0x1a stat(S_CU_STAT) <= stat_word_cu(15 downto 0); -- 14 0x1c stat(S_GENSTAT) <= stat_clks_top_i & stat_clks_main_i & "00" & clk_ext_on_i & busy_ro; -- 15 0x1e stat(S_TOP_RAW) <= RO_MOD_RAW(15 downto 0); -- 16 0x20 stat(S_TOP_HST) <= RO_MOD_HST(15 downto 0); -- 17 0x22 stat(S_BOT_RAW) <= RO_MOD_RAW(31 downto 16); -- 18 0x24 stat(S_BOT_HST) <= RO_MOD_HST(31 downto 16); -- 19 0x26 stat(S_IDC_HSTRAW) <= x"0" & RO_MOD_HST(35 downto 32) & x"0" & RO_MOD_RAW(35 downto 32); -- 20 0x28 stat(S_SPY_HOLD_REG) <= spy_hold_reg; -- 21 0x2a stat(S_TIMESTAMP_LO) <= epoc_secs(15 downto 0); -- 22 0x2c stat(S_TIMESTAMP_HI) <= epoc_secs(31 downto 16); -- 23 0x2e stat(S_SQ_ADDR) <= sq_addr; -- 24 0x30 --stat(S_SK_ADDR) <= sk_addr; -- 25 0x32 stat(S_L0ID_L1) <= x"00" & l0id_l1; -- 26 0x34 stat(27) <= tdc_data_i(15 downto 0); -- 27 0x36 stat(28) <= tdc_counter2_i(31 downto 16); -- 28 0x38 stat(29) <= tdc_counter2_i(15 downto 0); -- 29 0x3a stat(30) <= tdc_counter1_i(31 downto 16); -- 30 0x3c stat(31) <= tdc_counter1_i(15 downto 0); -- 31 0x3e MODULECOUNT <= conv_integer(RO_MOD_PRES(35)) + conv_integer(RO_MOD_PRES(34)) + conv_integer(RO_MOD_PRES(33)) + conv_integer(RO_MOD_PRES(32)) + conv_integer(RO_MOD_PRES(31)) + conv_integer(RO_MOD_PRES(30)) + conv_integer(RO_MOD_PRES(29)) + conv_integer(RO_MOD_PRES(28)) + conv_integer(RO_MOD_PRES(27)) + conv_integer(RO_MOD_PRES(26)) + conv_integer(RO_MOD_PRES(25)) + conv_integer(RO_MOD_PRES(24)) + conv_integer(RO_MOD_PRES(23)) + conv_integer(RO_MOD_PRES(22)) + conv_integer(RO_MOD_PRES(21)) + conv_integer(RO_MOD_PRES(20)) + conv_integer(RO_MOD_PRES(19)) + conv_integer(RO_MOD_PRES(18)) + conv_integer(RO_MOD_PRES(17)) + conv_integer(RO_MOD_PRES(16)) + conv_integer(RO_MOD_PRES(15)) + conv_integer(RO_MOD_PRES(14)) + conv_integer(RO_MOD_PRES(13)) + conv_integer(RO_MOD_PRES(12)) + conv_integer(RO_MOD_PRES(11)) + conv_integer(RO_MOD_PRES(10)) + conv_integer(RO_MOD_PRES(9)) + conv_integer(RO_MOD_PRES(8)) + conv_integer(RO_MOD_PRES(7)) + conv_integer(RO_MOD_PRES(6)) + conv_integer(RO_MOD_PRES(5)) + conv_integer(RO_MOD_PRES(4)) + conv_integer(RO_MOD_PRES(3)) + conv_integer(RO_MOD_PRES(2)) + conv_integer(RO_MOD_PRES(1)) + conv_integer(RO_MOD_PRES(0)); -- HDL Embedded Text Block 4 eb4 -- eb4 4 strm_reg_o <= strm_reg; -- HDL Embedded Text Block 8 eb8 -- eb6 6 -- seperate downstream resets rst <= rst_in when rising_edge(clk); -- ModuleWare code(v1.12) for instance 'U_28' of 'and' twin_open <= twin_clk40 and twin_clk80; -- ModuleWare code(v1.12) for instance 'U_0' of 'buff' rawsigs_o <= rawsigs; -- ModuleWare code(v1.12) for instance 'U_1' of 'buff' command_o <= command; -- ModuleWare code(v1.12) for instance 'U_6' of 'buff' com_abc_o <= com_ocrawcom; -- ModuleWare code(v1.12) for instance 'U_60' of 'buff' strobe40 <= strobe40_i; -- ModuleWare code(v1.12) for instance 'U_7' of 'inv' strobe40_n <= not(strobe40_i); -- ModuleWare code(v1.12) for instance 'U_22' of 'mux' u_22combo_proc: process(clkn80_delayed, clk80_delayed, twin_swap) begin case twin_swap is when '0' => twin_clk80 <= clkn80_delayed; when '1' => twin_clk80 <= clk80_delayed; when others => twin_clk80 <= 'X'; end case; end process u_22combo_proc; -- ModuleWare code(v1.12) for instance 'U_27' of 'mux' u_27combo_proc: process(clkn40_delayed, clk40_delayed, twin_swap) begin case twin_swap is when '0' => twin_clk40 <= clkn40_delayed; when '1' => twin_clk40 <= clk40_delayed; when others => twin_clk40 <= 'X'; end case; end process u_27combo_proc; -- Instance port mappings. Uctltop : control_top port map ( c_lld => s_lld(255 downto 240), clk => clk, oc_data_i => oc_data_i, oc_valid_i => oc_valid_i, rst => rst, rst_ocb_i => rst_ocb_i, s40 => strobe40, sda_i => sda_i, stat_i => stat, tick_i => tick, tog20_i => tog20_i, trg_all_mask_i => trg_all_mask, c_lls => s_lls(255 DOWNTO 240), com_ocrawcom_o => com_ocrawcom, command_o => command, db_data_o => db_data, db_wr_o => db_wr, oc_dack_no => oc_dack_no, ocraw_start_o => ocraw_start, rawsigs_o => rawsigs, reg_o => reg_internal, rst_disp_o => rst_disp, rst_feo_o => open, rst_netrx_o => rst_netrx, rst_nettx_o => rst_nettx, rst_ro_o => rst_ro, rst_trig_o => rst_trig, sck_o => sck_o, sck_to => sck_to, sda_o => sda_o, sda_to => sda_to, spiser_clk_o => spiser_clk_o, spiser_com_o => spiser_com_o, sq_addr_o => sq_addr, sq_stat_o => sq_stat, strm_cmd_o => strm_cmd, strm_reg_o => strm_reg, strm_req_stat_o => strm_req_stat, ti2c_cvst_no => ti2c_cvst_no, ti2c_cvstt_no => ti2c_cvstt_no ); Ureadout : readout_top generic map ( MOD_PRES => RO_MOD_PRES, MOD_RAW => RO_MOD_RAW, MOD_HST => RO_MOD_HST, MOD_TYPE => RO_MOD_TYPE, MOD_IDBG => RO_MOD_IDBG, RO_TYPE => RO_TYPE ) port map ( bcid_i => bcid, clk => clk, l1id_i => l1id, link4x_i => link4x_i, ocraw_start_i => ocraw_start, reg => reg_internal, rst => rst_ro, s20_i => s20_i, s_lld_i => s_lld(135 downto 0), strm_cmd_i => strm_cmd, strm_reg_i => strm_reg, strm_req_stat_i => strm_req_stat, strobe40_i => strobe40, tick => tick, trig80_i => trig80, busy_o => busy_ro, gen13data80_o => open, gen13data_o => open, s_lls_o => s_lls(135 downto 0) ); Utimestamp : timestamp port map ( ts_o => epoc_secs ); Utriggertop : trigger_top generic map ( TLU_EN => TRIG_TLU_EN, TDC_EN => TRIG_TDC_EN ) port map ( busy_ext_i => LO, busy_ro_i => busy_ro, clk => clk, command => command, lemo_bcr_i => LO, lemo_ecr_i => LO, lemo_trig_i => lemo_trig, lld_i => s_lld(238), ocraw_start_i => ocraw_start, rawsigs_i => rawsigs, reg => reg_internal, rst => rst_trig, s40 => strobe40, tdc_data_i => tdc_data_i, tdc_new_i => tdc_new_i, tick => tick, tlu_reset_i => tlu_reset, tlu_trig_i => tlu_trig, tog => tog, twin_open_i => twin_open, bcid_l1a_o => bcid_l1a, bcid_o => bcid, bcr_all_o => open, busy_all_o => busy_all, busy_ext_o => busy_ext, dbg_trig_ext_o => dbg_trig_ext, ecr_all_o => open, l0id_l1_o => l0id_l1, l0id_o => l0id, lls_o => s_lls(238), outsigs_o => outsigs_o, pretrig_o => pretrig_out, tb_bcount_o => tb_bcount, tb_flags_o => tb_flags, tb_tcount_o => tb_tcount, tlu_busy_o => tlu_busy_internal, tlu_tclk_o => tlu_tclk_internal, trg_all_mask_o => trg_all_mask, trid_tlu_new_o => trid_tlu_new_o, trig40_o => trig40, trig80_o => trig80, trig_out_o => trig_out ); Umux256 : ll_syncmux256 port map ( clk => clk, lld_i => tx_lld_i, rst => rst, s_lls_i => s_lls, lls_o => tx_lls_o, s_lld_o => s_lld, selected_str_o => open ); Umpower : m_power port map ( hi => HI, lo => LO ); Uticksgen1 : ticks_gen generic map ( SIM_MODE => SIM_MODE, CLK_MHZ => 80 ) port map ( tick_o => tick, toggle_o => tog, clk => clk, rst => rst ); g2: IF 1=2 GENERATE -- HDL Embedded Text Block 1 eb1 SPY_STREAM_ID <= 16#00F0#; Urospyunit : ro_spy_unit port map ( STREAM_ID => SPY_STREAM_ID, capture_len_i => reg_internal(R_LEN0), clk => clk, hold_reg_rst_i => command(CMD_LATCH_RST), lld_i => s_lld(239), ocraw_start_i => ocraw_start, rawsigs_i => rawsigs, reg_spysig_ctl_i => reg_internal(R_SPYSIG_CTL), rst => rst_ro, sink_go_i => command(CMD_SINK_GO), spy_sig_i => dbg_outsigs_i, lls_o => s_lls(239), spy_hold_reg_o => spy_hold_reg ); end generate g2; g3: IF ISHSIO=1 GENERATE -- HDL Embedded Text Block 2 eb2 HSIO_VER <= stat(3) & build_no_slv; dbg_oe <= dbg_reg(R_CONTROL)(CTL_DBG_EN); -- P2 IDC ------------------------------------------------------------- -- P2 is used for add-on devices -- -- P3 IDC ------------------------------------------------------------- -- P3 could be used for fake serial data sending -- The return path is via the EOS porch. -- --gen_p3_dbg_sig : for n in 0 to 31 generate --begin -- idc_p3_io(n) <= '0'; --end generate; --idc_p3_io <= (others => '0'); -- P4 IDC ------------------------------------------------------------- --gen_p4_dbg_sig : for n in 0 to 31 generate --begin -- idc_p4_io(m) <= '0'; --end generate; --idc_p4_io <= (others => '0'); -- P5 IDC ------------------------------------------------------------- idc_p5_io(0) <= dbg_clk; --idc 1 idc_p5_io(2) <= dbg_oe and dbg_strobe40; --idc 3 idc_p5_io(4) <= dbg_oe and dbg_trig80; --idc 5 idc_p5_io(6) <= dbg_clk40; --idc 7 -- gnd ---------------- gnd --idc 9 idc_p5_io(8) <= dbg_oe and dbg_lemo_trig; --idc11 idc_p5_io(10) <= dbg_oe and dbg_com_abc; --idc13 idc_p5_io(12) <= dbg_oe and dbg_busy_ro; --idc15 idc_p5_io(14) <= dbg_oe and dbg_ocraw_start; --idc17 -- gnd ---------------- gnd --idc19 idc_p5_io(16) <= dbg_oe and dbg_tlu_trig; --idc21 idc_p5_io(18) <= dbg_oe and dbg_tlu_tclk; --idc23 idc_p5_io(20) <= dbg_oe and dbg_tlu_busy; --idc25 idc_p5_io(22) <= dbg_oe and dbg_tlu_reset; --idc27 -- gnd ---------------- gnd --idc29 idc_p5_io(24) <= dbg_clk160; --idc31 idc_p5_io(26) <= dbg_clk160ps; --idc33 idc_p5_io(28) <= dbg_clk_p2_pll; --idc35 idc_p5_io(30) <= dbg_oe and dbg_oc_start_i; --idc37 -- gnd ---------------- gnd --idc39 -- map "far side" P5 IDC signals (idc 2-40, evens, 10,20,30,40 = gnd)) gen_p5_dbg_sig : for n in 0 to 15 generate begin idc_p5_io((n*2)+1) <= dbg_oe and dbg_outsigs_i(n); end generate; --------------------------------------------------------- idbg_link_sel <= conv_integer(reg_internal(R_LEMO_STRM))/2; dbg_lemo_strm0 <= dbg_strm(idbg_link_sel*2); dbg_lemo_strm1 <= dbg_strm((idbg_link_sel*2)+1); dbg_lemo_link <= dbg_link_idly(idbg_link_sel); ------------------------------------ -- Display ------------------------------------ dispDigitA <= "0000" & dispword(31 downto 28); dispDigitB <= "0000" & dispword(27 downto 24); dispDigitC <= "0000" & dispword(23 downto 20); dispDigitD <= "0000" & dispword(19 downto 16); dispDigitE <= "0000" & dispword(15 downto 12); dispDigitF <= "0000" & dispword(11 downto 8); dispDigitG <= "0000" & dispword(7 downto 4); dispDigitH <= "0000" & dispword(3 downto 0); dispword(31 downto 0) <= HSIO_VER; -- HSIO_VER when (post_rst_5s = '1') else -- --(x"0007" & dbg_reg(R_LEN0)) when (dbg_reg(R_DISP_SEL) = x"0007") else -- --(x"0008" & dbg_reg(R_LEN1)) when (dbg_reg(R_DISP_SEL) = x"0008") else -- --(x"0016" & dbg_reg(R_COM_ENA)) when (dbg_reg(R_DISP_SEL) = x"0010") else -- (x"0021" & dbg_l1id(15 downto 0)) when (dbg_reg(R_DISP_SEL) = x"0015") else -- (x"0022" & x"0" & dbg_bcid_l1a) when (dbg_reg(R_DISP_SEL) = x"0016") else -- --(x"0023" & dbg_reg(R_CONTROL)) when (dbg_reg(R_DISP_SEL) = x"0017") else -- --sf_stat_word_i(0)(31 downto 0) when (dbg_reg(R_DISP_SEL) = x"0020") else -- --sf_stat_word_i(1)(31 downto 0) when (dbg_reg(R_DISP_SEL) = x"0022") else -- --stat_word_cu(31 downto 0) when (dbg_reg(R_DISP_SEL) = x"0024") else -- HSIO_VER; Udisp : disp_top port map ( clk => clk, reset => rst_disp, tick_2khz_i => tick(T_2kHz), toggle_2mhz_i => tog(T_2MHz), dispClk => disp_clk_o, dispDat => disp_dat_o, dispLoadL => disp_load_no, dispRstL => disp_rst_no, dispDigitA => binmapchar, dispDigitB => dispDigitB, dispDigitC => dispDigitC, dispDigitD => dispDigitD, dispDigitE => dispDigitE, dispDigitF => dispDigitF, dispDigitG => dispDigitG, dispDigitH => dispDigitH ); U_44 : led_pulse port map ( clk => clk, i => trig80, tick_i => tick(T_10Hz), rst => rst_disp, o => led_trig ); -- ModuleWare code(v1.12) for instance 'U_45' of 'or' led_status_o <= led_trig or tog(T_4Hz); Udispbinmap : disp_binmap port map ( bit0 => led_tx, bit1 => led_rx, bit2 => sf_syncacq_i(1), bit3 => sf_syncacq_i(0), dispchar_o => binmapchar ); U_47 : led_pulse port map ( clk => clk, i => rx_ok_i, tick_i => tick(T_20Hz), rst => rst_disp, o => led_rx ); U_48 : led_pulse port map ( clk => clk, i => tx_ok_i, tick_i => tick(T_20Hz), rst => rst_disp, o => led_tx ); -- ModuleWare code(v1.12) for instance 'U_8' of 'buff' dbg_com_abc <= com_abc; -- ModuleWare code(v1.12) for instance 'U_9' of 'buff' dbg_l1r_abc <= l1r_abc; -- ModuleWare code(v1.12) for instance 'U_10' of 'buff' dbg_lemo_trig <= lemo_trig; -- HDL Embedded Text Block 5 eb5 -- eb1 1 dbg_reg <= reg_internal; -- ModuleWare code(v1.12) for instance 'U_11' of 'buff' -- ModuleWare code(v1.12) for instance 'U_12' of 'buff' dbg_bcid_l1a <= bcid_l1a; -- ModuleWare code(v1.12) for instance 'U_15' of 'buff' dbg_twin_open <= twin_open; -- ModuleWare code(v1.12) for instance 'U_16' of 'buff' dbg_busy_ro <= busy_ro; -- ModuleWare code(v1.12) for instance 'U_17' of 'buff' dbg_ocraw_start <= ocraw_start; -- ModuleWare code(v1.12) for instance 'U_4' of 'buff' dbg_link_idly <= link_idly_i; -- ModuleWare code(v1.12) for instance 'U_5' of 'buff' dbg_strm <= strm_i; -- ModuleWare code(v1.12) for instance 'U_18' of 'buff' dbg_count_o <= sim_count; -- HDL Embedded Text Block 6 eb6 -- eb6 6 clocky_leds_o(7) <= led_tlu_busy; clocky_leds_o(6) <= led_tlu_tclk; clocky_leds_o(5) <= led_tlu_trig; clocky_leds_o(4) <= led_ocraw_start; clocky_leds_o(3) <= led_trig; clocky_leds_o(2) <= clk_ext_on_i; clocky_leds_o(1) <= tog_pll(T_4Hz); clocky_leds_o(0) <= tog(T_4Hz); U_46 : led_pulse port map ( clk => clk, i => dbg_ocraw_start, tick_i => tick(T_10Hz), rst => rst_disp, o => led_ocraw_start ); -- ModuleWare code(v1.12) for instance 'U_19' of 'buff' dbg_busy_ext <= busy_ext; Uticksgen : ticks_gen generic map ( SIM_MODE => SIM_MODE, CLK_MHZ => 40 ) port map ( tick_o => open, toggle_o => tog_pll, clk => clk_p2_pll_i, rst => rst ); -- HDL Embedded Text Block 7 eb7 -- Jn LEMOs ------------------------- --------------------- -- top J5 J7 J6 J8 -- front J4 J3 J1 J2 --------------------- sma_io(1) <= busy_ext; sma_io(2) <= lemo_bco_out; lemo_clk_in <= sma_io(3); lemo_trig <= sma_io(4); sma_io(5) <= dbg_trig_ext; sma_io(6) <= dbg_lemo_link; sma_io(7) <= trig_out; sma_io(8) <= pretrig_out; -- ModuleWare code(v1.12) for instance 'U_21' of 'buff' dbg_trig_out <= trig_out; Usimcounter : counter generic map ( BITS => 8, ROLLOVER_EN => 1, RST_IS_PRESET => 0 -- reset is preset ) port map ( inc_i => HI, clr_i => LO, pre_i => LO, count_o => sim_count, count_at_max_o => open, en_i => HI, rst => rst, clk => clk ); Uoddrbco : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => lemo_bco_out, C => clk, CE => HI, D1 => strobe40, D2 => strobe40_n, R => rst, S => LO ); Ubufrlemoclk : BUFR generic map ( BUFR_DIVIDE => "BYPASS", SIM_DEVICE => "VIRTEX4" ) port map ( O => lemo_clk, CE => HI, CLR => LO, I => lemo_clk_in ); Uoddrbco1 : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_clk40, C => clk, CE => dbg_oe, D1 => strobe40, D2 => strobe40_n, R => rst, S => LO ); Uoddrbco2 : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_clk, C => clk, CE => dbg_oe, D1 => HI, D2 => LO, R => rst, S => LO ); -- ModuleWare code(v1.12) for instance 'U_25' of 'buff' dbg_strobe40 <= strobe40; -- ModuleWare code(v1.12) for instance 'U_20' of 'buff' dbg_trig80 <= trig80; Uoddrbco5 : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_clk_p2_pll, C => clk_p2_pll_i, CE => dbg_oe, D1 => HI, D2 => LO, R => LO, S => LO ); Uoddrbco6 : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_lemo_clk, C => lemo_clk, CE => dbg_oe, D1 => HI, D2 => LO, R => LO, S => LO ); -- ModuleWare code(v1.12) for instance 'U_13' of 'buff' lemo_clk_o <= lemo_clk; -- ModuleWare code(v1.12) for instance 'U_14' of 'buff' dbg_tdc_calib_edge0 <= tdc_calib_edge0; -- ModuleWare code(v1.12) for instance 'U_23' of 'buff' dbg_tlu_trig <= tlu_trig; -- ModuleWare code(v1.12) for instance 'U_24' of 'buff' dbg_tlu_tclk <= tlu_tclk_internal; -- ModuleWare code(v1.12) for instance 'U_26' of 'buff' dbg_tlu_busy <= tlu_busy_internal; U_49 : led_pulse port map ( clk => clk, i => tlu_trig, tick_i => tick(T_10Hz), rst => rst_disp, o => led_tlu_trig ); U_50 : led_pulse port map ( clk => clk, i => tlu_busy_internal, tick_i => tick(T_10Hz), rst => rst_disp, o => led_tlu_busy ); U_51 : led_pulse port map ( clk => clk, i => tlu_tclk_internal, tick_i => tick(T_10Hz), rst => rst_disp, o => led_tlu_tclk ); U_53 : counter generic map ( BITS => 2, ROLLOVER_EN => 0, RST_IS_PRESET => 0 -- reset is preset ) port map ( inc_i => tick(T_0Hz5), clr_i => LO, pre_i => LO, count_o => open, count_at_max_o => post_rst_5s_n, en_i => HI, rst => rst, clk => clk ); -- ModuleWare code(v1.12) for instance 'U_3' of 'inv' post_rst_5s <= not(post_rst_5s_n); -- ModuleWare code(v1.12) for instance 'U_29' of 'buff' dbg_tlu_reset <= tlu_reset; g1: FOR ff IN 0 TO 2 GENERATE g0: FOR f IN 0 TO 3 GENERATE Uoddrfakecom : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => sim_dat(f+ff*4), C => clk, CE => dbg_oe, D1 => sim_count(f*2+1), D2 => sim_count(f*2), R => rst, S => LO ); Uob6 : OBUFDS generic map ( CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS_25" ) port map ( O => sim_dat_lvds_o(f*2+ff*8), OB => sim_dat_lvds_o(f*2+1+ff*8), I => sim_dat(f+ff*4) ); end generate g0; end generate g1; g4: IF 1=2 GENERATE Uoddrbco7 : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_clk160ps, C => clk160ps, CE => dbg_oe, D1 => HI, D2 => LO, R => LO, S => LO ); Uoddrbco8 : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) port map ( Q => dbg_clk160, C => clk160, CE => dbg_oe, D1 => HI, D2 => LO, R => LO, S => LO ); end generate g4; end generate g3; -- Implicit buffered output assignments reg <= reg_internal; tlu_busy <= tlu_busy_internal; tlu_tclk <= tlu_tclk_internal; end struct;