Generation Settings

Component declarationsyes
Configurationsin separate file
add pragmas
exclude view name

Declarations

Ports:

clk               : std_logic
rst               : std_logic
trig80_i          : std_logic
bcid_i            : std_logic_vector(11 DOWNTO 0)
l1id_i            : std_logic_vector(23 DOWNTO 0)
strm_reg_i        : slv16_array(143 DOWNTO 0)
strm_cmd_i        : slv16_array(143 DOWNTO 0)
-- streams interface
strm_req_stat_i   : std_logic_vector(143 DOWNTO 0)
strobe40_i        : std_logic
--ht_delta_max_i   : in  slv6;
busy_o            : std_logic
s_lls_o           : t_llsrc_array(135 DOWNTO 0)
s_lld_i           : std_logic_vector(135 DOWNTO 0)
-- registers
reg               : t_reg_bus
tick              : std_logic_vector(MAX_TICTOG downto 0)
gen13data_o       : slv2_array(1 downto 0)
gen13data80_o     : slv2_array(1 downto 0)
ocraw_start_i     : std_logic
s20_i             : std_logic
-- In
link4x_i          : slv4_array(67 downto 0)

Diagram Signals:

signal capture_start     : std_logic
--ht_delta_max_i   : in  slv6;
signal busy_bus          : std_logic_vector(135 DOWNTO 0)
signal mode40_strobe     : std_logic
signal capture_start80_q : std_logic
signal capture_start80   : std_logic
signal strm_i            : std_logic_vector(135 DOWNTO 0)
signal gen13data80       : slv2_array(1 downto 0)
signal gen13data         : slv2_array(1 downto 0)
signal LOLO2             : slv2_array(1 downto 0)
signal strm16            : std_logic_vector(135 DOWNTO 0)
signal strm32            : std_logic_vector(135 DOWNTO 0)
signal RAW_MULTI_EN      : std_logic
signal HI                : std_logic
signal LO                : std_logic
signal LOHI              : std_logic_vector(1 downto 0)
signal HIHI              : std_logic_vector(1 downto 0)
signal LOLO              : std_logic_vector(1 DOWNTO 0)
signal HILO              : std_logic_vector(1 downto 0)
signal SLV_MOD_RAW       : std_logic_vector(35 downto 0)
signal SLV_MOD_HST       : std_logic_vector(35 downto 0)
signal STREAM_IDS        : integer_array(135 downto 0)
signal serdata           : std_logic_vector(135 downto 0)

Pre User:


Post User:


Package List

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;

Bundles