-- VHDL Entity hsio.readout_top.symbol -- -- Created by Matt Warren 2015 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity readout_top is generic( MOD_PRES : std_logic_vector(35 downto 0) := x"000000000"; MOD_RAW : std_logic_vector(35 downto 0) := x"000000000"; MOD_HST : std_logic_vector(35 downto 0) := x"000000000"; MOD_TYPE : std_logic_vector(35 downto 0) := x"000000000"; MOD_IDBG : std_logic_vector(35 downto 0) := x"000000000"; RO_TYPE : integer := 99 ); port( bcid_i : in std_logic_vector (11 downto 0); clk : in std_logic; l1id_i : in std_logic_vector (23 downto 0); -- In link4x_i : in slv4_array (67 downto 0); ocraw_start_i : in std_logic; -- registers reg : in t_reg_bus; rst : in std_logic; s20_i : in std_logic; s_lld_i : in std_logic_vector (135 downto 0); strm_cmd_i : in slv16_array (143 downto 0); strm_reg_i : in slv16_array (143 downto 0); -- streams interface strm_req_stat_i : in std_logic_vector (143 downto 0); strobe40_i : in std_logic; tick : in std_logic_vector (MAX_TICTOG downto 0); trig80_i : in std_logic; --ht_delta_max_i : in slv6; busy_o : out std_logic; gen13data80_o : out slv2_array (1 downto 0); gen13data_o : out slv2_array (1 downto 0); s_lls_o : out t_llsrc_array (135 downto 0) ); -- Declarations end readout_top ; -- VHDL from Block Diagram -- Generated by Mentor Graphics HDL Designer(TM) 2015.1 (Build 16) -- -- hsio.readout_top.struct -- -- Created by Matt Warren 2015 -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; architecture struct of readout_top is -- Architecture declarations -- Internal signal declarations signal HI : std_logic; signal HIHI : std_logic_vector(1 downto 0); signal HILO : std_logic_vector(1 downto 0); signal LO : std_logic; signal LOHI : std_logic_vector(1 downto 0); signal LOLO : std_logic_vector(1 downto 0); signal LOLO2 : slv2_array(1 downto 0); signal RAW_MULTI_EN : std_logic; signal SLV_MOD_HST : std_logic_vector(35 downto 0); signal SLV_MOD_RAW : std_logic_vector(35 downto 0); signal STREAM_IDS : integer_array(135 downto 0); --ht_delta_max_i : in slv6; signal busy_bus : std_logic_vector(135 downto 0); signal capture_start : std_logic; signal capture_start80 : std_logic; signal capture_start80_q : std_logic; signal gen13data : slv2_array(1 downto 0); signal gen13data80 : slv2_array(1 downto 0); signal mode40_strobe : std_logic; signal serdata : std_logic_vector(135 downto 0); signal strm16 : std_logic_vector(135 downto 0); signal strm32 : std_logic_vector(135 downto 0); signal strm_i : std_logic_vector(135 downto 0); -- Component Declarations component ro_unit port ( HST_EN : in std_logic ; RAW_EN : in std_logic ; RAW_MULTI_EN : in std_logic ; STREAM_ID : in integer ; bcid_i : in std_logic_vector (11 downto 0) bus; capture_start_i : in std_logic ; clk : in std_logic ; l1id_i : in std_logic_vector (23 downto 0) bus; lld_i : in std_logic ; mode40_strobe_i : in std_logic ; -- registers reg : in t_reg_bus ; req_stat_i : in std_logic ; rst : in std_logic ; serdata_i : in std_logic ; strm_cmd_i : in std_logic_vector (15 downto 0); strm_reg_i : in std_logic_vector (15 downto 0); trig80_i : in std_logic ; --ht_delta_max_i : in slv6; busy_o : out std_logic ; --out lls_o : out t_llsrc ); end component; component ro13_datagen_top port ( bcid_i : in std_logic_vector (11 downto 0); clk : in std_logic ; l1id_i : in std_logic_vector (23 downto 0); -- registers reg : in t_reg_bus ; rst : in std_logic ; trig80_i : in std_logic ; gen13data80_o : out slv2_array (1 downto 0); gen13data_o : out slv2_array (1 downto 0) ); end component; component ro13_link generic ( STREAM_ID : integer := 0; HST_EN : std_logic := '0'; RAW_EN : std_logic := '0'; RO_TYPE : integer := 99 ); port ( bcid_i : in std_logic_vector (11 downto 0) bus; capture_start_i : in std_logic ; clk : in std_logic ; gen13data80_i : in slv2_array (1 downto 0); gen13data_i : in slv2_array (1 downto 0); l1id_i : in std_logic_vector (23 downto 0) bus; -- In link4x_i : in slv4 ; lld_i : in std_logic ; -- registers reg : in t_reg_bus ; -- stats req_stat_i : in std_logic ; rst : in std_logic ; s20_i : in std_logic ; s40 : in std_logic ; sim13data_i : in slv2_array (1 downto 0); strm_cmd_i : in std_logic_vector (15 downto 0); strm_reg_i : in std_logic_vector (15 downto 0); tick : in std_logic_vector (MAX_TICTOG downto 0); trig80_i : in std_logic ; --ht_delta_max_i : in slv6; busy_o : out std_logic ; --out lls_o : out t_llsrc ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 1 eb1 -- eb1 1 mode40_strobe <= '1' when (reg(R_CONTROL)(CTL_DCLK40_MODE) = '0') else not(strobe40_i); -- *** this is because we usually "if (strobe40_i='0') ..." capture_start80 <= trig80_i when (reg(R_CONTROL)(CTL_CAP_START_SRC) = '1') else ocraw_start_i; capture_start80_q <= capture_start80 when rising_edge(clk); capture_start <= capture_start80 or capture_start80_q; -- HDL Embedded Text Block 2 eb2 -- eb2 2 --busy_bus(127 downto 112) <= x"0000"; --busy_bus(63 downto 48) <= x"0000"; -- 1234567890123456789012345678901234 busy_o <= '0' when busy_bus = x"0000000000000000000000000000000000" else '1'; -- HDL Embedded Text Block 7 eb7 -- eb1 1 HI <= '1'; LO <= '0'; HIHI <= "11"; LOLO <= "00"; HILO <= "10"; LOHI <= "01"; LOLO2(0) <= "00"; LOLO2(1) <= "00"; -- HDL Embedded Text Block 8 eb8 -- eb8 8 gen13data_o <= gen13data; gen13data80_o <= gen13data80; -- Instance port mappings. Udatagentop : ro13_datagen_top port map ( bcid_i => bcid_i, clk => clk, l1id_i => l1id_i, reg => reg, rst => rst, trig80_i => trig80_i, gen13data80_o => gen13data80, gen13data_o => gen13data ); g_rawmulti1: IF (C_RAW_MULTI_EN = '1') GENERATE -- HDL Embedded Text Block 9 eb9 -- eb9 9 strm16( 15 downto 0) <= strm_i(31 downto 16); strm16( 63 downto 16) <= (others => '0'); strm16( 79 downto 64) <= strm_i(95 downto 80); strm16(135 downto 80) <= (others => '0'); strm32( 15 downto 0) <= strm_i(47 downto 32); strm32( 63 downto 16) <= (others => '0'); strm32( 79 downto 64) <= strm_i(111 downto 96); strm32(135 downto 80) <= (others => '0'); RAW_MULTI_EN <= '1'; end generate g_rawmulti1; g_rawmulti2: IF (C_RAW_MULTI_EN = '0') GENERATE -- HDL Embedded Text Block 10 eb10 -- eb9 9 strm16 <= (others => '0'); strm32 <= (others => '0'); RAW_MULTI_EN <= '0'; end generate g_rawmulti2; g_modules: FOR m IN 0 TO 33 GENERATE gif_tn: IF (MOD_PRES(m) = '0') GENERATE -- HDL Embedded Text Block 3 eb3 -- eb3 3 busy_bus(m*4+3 downto m*4) <= "0000"; end generate gif_tn; gr1: IF (MOD_RAW(m)='1') GENERATE -- HDL Embedded Text Block 12 eb12 -- eb12 12 SLV_MOD_RAW(m) <= '1'; end generate gr1; g_abc130: IF (MOD_PRES(m) = '1') and (MOD_TYPE(m) = '1') GENERATE g_ro13_link: for s in 0 to 1 GENERATE Uro13link : ro13_link generic map ( STREAM_ID => m*4+s*2, HST_EN => MOD_HST(m), RAW_EN => MOD_RAW(m), RO_TYPE => RO_TYPE ) port map ( bcid_i => bcid_i, capture_start_i => capture_start, clk => clk, gen13data80_i => gen13data80, gen13data_i => gen13data, l1id_i => l1id_i, link4x_i => link4x_i(m*2+s), lld_i => s_lld_i(m*4+s*2), reg => reg, req_stat_i => strm_req_stat_i(m*4+s*2), rst => rst, s20_i => s20_i, s40 => strobe40_i, sim13data_i => LOLO2, strm_cmd_i => strm_cmd_i(m*4+s*2), strm_reg_i => strm_reg_i(m*4+s*2), tick => tick, trig80_i => trig80_i, busy_o => busy_bus(m*4+s*2), lls_o => s_lls_o(m*4+s*2) ); g1: IF RO_TYPE = RTYP_HVCSV1 GENERATE -- HDL Embedded Text Block 4 eb4 -- eb3 3 busy_bus(m*4+s*2+1) <= '0'; end generate g1; g_ro13_link1: IF RO_TYPE = RTYP_130 GENERATE Uro13link1 : ro13_link generic map ( STREAM_ID => m*4+s*2+1, HST_EN => MOD_HST(m), RAW_EN => MOD_RAW(m), RO_TYPE => RO_TYPE ) port map ( bcid_i => bcid_i, capture_start_i => capture_start, clk => clk, gen13data80_i => gen13data80, gen13data_i => gen13data, l1id_i => l1id_i, link4x_i => link4x_i(m*2+s), lld_i => s_lld_i(m*4+s*2+1), reg => reg, req_stat_i => strm_req_stat_i(m*4+s*2+1), rst => rst, s20_i => s20_i, s40 => strobe40_i, sim13data_i => LOLO2, strm_cmd_i => strm_cmd_i(m*4+s*2+1), strm_reg_i => strm_reg_i(m*4+s*2+1), tick => tick, trig80_i => trig80_i, busy_o => busy_bus(m*4+s*2+1), lls_o => s_lls_o(m*4+s*2+1) ); end generate g_ro13_link1; end generate g_ro13_link; end generate g_abc130; gh1: IF (MOD_HST(m)='1') GENERATE -- HDL Embedded Text Block 14 eb14 -- eb12 12 SLV_MOD_HST(m) <= '1'; end generate gh1; gh2: IF (MOD_HST(m)='0') GENERATE -- HDL Embedded Text Block 15 eb15 -- eb12 12 SLV_MOD_HST(m) <= '0'; end generate gh2; gr2: IF (MOD_RAW(m)='0') GENERATE -- HDL Embedded Text Block 13 eb13 -- eb12 12 SLV_MOD_RAW(m) <= '0'; end generate gr2; end generate g_modules; g_modules1: FOR m IN 0 TO 33 GENERATE g_abcn1: IF (MOD_PRES(m) = '1') and (MOD_TYPE(m) = '0') GENERATE g_ro_unit251: for h in 0 to 1 GENERATE -- HDL Embedded Text Block 16 eb16 --eb11 11 STREAM_IDS(m*4+h*2) <= m*4+h*2; --RAW_MULTI_EN <= C_MULTI_RAW_EN; serdata(m*4+h*2) <= link4x_i(m*2+h)(0); Urounit250 : ro_unit port map ( HST_EN => SLV_MOD_HST(m), RAW_EN => SLV_MOD_RAW(m), RAW_MULTI_EN => RAW_MULTI_EN, STREAM_ID => STREAM_IDS(m*4+h*2), bcid_i => bcid_i, capture_start_i => capture_start, clk => clk, l1id_i => l1id_i, lld_i => s_lld_i(m*4+h*2), mode40_strobe_i => mode40_strobe, reg => reg, req_stat_i => strm_req_stat_i(m*4+h*2), rst => rst, serdata_i => serdata(m*4+h*2), strm_cmd_i => strm_cmd_i(m*4+h*2), strm_reg_i => strm_reg_i(m*4+h*2), trig80_i => trig80_i, busy_o => busy_bus(m*4+h*2), lls_o => s_lls_o(m*4+h*2) ); -- HDL Embedded Text Block 17 eb17 --eb11 11 STREAM_IDS(m*4+h*2+1) <= m*4+h*2+1; --RAW_MULTI_EN <= C_MULTI_RAW_EN; serdata(m*4+h*2+1) <= link4x_i(m*2+h)(2); Urounit251 : ro_unit port map ( HST_EN => SLV_MOD_HST(m), RAW_EN => SLV_MOD_RAW(m), RAW_MULTI_EN => RAW_MULTI_EN, STREAM_ID => STREAM_IDS(m*4+h*2+1), bcid_i => bcid_i, capture_start_i => capture_start, clk => clk, l1id_i => l1id_i, lld_i => s_lld_i(m*4+h*2+1), mode40_strobe_i => mode40_strobe, reg => reg, req_stat_i => strm_req_stat_i(m*4+h*2+1), rst => rst, serdata_i => serdata(m*4+h*2+1), strm_cmd_i => strm_cmd_i(m*4+h*2+1), strm_reg_i => strm_reg_i(m*4+h*2+1), trig80_i => trig80_i, busy_o => busy_bus(m*4+h*2+1), lls_o => s_lls_o(m*4+h*2+1) ); end generate g_ro_unit251; end generate g_abcn1; end generate g_modules1; end struct;