Generation Settings
Component declarations | yes |
Configurations | in separate file |
add pragmas |
exclude view name |
Declarations
Ports:
rst : std_logic
clk : std_logic
capture_len_i : std_logic_vector(15 downto 0)
reg_spysig_ctl_i : std_logic_vector(15 downto 0)
lld_i : std_logic
-- locallink tx interface
lls_o : t_llsrc
STREAM_ID : integer
ocraw_start_i : std_logic
hold_reg_rst_i : std_logic
spy_hold_reg_o : std_logic_vector(15 downto 0)
rawsigs_i : std_logic_vector(15 downto 0)
spy_sig_i : std_logic_vector(15 DOWNTO 0)
sink_go_i : std_logic
Diagram Signals:
signal HI : std_logic
signal LO : std_logic
signal deser_data : std_logic_vector(15 downto 0)
signal deser_sof : std_logic
signal deser_eof : std_logic
signal deser_we : std_logic
signal deser_data_len : std_logic_vector(10 downto 0)
signal fifo_full : std_logic
signal deser_data_truncd : std_logic
signal fifo_near_full : std_logic
signal serdata : std_logic
-- deser monitoring
signal dropped_pkts : slv8
signal spy_data : std_logic_vector(15 DOWNTO 0)
signal ZERO24 : std_logic_vector(23 DOWNTO 0)
signal ZERO12 : std_logic_vector(11 DOWNTO 0)
signal deser_data_len_wr : std_logic
signal len_fifo_full : std_logic
signal len_fifo_near_full : std_logic
signal tseen_lch : std_logic
signal header_seen : std_logic
signal tseen_lch_clr : std_logic
signal trailer_seen : std_logic
signal hseen_lch : std_logic
signal sr_data_o : std_logic_vector(34 downto 0)
signal ZERO3 : std_logic_vector(2 downto 0)
signal sr_data_word : std_logic_vector(15 downto 0)
signal capture_start : std_logic
Pre User:
Post User:
Package List
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY UNISIM;
USE UNISIM.VComponents.all;
library utils;
use utils.pkg_types.all;
library hsio;
use hsio.pkg_core_globals.all;
Bundles