Generation Settings
Component declarations | yes |
Configurations | in separate file |
add pragmas |
exclude view name |
Declarations
Ports:
rst : std_logic
clk : std_logic
bcid_i : std_logic_vector(11 DOWNTO 0) bus
l1id_i : std_logic_vector(23 DOWNTO 0) bus
strm_reg_i : std_logic_vector(15 downto 0)
strm_cmd_i : std_logic_vector(15 downto 0)
req_stat_i : std_logic
capture_start_i : std_logic
trig80_i : std_logic
--ht_delta_max_i : in slv6;
busy_o : std_logic
mode40_strobe_i : std_logic
lld_i : std_logic
--out
lls_o : t_llsrc
-- registers
reg : t_reg_bus
serdata_i : std_logic
STREAM_ID : integer
RAW_EN : std_logic
HST_EN : std_logic
RAW_MULTI_EN : std_logic
Diagram Signals:
signal HI : std_logic
signal LO : std_logic
signal histo_en : std_logic
signal deser_data : std_logic_vector(15 downto 0)
signal deser_sof : std_logic
signal deser_eof : std_logic
signal deser_we : std_logic
signal deser_data_len : std_logic_vector(10 downto 0)
signal fifo_full : std_logic
signal fifo_overflow : std_logic
signal fifo_underflow : std_logic
signal deser_data_truncd : std_logic
signal fifo_near_full : std_logic
signal strm_src : std_logic_vector(2 DOWNTO 0)
signal capture_mode : std_logic
signal deser_en : std_logic
-- deser monitoring
signal dropped_pkts : slv8
signal gendata_sel : std_logic
signal strm_mode : std_logic_vector(1 DOWNTO 0)
signal strm_reset : std_logic
signal strm_en : std_logic
signal strm_histo_ro : std_logic
signal deser_data_len_wr : std_logic
signal len_fifo_full : std_logic
signal len_fifo_near_full : std_logic
signal header_seen : std_logic
signal busy_en_fifo : std_logic
signal busy_en_delta : std_logic
signal data_count : std_logic_vector(1 downto 0)
signal len_fifo_data_count : std_logic_vector(1 downto 0)
-- locallink tx interface
signal r_lls : t_llsrc_array(3 DOWNTO 0)
signal r_lld : std_logic_vector(3 DOWNTO 0)
signal tseen_lch : std_logic
signal tseen_lch_clr : std_logic
signal trailer_seen : std_logic
signal sr_data_o : std_logic_vector(34 downto 0)
signal hseen_lch : std_logic
signal reg_len0 : std_logic_vector(15 downto 0)
signal histo_debug_mode : std_logic
signal reg_busy_delta : std_logic_vector(15 downto 0)
signal para_histo_en : std_logic
--out
signal f_lls : t_llsrc
--out
signal p_lls : t_llsrc
signal f_data_count : std_logic_vector(1 downto 0)
signal f_len_fifo_data_count : std_logic_vector(1 downto 0)
-- deser monitoring
signal f_dropped_pkts : slv8
Pre User:
Post User:
Package List
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY UNISIM;
USE UNISIM.VComponents.all;
library utils;
use utils.pkg_types.all;
library hsio;
use hsio.pkg_core_globals.all;
Bundles