-- VHDL Entity hsio.ro_unit.symbol -- -- Created by Matt Warren 2015 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity ro_unit is port( HST_EN : in std_logic; RAW_EN : in std_logic; RAW_MULTI_EN : in std_logic; STREAM_ID : in integer; bcid_i : in std_logic_vector (11 downto 0) bus; capture_start_i : in std_logic; clk : in std_logic; l1id_i : in std_logic_vector (23 downto 0) bus; lld_i : in std_logic; mode40_strobe_i : in std_logic; -- registers reg : in t_reg_bus; req_stat_i : in std_logic; rst : in std_logic; serdata_i : in std_logic; strm_cmd_i : in std_logic_vector (15 downto 0); strm_reg_i : in std_logic_vector (15 downto 0); trig80_i : in std_logic; --ht_delta_max_i : in slv6; busy_o : out std_logic; --out lls_o : out t_llsrc ); -- Declarations end ro_unit ; -- VHDL from Block Diagram -- Generated by Mentor Graphics HDL Designer(TM) 2015.1 (Build 16) -- -- hsio.ro_unit.struct -- -- Created by Matt Warren 2015 -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; LIBRARY UNISIM; USE UNISIM.VComponents.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; architecture struct of ro_unit is -- Architecture declarations -- Internal signal declarations signal HI : std_logic; signal LO : std_logic; signal busy_en_delta : std_logic; signal busy_en_fifo : std_logic; signal capture_mode : std_logic; signal data_count : std_logic_vector(1 downto 0); signal deser_data : std_logic_vector(15 downto 0); signal deser_data_len : std_logic_vector(10 downto 0); signal deser_data_len_wr : std_logic; signal deser_data_truncd : std_logic; signal deser_en : std_logic; signal deser_eof : std_logic; signal deser_sof : std_logic; signal deser_we : std_logic; -- deser monitoring signal dropped_pkts : slv8; signal f_data_count : std_logic_vector(1 downto 0); -- deser monitoring signal f_dropped_pkts : slv8; signal f_len_fifo_data_count : std_logic_vector(1 downto 0); --out signal f_lls : t_llsrc; signal fifo_full : std_logic; signal fifo_near_full : std_logic; signal fifo_overflow : std_logic; signal fifo_underflow : std_logic; signal gendata_sel : std_logic; signal header_seen : std_logic; signal histo_debug_mode : std_logic; signal histo_en : std_logic; signal hseen_lch : std_logic; signal len_fifo_data_count : std_logic_vector(1 downto 0); signal len_fifo_full : std_logic; signal len_fifo_near_full : std_logic; --out signal p_lls : t_llsrc; signal para_histo_en : std_logic; signal r_lld : std_logic_vector(3 downto 0); -- locallink tx interface signal r_lls : t_llsrc_array(3 downto 0); signal reg_busy_delta : std_logic_vector(15 downto 0); signal reg_len0 : std_logic_vector(15 downto 0); signal sr_data_o : std_logic_vector(34 downto 0); signal strm_en : std_logic; signal strm_histo_ro : std_logic; signal strm_mode : std_logic_vector(1 downto 0); signal strm_reset : std_logic; signal strm_src : std_logic_vector(2 downto 0); signal trailer_seen : std_logic; signal tseen_lch : std_logic; signal tseen_lch_clr : std_logic; -- Component Declarations component ro_deser port ( STREAM_ID : in integer ; --RAW_MULTI_EN : in std_logic; sr_data_word_i : in std_logic_vector (15 downto 0); header_seen_i : in std_logic ; trailer_seen_i : in std_logic ; tseen_lch_i : in std_logic ; tseen_lch_clr_o : out std_logic ; --gendata_sel_i : in std_logic; capture_mode_i : in std_logic ; wide_cap_mode_i : in std_logic ; capture_len_i : in std_logic_vector (8 downto 0); --strm_src_i : in std_logic_vector (2 downto 0); capture_start_i : in std_logic ; --ocrawcom_start_i : in std_logic; mode40_strobe_i : in std_logic ; -- output fifo interface fifo_we_o : out std_logic ; fifo_eof_o : out std_logic ; fifo_sof_o : out std_logic ; fifo_data_o : out slv16 ; data_len_o : out std_logic_vector (10 downto 0); data_len_wr_o : out std_logic ; data_truncd_o : out std_logic ; -- fifo monitoring fifo_near_full_i : in std_logic ; fifo_full_i : in std_logic ; len_fifo_near_full_i : in std_logic ; len_fifo_full_i : in std_logic ; -- header details l1id_i : in std_logic_vector (23 downto 0); bcid_i : in std_logic_vector (11 downto 0); -- deser monitoring dropped_pkts_o : out slv8 ; -- infra en : in std_logic ; clk : in std_logic ; rst : in std_logic ); end component; component ro_shiftreg generic ( SR_MAX : integer := 34 ); port ( serdata_i : in std_logic ; sr_data_o : out std_logic_vector (SR_MAX downto 0); header_seen_o : out std_logic ; hseen_lch_o : out std_logic ; hseen_lch_clr_i : in std_logic ; trailer_seen_o : out std_logic ; tseen_lch_o : out std_logic ; tseen_lch_clr_i : in std_logic ; mode40_strobe_i : in std_logic ; clk : in std_logic ; rst : in std_logic ); end component; component ro_unit_fifo port ( -- input interface wren_i : in std_logic ; data_i : in std_logic_vector (15 downto 0); sof_i : in std_logic ; eof_i : in std_logic ; data_truncd_i : in std_logic ; data_len_i : in std_logic_vector (10 downto 0); data_len_wr_i : in std_logic ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- fifo status full_o : out std_logic ; near_full_o : out std_logic ; overflow_o : out std_logic ; underflow_o : out std_logic ; data_count_o : out std_logic_vector (1 downto 0); len_fifo_full_o : out std_logic ; len_fifo_near_full_o : out std_logic ; len_fifo_data_count_o : out std_logic_vector (1 downto 0); -- infrastructure en : in std_logic ; clk : in std_logic ; rst : in std_logic ); end component; component ro_unit_stat port ( STREAM_ID : in integer ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- stats req_stat_i : in std_logic ; strm_reg_i : in slv16 ; reg_busy_delta_i : in slv16 ; header_seen_i : in std_logic ; trig80_i : in std_logic ; dropped_pkts_i : in slv8 ; fifo_count_i : in slv2 ; len_fifo_count_i : in slv2 ; busy_en_delta_i : in std_logic ; busy_en_fifo_i : in std_logic ; --hd_delta_max_i : in slv6; deser_en_i : in std_logic ; histo_en_i : in std_logic ; busy_o : out std_logic ; -- infrastructure clk : in std_logic ; rst : in std_logic ); end component; component ll_automux generic ( LEVELS : integer := 2 ); port ( -- locallink interfaces --in lls_i : in t_llsrc_array ((2**LEVELS)-1 downto 0); lld_o : out std_logic_vector ((2**LEVELS)-1 downto 0); --out lls_o : out t_llsrc ; lld_i : in std_logic ; -- infrastructure rst : in std_logic ; clk : in std_logic ); end component; component lls_en_zero port ( en_i : in std_logic; lls_i : in t_llsrc; lls_o : out t_llsrc ); end component; component lls_zero port ( lls_o : out t_llsrc ); end component; component parser_tom_top generic ( -- STREAM_ID : integer := 0; histogram_width : integer := 16 ); port ( STREAM_ID : in integer ; rst : in std_logic ; -- HSIO switch2, code_reload# en : in std_logic ; abcdata_i : in std_logic ; start_hstro_i : in std_logic ; debug_mode_i : in std_logic ; lls_o : out t_llsrc ; lld_i : in std_logic ; clk : in std_logic ); end component; component m_power port ( hi : out std_logic ; lo : out std_logic ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 2 eb2 -- eb2 2 para_histo_en <= strm_reg_i(8); busy_en_fifo <= strm_reg_i(7); busy_en_delta <= strm_reg_i(6); strm_mode <= strm_reg_i(5 downto 4); --strm_src <= strm_reg_i(3 downto 1); strm_en <= strm_reg_i(0); deser_en <= '1' when ((strm_en = '1') and (RAW_EN = '1') and (strm_mode /= "11")) else '0'; histo_en <= '1' when ((strm_en = '1') and (HST_EN = '1') and (strm_mode = "11")) or (para_histo_en = '1') else '0'; capture_mode <= '1' when (strm_mode = "01") else '0'; --gendata_sel <= '1' when (strm_src(2) = '1') else '0'; -- Commands -------------------------------------- strm_reset <= strm_cmd_i(15) or rst; strm_histo_ro <= strm_cmd_i(0); -- HDL Embedded Text Block 3 eb3 -- eb1 1 data_count <= "00" when (RAW_EN='0') else f_data_count; f_len_fifo_data_count <= "00" when (RAW_EN='0') else f_len_fifo_data_count; dropped_pkts <= x"00" when (RAW_EN='0') else f_dropped_pkts; -- HDL Embedded Text Block 4 eb4 -- eb3 3 reg_len0 <= reg(R_LEN0); reg_busy_delta <= reg(R_BUSY_DELTA); histo_debug_mode <= reg(R_CONTROL)(CTL_HTEST_EN); -- Instance port mappings. Udeser : ro_deser port map ( STREAM_ID => STREAM_ID, sr_data_word_i => sr_data_o(34 downto 19), header_seen_i => header_seen, trailer_seen_i => trailer_seen, tseen_lch_i => tseen_lch, tseen_lch_clr_o => tseen_lch_clr, capture_mode_i => capture_mode, wide_cap_mode_i => LO, capture_len_i => reg_len0(8 downto 0), capture_start_i => capture_start_i, mode40_strobe_i => mode40_strobe_i, fifo_we_o => deser_we, fifo_eof_o => deser_eof, fifo_sof_o => deser_sof, fifo_data_o => deser_data, data_len_o => deser_data_len, data_len_wr_o => deser_data_len_wr, data_truncd_o => deser_data_truncd, fifo_near_full_i => fifo_near_full, fifo_full_i => fifo_full, len_fifo_near_full_i => len_fifo_near_full, len_fifo_full_i => len_fifo_full, l1id_i => l1id_i, bcid_i => bcid_i, dropped_pkts_o => f_dropped_pkts, en => deser_en, clk => clk, rst => strm_reset ); Usr : ro_shiftreg generic map ( SR_MAX => 34 ) port map ( serdata_i => serdata_i, sr_data_o => sr_data_o, header_seen_o => header_seen, hseen_lch_o => hseen_lch, hseen_lch_clr_i => LO, trailer_seen_o => trailer_seen, tseen_lch_o => tseen_lch, tseen_lch_clr_i => tseen_lch_clr, mode40_strobe_i => mode40_strobe_i, clk => clk, rst => rst ); Ufifo : ro_unit_fifo port map ( wren_i => deser_we, data_i => deser_data, sof_i => deser_sof, eof_i => deser_eof, data_truncd_i => deser_data_truncd, data_len_i => deser_data_len, data_len_wr_i => deser_data_len_wr, lls_o => f_lls, lld_i => r_lld(0), full_o => fifo_full, near_full_o => fifo_near_full, overflow_o => fifo_overflow, underflow_o => fifo_underflow, data_count_o => f_data_count, len_fifo_full_o => len_fifo_full, len_fifo_near_full_o => len_fifo_near_full, len_fifo_data_count_o => f_len_fifo_data_count, en => deser_en, clk => clk, rst => strm_reset ); Urustat : ro_unit_stat port map ( STREAM_ID => STREAM_ID, lls_o => r_lls(1), lld_i => r_lld(1), req_stat_i => req_stat_i, strm_reg_i => strm_reg_i, reg_busy_delta_i => reg_busy_delta, header_seen_i => header_seen, trig80_i => trig80_i, dropped_pkts_i => dropped_pkts, fifo_count_i => data_count, len_fifo_count_i => len_fifo_data_count, busy_en_delta_i => busy_en_delta, busy_en_fifo_i => busy_en_fifo, deser_en_i => deser_en, histo_en_i => histo_en, busy_o => busy_o, clk => clk, rst => strm_reset ); Ullautomux : ll_automux generic map ( LEVELS => 2 ) port map ( lls_i => r_lls, lld_o => r_lld, lls_o => lls_o, lld_i => lld_i, rst => strm_reset, clk => clk ); Ullsez0 : lls_en_zero port map ( lls_i => f_lls, lls_o => r_lls(0), en_i => RAW_EN ); Ullsez2 : lls_en_zero port map ( lls_i => p_lls, lls_o => r_lls(2), en_i => HST_EN ); Ullsz3 : lls_zero port map ( lls_o => r_lls(3) ); Umpower : m_power port map ( hi => HI, lo => LO ); g0: IF 1=2 GENERATE Uparsertop : parser_tom_top generic map ( -- STREAM_ID : integer := 0; histogram_width => 16 ) port map ( STREAM_ID => STREAM_ID, rst => strm_reset, en => histo_en, abcdata_i => serdata_i, start_hstro_i => strm_histo_ro, debug_mode_i => histo_debug_mode, lls_o => p_lls, lld_i => r_lld(2), clk => clk ); end generate g0; end struct;