-- VHDL Entity hsio.trigger_top.symbol -- -- Created: -- by - warren.warren (mbb) -- at - 07:39:41 05/31/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; entity trigger_top is generic( TLU_EN : integer := 1; TDC_EN : integer := 1 ); port( busy_ext_i : in std_logic; busy_ro_i : in std_logic; clk : in std_logic; command : in std_logic_vector (15 downto 0); lemo_bcr_i : in std_logic; lemo_ecr_i : in std_logic; lemo_trig_i : in std_logic; lld_i : in std_logic; ocraw_start_i : in std_logic; rawsigs_i : in std_logic_vector (15 downto 0); -- registers reg : in t_reg_bus; rst : in std_logic; s40 : in std_logic; tdc_data_i : in std_logic_vector (39 downto 0); tdc_new_i : in std_logic; tick : in std_logic_vector (34 downto 0); tlu_reset_i : in std_logic; tlu_trig_i : in std_logic; tog : in std_logic_vector (34 downto 0); twin_open_i : in std_logic; bcid_l1a_o : out std_logic_vector (11 downto 0); bcid_o : out std_logic_vector (11 downto 0); bcr_all_o : out std_logic; busy_all_o : out std_logic; busy_ext_o : out std_logic; dbg_trig_ext_o : out std_logic; ecr_all_o : out std_logic; l0id_l1_o : out std_logic_vector (7 downto 0); l0id_o : out std_logic_vector (31 downto 0); -- locallink tx interface lls_o : out t_llsrc; outsigs_o : out std_logic_vector (15 downto 0); pretrig_o : out std_logic; tb_bcount_o : out std_logic_vector (15 downto 0); tb_flags_o : out std_logic_vector (7 downto 0); tb_tcount_o : out std_logic_vector (15 downto 0); tlu_busy_o : out std_logic; tlu_tclk_o : out std_logic; trg_all_mask_o : out std_logic_vector (15 downto 0); trig40_o : out std_logic; trig80_o : out std_logic; trig_out_o : out std_logic ); -- Declarations end trigger_top ; -- -- VHDL Architecture hsio.trigger_top.struct -- -- Created: -- by - warren.warren (mbb) -- at - 07:39:41 05/31/15 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils; use utils.pkg_types.all; library hsio; use hsio.pkg_core_globals.all; architecture struct of trigger_top is -- Architecture declarations -- Internal signal declarations signal HI : std_logic; signal LO : std_logic; signal ZERO13 : std_logic_vector(12 downto 0); signal ZERO16 : std_logic_vector(15 downto 0); signal ZERO2 : std_logic_vector(1 downto 0); signal ZERO3 : std_logic_vector(2 downto 0); signal ZERO4 : std_logic_vector(3 downto 0); signal ZERO8 : std_logic_vector(7 downto 0); signal bcid : std_logic_vector(11 downto 0); signal bcr_all : std_logic; signal bcr_cmd : std_logic; signal bcr_dec : std_logic; signal bcr_ecb : std_logic; signal bcr_ext : std_logic; signal bcr_genc : std_logic; signal busy : std_logic; signal busy_ext_q : std_logic := '0'; signal busy_reg : std_logic; signal busy_tlu : std_logic; signal busy_trig : std_logic; signal com_all : std_logic; signal com_genc : std_logic; signal din1 : std_logic; signal ecr_all : std_logic; signal ecr_cmd : std_logic; signal ecr_dec : std_logic; signal ecr_ecb : std_logic; signal ecr_ext : std_logic; signal ecr_genc : std_logic; signal ecr_ins : std_logic; signal l0id : std_logic_vector(31 downto 0); signal l1_auto : std_logic; signal lemo_atrig : std_logic; signal lemo_trig0 : std_logic; signal ocraw_start40 : std_logic; signal pretrig : std_logic; signal reg_control : std_logic_vector(15 downto 0); signal reg_control1 : std_logic_vector(15 downto 0); signal reg_int_ena : std_logic_vector(15 downto 0); signal reg_out_ena : std_logic_vector(15 downto 0); signal reg_outsigs : std_logic_vector(15 downto 0); signal s40_n : std_logic; signal tb_testflag : std_logic; signal td_packet : std_logic_vector(63 downto 0); signal td_pkt_rdack : std_logic; signal td_pkt_valid : std_logic; signal tlu_debug_trig_i : std_logic; signal tlu_ecr : std_logic; signal tlu_trig_sync : std_logic; signal trid_new : std_logic; signal trid_tlu : std_logic_vector(15 downto 0); signal trid_valid : std_logic; signal trig40 : std_logic; signal trig80 : std_logic; signal trig_all : std_logic; signal trig_burster : std_logic; signal trig_bus : std_logic_vector(15 downto 0); signal trig_cmd : std_logic; signal trig_cmd0 : std_logic; signal trig_ext : std_logic; signal trig_ext0 : std_logic; signal trig_src : std_logic_vector(3 downto 0); signal trig_tlu : std_logic; signal trigdat_en : std_logic; signal ts_count : std_logic_vector(39 downto 0); -- ModuleWare signal declarations(v1.12) for instance 'Ubcid_l1a' of 'adff' signal mw_Ubcid_l1areg_cval : std_logic_vector(11 downto 0); -- Component Declarations component com_decoder port ( clk : in std_logic; com_i : in std_logic; rst : in std_logic; strobe40_i : in std_logic; a13_bcr_o : out std_logic; a13_ecr_o : out std_logic; a13_fcfr_o : out std_logic; a13_softr_o : out std_logic; a13_sysr_o : out std_logic ); end component; component l1_autogen port ( clk : in std_logic; ecr_i : in std_logic; en_i : in std_logic; l0_i : in std_logic; l0id_i : in std_logic_vector (31 downto 0); rst : in std_logic; strobe40_i : in std_logic; l0id_send_o : out std_logic_vector (7 downto 0); l1_o : out std_logic ); end component; component outsigs_enc_map port ( clk : in std_logic; com_genc_i : in std_logic; invert_mux_i : in std_logic; l0_trig_all_i : in std_logic; l1_auto_i : in std_logic; rawsigs_i : in std_logic_vector (15 downto 0); reg_outsigs_i : in std_logic_vector (15 downto 0); rst : in std_logic; strobe40 : in std_logic; outsigs_o : out std_logic_vector (15 downto 0); trg_all_mask_o : out std_logic_vector (15 downto 0) ); end component; component trig_burst generic ( rptLen : integer := 16; -- bit length of trigger reitition counter rpt2Len : integer := 16; -- bit length of supercycle repitition counter waitLen : integer := 20; -- bit length of repeat cycle countdown timer wait2Len : integer := 20; -- bit length of supercycle countdown timer (VHDL integers have max. value 2**31-1) sqLenExp : integer := 3 -- exponent for bit length (2**sqLenExp) of trigger bit-sequence register ); port ( --clock : in std_logic; -- global 40 MHz clock clock : in std_logic ; -- global 80 MHz clock strobe40_i : in std_logic ; -- 40MHz clock strobe - for 80MHz sync reset : in std_logic ; -- global reset trigs_count_o : out std_logic_vector (15 downto 0); bursts_count_o : out std_logic_vector (15 downto 0); ready_o : out std_logic ; running_o : out std_logic ; finished_o : out std_logic ; -- trigger_in : in std_logic; -- readout trigger giddyup_in : in std_logic ; -- "go," since trigger might just mean "read config ports" seq_reset_i : in std_logic ; -- config_in : in std_logic; -- if received concurrently with trigger, module reads and registers config inputs. rpt_in : in std_logic_vector (rptLen-1 downto 0); -- number of triggers within a burst -- *** all of our registers are 16b, so we need to make these values waitMin16_in : in std_logic_vector (15 downto 0); -- minimum number of clock ticks between triggers w/in a burst waitMax16_in : in std_logic_vector (15 downto 0); -- maximum number of clock ticks between triggers w/in a burst rpt2_in : in std_logic_vector (rpt2Len-1 downto 0); -- number of trigger bursts wait2_16_in : in std_logic_vector (15 downto 0); -- fixed number of clock ticks between bursts --sq_in : in std_logic_vector(2**sqLenExp-1 downto 0); --sqLen_in : in std_logic_vector(sqLenExp-1 downto 0); busy_i : in std_logic ; -- input for back-pressure or flow control outBit_out : out std_logic ; -- trigger signal output testFlag_out : out std_logic -- long-lived flag for oscilloscope inspection ); end component; component trig_busygen port ( clk : in std_logic; reg_busylen_i : in std_logic_vector (15 downto 0); rst : in std_logic; s40 : in std_logic; tick_i : in std_logic_vector (34 downto 0); trig_i : in std_logic; trig_sbusy_i : in std_logic; busy_o : out std_logic ); end component; component trig_dataenc port ( clk : in std_logic; en : in std_logic; l0id16_i : in std_logic_vector (15 downto 0); pkt_rdack_i : in std_logic; rst : in std_logic; tdc_data_i : in std_logic_vector (39 downto 0); tdc_new_i : in std_logic; trid_i : in std_logic_vector (15 downto 0); trid_new_i : in std_logic; trig_bus_i : in std_logic_vector (15 downto 0); trig_i : in std_logic; packet_o : out std_logic_vector (63 downto 0); pkt_valid_o : out std_logic; trig_src_o : out std_logic_vector (3 downto 0) ); end component; component trig_tlu_if port ( clk : in std_logic; debug_trig_i : in std_logic; l0id16_i : in std_logic_vector (15 downto 0); reg_tlu_ctl_i : in std_logic_vector (15 downto 0); rst : in std_logic; s40 : in std_logic; tlu_trig_sync_i : in std_logic; tog_i : in std_logic_vector (34 downto 0); busy_tlu_o : out std_logic; tlu_tclk_o : out std_logic; trid_new_o : out std_logic; trid_tlu_o : out std_logic_vector (15 downto 0); trid_valid_o : out std_logic; trig_tlu_o : out std_logic ); end component; component ro13_mod_fifo generic ( STREAM_ID : integer := 0; TS_HIRES : integer := 0 ); port ( l0id16_i : in std_logic_vector (15 downto 0); ts_count_i : in std_logic_vector (39 downto 0); ts_source_i : in std_logic_vector (3 downto 0); ts_always_i : in std_logic ; ts_disable_i : in std_logic ; timeout_tick_i : in std_logic ; strm_src_i : in std_logic_vector (2 downto 0); capture_mode_i : in std_logic ; -- input interface packet_i : in slv64 ; --t_packet; pkt_valid_i : in sl ; pkt_rdack_o : out sl ; -- locallink tx interface lls_o : out t_llsrc ; lld_i : in std_logic ; -- fifo status full_o : out std_logic ; --near_full_o : out std_logic; overflow_o : out std_logic ; underflow_o : out std_logic ; data_count_o : out std_logic_vector (1 downto 0); -- infrastructure en : in std_logic ; s40 : in std_logic ; clk : in std_logic ; rst : in std_logic ); end component; component counter generic ( BITS : integer := 16; ROLLOVER_EN : integer := 1; RST_IS_PRESET : integer := 0 -- reset is preset ); port ( inc_i : in std_logic ; clr_i : in std_logic ; pre_i : in std_logic ; count_o : out std_logic_vector ((BITS-1) downto 0); count_at_max_o : out std_logic ; en_i : in std_logic ; rst : in std_logic ; clk : in std_logic ); end component; component edgedet_sync generic ( EN_ID : integer := 0 ); port ( s40 : in std_logic ; async_i : in std_logic ; async_o : out std_logic ; edgesync_o : out std_logic ; sync_o : out std_logic ; ena_i : in std_logic_vector (15 downto 0); inv_i : in std_logic_vector (15 downto 0); rst : in std_logic ; clk : in std_logic ); end component; component ff_d2 port ( clk : in std_logic; d : in std_logic; q1 : out std_logic := '0'; q2 : out std_logic := '0' ); end component; component prog_delay generic ( LEN : integer := 256 ); port ( clk : in std_logic; delay_i : in std_logic_vector (15 downto 0); rst : in std_logic; sig_i : in std_logic; strobe40_i : in std_logic; dsig_o : out std_logic ); end component; component sercom_gen generic ( LEN : integer := 7; DATA : integer := 0 ); port ( clk : in std_logic; ena_i : in std_logic; go_i : in std_logic; rst : in std_logic; strobe40_i : in std_logic; com_o : out std_logic ); end component; component stretch1 port ( clk : in std_logic; i : in std_logic; o : out std_logic ); end component; component stretch_sr port ( clk : in std_logic; en : in std_logic; i : in std_logic; o16 : out std_logic; o8 : out std_logic ); end component; begin -- Architecture concurrent statements -- HDL Embedded Text Block 1 eb1 -- eb1 1 reg_int_ena <= reg(R_INT_ENA); reg_out_ena <= reg(R_OUT_ENA); reg_control <= reg(R_CONTROL); reg_outsigs <= reg(R_OUTSIGS); reg_control1 <= reg(R_CONTROL1); -- HDL Embedded Text Block 2 eb2 -- eb2 2 trig_bus <= x"000" & trig_cmd & trig_burster & trig_tlu & trig_ext; -- HDL Embedded Text Block 3 eb3 -- eb3 3 trigdat_en <= '0' when ((TLU_EN = 0) and (TDC_EN = 0)) else '1'; -- HDL Embedded Text Block 4 eb4 -- eb4 4 HI <= '1'; LO <= '0'; ZERO2 <= "00"; ZERO3 <= "000"; ZERO4 <= "0000"; ZERO8 <= "00000000"; ZERO13 <= "0000000000000"; ZERO16 <= "0000000000000000"; -- HDL Embedded Text Block 6 eb6 trig80 <= (trig40 and not(s40)) when rising_edge(clk); -- ModuleWare code(v1.12) for instance 'Ubcid_l1a' of 'adff' bcid_l1a_o <= mw_Ubcid_l1areg_cval; ubcid_l1aseq_proc: process (clk)begin if (clk'event and clk='1') then if (rst = '1') then mw_Ubcid_l1areg_cval <= "000000000000"; elsif (trig80 = '1') then mw_Ubcid_l1areg_cval <= bcid; end if; end if; end process ubcid_l1aseq_proc; -- ModuleWare code(v1.12) for instance 'U_9' of 'and' trig_ext <= not(busy) and trig_ext0; -- ModuleWare code(v1.12) for instance 'U_10' of 'and' lemo_trig0 <= lemo_trig_i and din1; -- ModuleWare code(v1.12) for instance 'U_11' of 'and' trig_cmd <= not(busy) and trig_cmd0; -- ModuleWare code(v1.12) for instance 'U_29' of 'and' busy_ext_o <= busy and reg_out_ena(ENA_BUSY); -- ModuleWare code(v1.12) for instance 'U_0' of 'buff' s40_n <= s40; -- ModuleWare code(v1.12) for instance 'U_1' of 'buff' ecr_all_o <= ecr_all; -- ModuleWare code(v1.12) for instance 'U_2' of 'buff' busy_reg <= reg_control(CTL_SBUSY); -- ModuleWare code(v1.12) for instance 'U_5' of 'buff' trig80_o <= trig80; -- ModuleWare code(v1.12) for instance 'U_6' of 'buff' bcid_o <= bcid; -- ModuleWare code(v1.12) for instance 'U_13' of 'buff' dbg_trig_ext_o <= trig_ext; -- ModuleWare code(v1.12) for instance 'U_15' of 'buff' trig40_o <= trig40; -- ModuleWare code(v1.12) for instance 'U_16' of 'buff' l0id_o <= l0id; -- ModuleWare code(v1.12) for instance 'U_23' of 'buff' bcr_all_o <= bcr_all; -- ModuleWare code(v1.12) for instance 'U_3' of 'or' ecr_ecb <= ecr_cmd or ecr_ext; -- ModuleWare code(v1.12) for instance 'U_4' of 'or' ecr_ins <= lemo_ecr_i or tlu_ecr; -- ModuleWare code(v1.12) for instance 'U_7' of 'or' trig_all <= rawsigs_i(RS_STT_L0) or rawsigs_i(RS_STB_L0) or rawsigs_i(RS_IDC_L0) or trig_burster or trig_tlu or trig_cmd or trig_ext; -- ModuleWare code(v1.12) for instance 'U_12' of 'or' din1 <= not(reg_control(CTL_TWIN_EN)) or twin_open_i; -- ModuleWare code(v1.12) for instance 'U_14' of 'or' com_all <= rawsigs_i(RS_STT_COM) or rawsigs_i(RS_STB_COM) or rawsigs_i(RS_ID0_COM) or rawsigs_i(RS_ID1_COM); -- ModuleWare code(v1.12) for instance 'U_17' of 'or' pretrig <= trig_all or ocraw_start40; -- ModuleWare code(v1.12) for instance 'U_19' of 'or' ecr_all <= ecr_dec or ecr_ecb; -- ModuleWare code(v1.12) for instance 'U_20' of 'or' bcr_ecb <= bcr_cmd or bcr_ext; -- ModuleWare code(v1.12) for instance 'U_21' of 'or' bcr_all <= bcr_dec or bcr_ecb; -- ModuleWare code(v1.12) for instance 'U_22' of 'or' com_genc <= ecr_genc or bcr_genc; -- ModuleWare code(v1.12) for instance 'U_27' of 'or' busy <= busy_reg or busy_ext_q or busy_ro_i or busy_tlu or busy_trig; -- Instance port mappings. Ucmddecoder : com_decoder port map ( com_i => com_all, a13_fcfr_o => open, a13_sysr_o => open, a13_bcr_o => bcr_dec, a13_ecr_o => ecr_dec, a13_softr_o => open, strobe40_i => s40, rst => rst, clk => clk ); Ul1autogen : l1_autogen port map ( strobe40_i => s40, l0id_i => l0id, l0id_send_o => l0id_l1_o, en_i => reg(R_CONTROL1)(CTL_L0_AUTOGEN), ecr_i => ecr_all, l0_i => trig40, l1_o => l1_auto, rst => rst, clk => clk ); Uosencmap : outsigs_enc_map port map ( invert_mux_i => reg(R_CONTROL)(CTL_A13MUX_INV), reg_outsigs_i => reg(R_OUTSIGS), rawsigs_i => rawsigs_i, l1_auto_i => l1_auto, l0_trig_all_i => trig40, com_genc_i => com_genc, trg_all_mask_o => trg_all_mask_o, outsigs_o => outsigs_o, strobe40 => s40, rst => rst, clk => clk ); Utrgburst : trig_burst generic map ( rptLen => 16, -- bit length of trigger rpeitition counter rpt2Len => 16, -- bit length of supercycle repitition counter waitLen => 20, -- bit length of repeat cycle countdown timer wait2Len => 20, -- bit length of supercycle countdown timer (VHDL integers have max. value 2**31-1) sqLenExp => 3 -- exponent for bit length (2**sqLenExp) of trigger bit-sequence register ) port map ( clock => clk, strobe40_i => s40, reset => rst, trigs_count_o => tb_tcount_o, bursts_count_o => tb_bcount_o, ready_o => tb_flags_o(TB_READY), running_o => tb_flags_o(TB_RUNNING), finished_o => tb_flags_o(TB_FINISHED), giddyup_in => command(CMD_TB_START), seq_reset_i => command(CMD_TB_RST), rpt_in => reg(R_TB_TRIGS), waitMin16_in => reg(R_TB_PMIN), waitMax16_in => reg(R_TB_PMAX), rpt2_in => reg(R_TB_BURSTS), wait2_16_in => reg(R_TB_PDEAD), busy_i => busy, outBit_out => trig_burster, testFlag_out => tb_testflag ); Utrigbusygen : trig_busygen port map ( trig_i => trig_all, trig_sbusy_i => reg(R_CONTROL1)(CTL_SBUSY_ON_T), reg_busylen_i => reg(R_BUSYLEN), busy_o => busy_trig, tick_i => tick, s40 => s40, clk => clk, rst => rst ); Utrgdatenc : trig_dataenc port map ( trig_i => trig40, l0id16_i => l0id(15 downto 0), trig_bus_i => trig_bus, trig_src_o => trig_src, trid_i => trid_tlu, trid_new_i => trid_new, tdc_new_i => tdc_new_i, tdc_data_i => tdc_data_i, packet_o => td_packet, pkt_valid_o => td_pkt_valid, pkt_rdack_i => td_pkt_rdack, en => trigdat_en, clk => clk, rst => rst ); Utdatfifo : ro13_mod_fifo generic map ( STREAM_ID => 144, TS_HIRES => 1 ) port map ( l0id16_i => l0id(15 downto 0), ts_count_i => ts_count, ts_source_i => trig_src, ts_always_i => HI, ts_disable_i => reg(R_CONTROL1)(CTL_TDC_CALIB), timeout_tick_i => tick(T_50kHz), strm_src_i => ZERO3, capture_mode_i => LO, packet_i => td_packet, pkt_valid_i => td_pkt_valid, pkt_rdack_o => td_pkt_rdack, lls_o => lls_o, lld_i => lld_i, full_o => open, overflow_o => open, underflow_o => open, data_count_o => open, en => trigdat_en, s40 => s40, clk => clk, rst => rst ); Ubcid : counter generic map ( BITS => 12, ROLLOVER_EN => 1, RST_IS_PRESET => 0 -- reset is preset ) port map ( inc_i => s40, clr_i => bcr_all, pre_i => LO, count_o => bcid, count_at_max_o => open, en_i => HI, rst => rst, clk => clk ); Ul0id : counter generic map ( BITS => 32, ROLLOVER_EN => 1, RST_IS_PRESET => 1 -- reset is preset ) port map ( inc_i => trig_all, clr_i => LO, pre_i => ecr_all, count_o => l0id, count_at_max_o => open, en_i => s40, rst => rst, clk => clk ); Utimestamp : counter generic map ( BITS => 40, ROLLOVER_EN => 1, RST_IS_PRESET => 0 -- reset is preset ) port map ( inc_i => HI, clr_i => LO, pre_i => LO, count_o => ts_count, count_at_max_o => open, en_i => s40_n, rst => LO, clk => clk ); Uedgedet : edgedet_sync generic map ( EN_ID => ENA_TRIG0 ) port map ( s40 => s40, async_i => lemo_trig_i, async_o => lemo_atrig, edgesync_o => trig_ext0, sync_o => open, ena_i => reg(R_IN_ENA), inv_i => reg(R_IN_INV), rst => rst, clk => clk ); Uedgedet1 : edgedet_sync generic map ( EN_ID => ENA_ECR ) port map ( s40 => s40, async_i => ecr_ins, async_o => open, edgesync_o => ecr_ext, sync_o => open, ena_i => reg(R_IN_ENA), inv_i => reg(R_IN_INV), rst => rst, clk => clk ); Uedgedet2 : edgedet_sync generic map ( EN_ID => ENA_BCR ) port map ( s40 => s40, async_i => lemo_bcr_i, async_o => open, edgesync_o => bcr_ext, sync_o => open, ena_i => reg(R_IN_ENA), inv_i => reg(R_IN_INV), rst => rst, clk => clk ); Ubusyextq : ff_d2 port map ( clk => clk, d => busy_ext_i, q1 => busy_ext_q, q2 => open ); Ubusyextq1 : ff_d2 port map ( clk => clk, d => busy, q1 => busy_all_o, q2 => open ); Utrigdelay : prog_delay generic map ( LEN => 256 ) port map ( strobe40_i => s40, delay_i => reg(R_TDELAY), sig_i => trig_all, dsig_o => trig40, rst => rst, clk => clk ); Uscgen_bcr : sercom_gen generic map ( LEN => 8, DATA => 2#10100101# ) port map ( strobe40_i => s40, ena_i => HI, go_i => bcr_ecb, com_o => bcr_genc, rst => rst, clk => clk ); Uscgen_ecr : sercom_gen generic map ( LEN => 8, DATA => 2#10100110# ) port map ( strobe40_i => s40, ena_i => HI, go_i => ecr_ecb, com_o => ecr_genc, rst => rst, clk => clk ); Ucbcrstrch : stretch1 port map ( clk => clk, i => command(CMD_BCR), o => bcr_cmd ); Ucecrstrch : stretch1 port map ( clk => clk, i => command(CMD_ECR), o => ecr_cmd ); Urwstrtstrch : stretch1 port map ( clk => clk, i => ocraw_start_i, o => ocraw_start40 ); Ustrch1 : stretch1 port map ( clk => clk, i => command(CMD_TRIG), o => trig_cmd0 ); Utrigostrch : stretch_sr port map ( i => pretrig, en => reg(R_CONTROL1)(CTL_PRETRIG_100), o8 => pretrig_o, o16 => open, clk => clk ); Utrigoutstretch : stretch_sr port map ( i => trig40, en => reg(R_CONTROL1)(CTL_TRIGOUT_100), o8 => trig_out_o, o16 => open, clk => clk ); g0: IF (TLU_EN = 1) GENERATE Uedgedet3 : edgedet_sync generic map ( EN_ID => ENA_TRIG1 ) port map ( s40 => s40, async_i => tlu_trig_i, async_o => open, edgesync_o => open, sync_o => tlu_trig_sync, ena_i => reg(R_IN_ENA), inv_i => reg(R_IN_INV), rst => rst, clk => clk ); Utluif : trig_tlu_if port map ( trig_tlu_o => trig_tlu, tlu_trig_sync_i => tlu_trig_sync, busy_tlu_o => busy_tlu, tlu_tclk_o => tlu_tclk_o, tog_i => tog, trid_tlu_o => trid_tlu, trid_valid_o => trid_valid, trid_new_o => trid_new, debug_trig_i => tlu_debug_trig_i, l0id16_i => l0id(15 downto 0), reg_tlu_ctl_i => reg(R_TLU_CTL), s40 => s40, clk => clk, rst => rst ); -- ModuleWare code(v1.12) for instance 'U_18' of 'or' tlu_debug_trig_i <= trig_cmd or trig_burster; -- ModuleWare code(v1.12) for instance 'U_34' of 'buff' tlu_ecr <= tlu_reset_i; -- ModuleWare code(v1.12) for instance 'U_36' of 'buff' tlu_busy_o <= busy; end generate g0; g2: IF (TLU_EN = 0) GENERATE -- ModuleWare code(v1.12) for instance 'U_35' of 'buff' tlu_ecr <= LO; -- HDL Embedded Text Block 5 eb5 -- eb5 5 tlu_tclk_o <= '0'; tlu_tclk_o <= '0'; trid_tlu <= (others => '0'); trid_valid <= '0'; trid_new <= '0'; trig_tlu <= '0'; busy_tlu <= '0'; end generate g2; end struct;