Generation Settings

Component declarationsyes
Configurationsin separate file
add pragmas
exclude view name

Declarations

Ports:

clk            : std_logic
rst            : std_logic
selected_str_o : std_logic_vector(7 DOWNTO 0)
s_lls_i        : t_llsrc_array(255 DOWNTO 0)
lld_i          : std_logic
lls_o          : t_llsrc
s_lld_o        : std_logic_vector(255 DOWNTO 0)

Diagram Signals:

signal sel            : std_logic_vector(7 DOWNTO 0)
signal freeze         : std_logic

Pre User:



Post User:




Package List


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;


Bundles