-- VHDL Entity locallink.ll_syncmux256.symbol
--
-- Created:
--          by - warren.warren (mbb)
--          at - 21:20:57 07/31/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;

entity ll_syncmux256 is
   port(
      clk            : in     std_logic;
      lld_i          : in     std_logic;
      rst            : in     std_logic;
      s_lls_i        : in     t_llsrc_array (255 downto 0);
      lls_o          : out    t_llsrc;
      s_lld_o        : out    std_logic_vector (255 downto 0);
      selected_str_o : out    std_logic_vector (7 downto 0)
   );

-- Declarations

end ll_syncmux256 ;

--
-- VHDL Architecture locallink.ll_syncmux256.struct
--
-- Created:
--          by - warren.warren (mbb)
--          at - 21:20:57 07/31/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library utils;
use utils.pkg_types.all;

library hsio;
use hsio.pkg_core_globals.all;


architecture struct of ll_syncmux256 is

   -- Architecture declarations

   -- Internal signal declarations
   signal freeze : std_logic;
   signal sel    : std_logic_vector(7 downto 0);


   -- Component Declarations
   component ll_mux_ctrl256
   port (
      s_lls_i   : in     t_llsrc_array (255 downto 0);
      s_lldr_o  : out    std_logic_vector (255 downto 0);
      dst_rdy_i : in     std_logic ;
      freeze_o  : out    std_logic ;
      sel_o     : out    std_logic_vector (7 downto 0);
      rst       : in     std_logic ;
      clk       : in     std_logic
   );
   end component;
   component ll_smx256
   port (
      clk      : in     std_logic;
      freeze_i : in     std_logic;
      rst      : in     std_logic;
      s_lls_i  : in     t_llsrc_array (255 downto 0);
      sel_i    : in     std_logic_vector (7 downto 0);
      lls_o    : out    t_llsrc
   );
   end component;


begin

   -- ModuleWare code(v1.12) for instance 'U_0' of 'buff'
   selected_str_o <= sel;

   -- Instance port mappings.
   Umuxctrl : ll_mux_ctrl256
      port map (
         s_lls_i   => s_lls_i,
         s_lldr_o  => s_lld_o,
         dst_rdy_i => lld_i,
         freeze_o  => freeze,
         sel_o     => sel,
         rst       => rst,
         clk       => clk
      );
   Usmx256 : ll_smx256
      port map (
         lls_o    => lls_o,
         s_lls_i  => s_lls_i,
         freeze_i => freeze,
         sel_i    => sel,
         clk      => clk,
         rst      => rst
      );

end struct;