Generation Settings

Declarations

Ports:

rst              : std_logic
clk              : std_logic
bcid_i           : std_logic_vector(11 DOWNTO 0) bus
l1id_i           : std_logic_vector(23 DOWNTO 0) bus
strm_reg_i       : std_logic_vector(15 downto 0)
strm_cmd_i       : std_logic_vector(15 downto 0)
capture_start_i  : std_logic
trig80_i         : std_logic
--ht_delta_max_i   : in  slv6;
busy_o           : std_logic
lld_i            : std_logic
--out
lls_o            : t_llsrc
-- registers
reg              : t_reg_bus
tick             : std_logic_vector(MAX_TICTOG downto 0)
-- stats
req_stat_i       : std_logic
gen13data_i      : slv2_array(1 downto 0)
gen13data80_i    : slv2_array(1 downto 0)
sim13data_i      : slv2_array(1 downto 0)
s40              : std_logic
s20_i            : std_logic
-- In
link4x_i         : slv4

Diagram Signals:

signal HI               : std_logic
signal LO               : std_logic
signal histo_en         : std_logic
signal strm_src         : std_logic_vector(2 DOWNTO 0)
signal capture_mode     : std_logic
signal deser_en         : std_logic
-- deser monitoring
signal dropped_pkts     : std_logic_vector(7 downto 0)
signal gendata_sel      : std_logic
signal strm_mode        : std_logic_vector(1 DOWNTO 0)
signal strm_reset       : std_logic
signal strm_en          : std_logic
signal strm_histo_ro    : std_logic
signal busy_en_fifo     : std_logic
signal busy_en_delta    : std_logic
signal data_count       : std_logic_vector(1 downto 0)
-- locallink tx interface
signal r_lls            : t_llsrc_array(3 DOWNTO 0)
signal r_lld            : std_logic_vector(3 DOWNTO 0)
signal reg_len0         : std_logic_vector(15 downto 0)
signal histo_debug_mode : std_logic
signal reg_busy_delta   : std_logic_vector(15 downto 0)
-- In
signal ser0             : slv2
signal LOLO             : std_logic_vector(1 downto 0)
signal HIHI             : std_logic_vector(1 downto 0)
signal HILO             : std_logic_vector(1 downto 0)
signal LOHI             : std_logic_vector(1 downto 0)
signal ser13data_i      : slv2
signal fifo_full        : std_logic
signal fifo_overflow    : std_logic
signal fifo_underflow   : std_logic
-- Pkt Out
signal packet           : slv64 --t_packet;
signal pkt_valid        : std_logic
signal pkt_rdack        : std_logic
signal mode_abc         : std_logic
signal ts_count         : std_logic_vector(39 downto 0)
signal s40_n            : std_logic
signal ZERO16           : std_logic_vector(15 downto 0)
signal ZERO4            : std_logic_vector(3 downto 0)
signal mode320          : std_logic
signal deser_mode       : std_logic_vector(1 downto 0)

Pre User:

Post User:

Package List

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY UNISIM;
USE UNISIM.VComponents.all;
library utils;
use utils.pkg_types.all;
library hsio;
use hsio.pkg_core_globals.all;

Bundles